Alexandre Honorat Ingénieur de recherche dans l'équipe STEEP.

Identifiants chercheurs

IdHAL :

alexandre-honorat

ORCID :

0000-0001-5875-7258

IdRef :

25313594X

Publications

Article dans une revue (4)

Graph Transformations for Memory Peak Minimization by Scheduling Pascal Fradet,Alain Girault,Alexandre Honorat ACM Transactions on Embedded Computing Systems (TECS), 2025, pp.1-36. ⟨10.1145/3707206⟩ Article dans une revue hal-04816271v1
Real-Time Fixed Priority Scheduling Synthesis using Affine DataFlow Graphs: from Theory to Practice Alexandre Honorat,Hai Nam Tran,Thierry Gautier,Loïc Besnard,Shuvra S. Bhattacharyyaet al. ACM Transactions on Embedded Computing Systems (TECS), 2025, 24 (3), pp.45. ⟨10.1145/3615586⟩ Article dans une revue hal-04200195v1
Automated Buffer Sizing of Dataflow Applications in a High-Level Synthesis Workflow Alexandre Honorat,Mickaël Dardaillon,Hugo Miomandre,Jean-François Nezan ACM Transactions on Reconfigurable Technology and Systems (TRETS), 2024, 17 (1), pp.1-26. ⟨10.1145/3626103⟩ Article dans une revue hal-04237266v1
Polychronous automata and their use for formal validation of AADL models Thierry Gautier,Clément Guy,Alexandre Honorat,Paul Le Guernic,Jean-Pierre Talpinet al. Frontiers of Computer Science, 2019, 13 (4), pp.677-697. ⟨10.1007/s11704-017-6134-5⟩ Article dans une revue hal-01411257v1

Communication dans un congrès (10)

Parallel scheduling of task graphs with minimal memory requirements Pascal Fradet,Alain Girault,Alexandre Honorat IPDPS 2025 - 39th IEEE International Parallel and Distributed Processing Symposium, Jun 2025, Milano, Italy. pp.1-12 Communication dans un congrès hal-04879748v1
Sequential Scheduling of Dataflow Graphs for Memory Peak Minimization Pascal Fradet,Alain Girault,Alexandre Honorat LCTES 2023 - 24th ACM SIGPLAN/SIGBED International Conference on Languages, Compilers, and Tools for Embedded Systems, Jun 2023, Orlando (FL), United States. pp.76-86, ⟨10.1145/3589610.3596280⟩ Communication dans un congrès hal-04163123v1
Influence of Dataflow Graph Moldable Parameters on Optimization Criteria Alexandre Honorat,Thomas Bourgoin,Hugo Miomandre,Karol Desnos,Daniel Menardet al. DASIP 2022 - Workshop on Design and Architectures for Signal and Image Processing, Jun 2022, Budapest, Hungary. pp.83-95, ⟨10.1007/978-3-031-12748-9_7⟩ Communication dans un congrès hal-03752645v1
A Framework for Fixed Priority Periodic Scheduling Synthesis from Synchronous Data-flow Graphs Hai Nam Tran,Alexandre Honorat,Shuvra S Bhattacharyya,Jean-Pierre Talpin,Thierry Gautieret al. SAMOS XXI 2021 - 21st International Conference on embedded computer Systems: Architectures, MOdeling and Simulation, Jul 2021, Virtual, France. pp.1-12 Communication dans un congrès hal-03488217v1
Scheduling of Synchronous Dataflow Graphs with Partially Periodic Real-Time Constraints Alexandre Honorat,Karol Desnos,Shuvra S Bhattacharyya,Jean-François Nezan Real-Time Networks and Systems, Jun 2020, Paris, France. ⟨10.1145/3394810.3394820⟩ Communication dans un congrès hal-02883663v1
A Fast Heuristic to Pipeline SDF Graphs Alexandre Honorat,Karol Desnos,Mickaël Dardaillon,Jean-François Nezan Embedded Computer Systems: Architectures, Modeling, and Simulation, Jul 2020, Pythagorion, Samos Island, Greece. pp.139-151, ⟨10.1007/978-3-030-60939-9_10⟩ Communication dans un congrès hal-02993338v1
Modeling Nested for Loops with Explicit Parallelism in Synchronous DataFlow Graphs Alexandre Honorat,Karol Desnos,Maxime Pelcat,Jean-François Nezan Embedded Computer Systems: Architectures, Modeling, and Simulation, Jul 2019, Pythagorion, Samos Island, Greece. pp.269-280, ⟨10.1007/978-3-030-27562-4_19⟩ Communication dans un congrès hal-02267487v2
Efficient Contention-Aware Scheduling of SDF Graphs on Shared Multi-bank Memory Hai Nam Tran,Alexandre Honorat,Jean-Pierre Talpin,Thierry Gautier,Loïc Besnard ICECCS 2019 - 24th International Conference on Engineering of Complex Computer Systems, Nov 2019, Hong Kong, China. pp.114-123, ⟨10.1109/ICECCS.2019.00020⟩ Communication dans un congrès hal-02193639v2
ADFG: a scheduling synthesis tool for dataflow graphs in real-time systems Alexandre Honorat,Hai Nam Tran,Loïc Besnard,Thierry Gautier,Jean-Pierre Talpinet al. International Conference on Real-Time Networks and Systems , Oct 2017, Grenoble, France. pp.1-10, ⟨10.1145/3139258.3139267⟩ Communication dans un congrès hal-01615142v1
A Stencil DSEL for Single Code Accelerated Computing with SYCL Olivier Aumage,Denis Barthou,Alexandre Honorat SYCL 2016 1st SYCL Programming Workshop during the 21st ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, Mar 2016, Barcelone, Spain Communication dans un congrès hal-01290099v1

Rapport (1)

Graph Transformations for Memory Peak Minimization by Scheduling Pascal Fradet,Alain Girault,Alexandre Honorat RR-9554, Inria - Research Centre Grenoble – Rhône-Alpes. 2024, pp.1-42 Rapport (rapport de recherche) hal-04688921v1

Thèse (1)

Modeling, Scheduling, Pipelining and Configuration of Synchronous Dataflow Graphs with Throughput Constraints Alexandre Honorat Signal and Image processing. INSA de Rennes, 2020. English. ⟨NNT : 2020ISAR0010⟩ Thèse tel-03337988v1