Bruno FERRES

Publications

Communication dans un congrès (5)

Collaborative Action on Timing InterferenCes: Summary and Perspectives at Mid-term Claire Maiza,Lionel Rieg,Mihail Asavoae,Jean-Luc Béchennec,Dominique Blouinet al. ERTS 2026 - Embedded Real-Time Systems, Feb 2026, Toulouse, France. pp.1-11, ⟨10.82331/ERTS.2026.27⟩ Communication dans un congrès hal-05465745v1
Communication and Shared Memory Efficient Mapping Techniques of Real-Time DAGs upon Clustered Multicore Platforms Matheus Schuh,Claire Maiza,Pascal Raymond,Bruno Ferres,Joël Goossenset al. 33rd International Conference on Real-Time Networks and Systems, Nov 2025, Pise, Italy Communication dans un congrès hal-05289989v1
A Transistor Level Relational Semantics for Electrical Rule Checking by SMT Solving Oussama Oulkaid,Bruno Ferres,Matthieu Moy,Pascal Raymond,Mehdi Khosravianet al. Design, Automation and Test in Europe Conference, Mar 2024, Valencia, Spain. pp.1-6, ⟨10.23919/DATE58400.2024.10546537⟩ Communication dans un congrès hal-04527225v1
Electrical Rule Checking of Integrated Circuits using Satisfiability Modulo Theory Bruno Ferres,Oussama Oulkaid,Ludovic Henrio,M. Khosravian G.,Matthieu Moyet al. DATE 2023 - Design, Automation and Test in Europe Conference, Apr 2023, Anvers (Antwerpen), Belgium. pp.1-2, ⟨10.23919/DATE56975.2023.10137147⟩ Communication dans un congrès hal-04007446v1
Integrating Quick Resource Estimators in Hardware Construction Framework for Design Space Exploration Bruno Ferres,Olivier Muller,Frédéric Rousseau 2021 IEEE International Workshop on Rapid System Prototyping (RSP), Oct 2021, Paris, France. pp.64-70, ⟨10.1109/RSP53691.2021.9806276⟩ Communication dans un congrès hal-03724027v1

Article dans une revue (3)

Modeling Techniques for the Formal Verification of Integrated Circuits at Transistor-Level: Performance vs. Precision Trade-offs Oussama Oulkaid,Bruno Ferres,Matthieu Moy,Pascal Raymond,Mehdi Khosravian IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2025, ⟨10.1109/TCAD.2025.3608647⟩ Article dans une revue hal-05290989v1
A Survey on Transistor-Level Electrical Rule Checking of Integrated Circuits Bruno Ferres,Oussama Oulkaid,Matthieu Moy,Gabriel Radanne,Ludovic Henrioet al. ACM Transactions on Design Automation of Electronic Systems, 2025, ⟨10.1145/3748327⟩ Article dans une revue hal-05185119v1
A Chisel Framework for Flexible Design Space Exploration through a Functional Approach Bruno Ferres,Olivier Muller,Frédéric Rousseau ACM Transactions on Design Automation of Electronic Systems, 2023, 28 (4), pp.1-31. ⟨10.1145/3590769⟩ Article dans une revue hal-04298227v1

Poster de conférence (2)

Electrical Rule Checking of Integrated Circuits using Satisfiability Modulo Theory Bruno Ferres,Oussama Oulkaid,Ludovic Henrio,Mehdi Khosravian,Matthieu Moyet al. Colloque du GDR SoC2, Jun 2023, Lyon, France Poster de conférence hal-04750092v1
Chisel Usecase: Designing General Matrix Multiply for FPGA Bruno Ferres,Olivier Muller,Frédéric Rousseau Fernando Rincón, Jesús Barba, Hayden K. H. So, Pedro Diniz, Julián Caba. Applied Reconfigurable Computing. Architectures, Tools, and Applications (ARC 2020), Apr 2020, Toledo, Spain. Springer, Applied Reconfigurable Computing. Architectures, Tools, and Applications 16th International Symposium, ARC 2020, Toledo, Spain, April 1–3, 2020, Proceedings, pp.61-72, Lecture Notes in Computer Science. ⟨10.1007/978-3-030-44534-8_5⟩ Poster de conférence hal-03082750v1

Thèse (1)

Leveraging Hardware Construction Languages for Flexible Design Space Exploration on FPGA Bruno Ferres Micro and nanotechnologies/Microelectronics. Université Grenoble Alpes [2020-..], 2022. English. ⟨NNT : 2022GRALT025⟩ Thèse tel-03709710v1