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Sylvain Feruglio
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- feruglio
- 0000-0002-6444-2671
- IdRef : 098578944
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FPGA implementation of reconfigurable ADPLL network for distributed clock generationFTP 2011 - International Conference on Field Programmable Technology, Dec 2011, New Delhi, India. pp.1-4, ⟨10.1109/FPT.2011.6132670⟩
Communication dans un congrès
hal-01053755v1
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