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Giorgio Di Natale

12
Documents

Présentation

Giorgio Di Natale received the PhD in Computer Engineering from the Politecnico di Torino in 2003. He is director of research for the National Research Center of France at the TIMA laboratory in Grenoble. His research interests include hardware security and trust, secure circuits design and test, reliability evaluation and fault tolerance, software implemented hardware fault tolerance, and VLSI testing.

Publications

paolo-maistri

Internal State Monitoring in RISC-V Microarchitectures for Security Purpose

Roua Boulifa , Giorgio Di Natale , Paolo Maistri
25th IEEE Latin American Test Symposium (LATS 2024), Apr 2024, Maceio (Brazil), Brazil
Communication dans un congrès hal-04513607v1
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Non-Invasive Attack on Ring Oscillator-based PUFs through Localized X-Ray Irradiation

Nasr-Eddine Ouldei Tebina , Aghiles Douadi , Luc Salvo , Vincent Beroulle , Nacer-Eddine Zergainoh
IEEE International Symposium on Hardware Oriented Security and Trust (HOST 2024), May 2024, Washington, DC, United States
Communication dans un congrès hal-04521587v1
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Experimental Evaluation of Delayed-Based Detectors Against Power-off Attack

Maryam Esmaeilian , Aghiles Douadi , Zahra Kazemi , Vincent Beroulle , Mirbaha Amir-Pasha
IEEE 29th International Symposium on On-Line Testing and Robust System Design (IOLTS 2023), Jul 2023, Crete, Greece. ⟨10.1109/IOLTS59296.2023.10224876⟩
Communication dans un congrès hal-04193277v1
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A Study of High Temperature Effects on Ring Oscillator based Physical Unclonable Functions

Aghiles Douadi , Giorgio Di Natale , Paolo Maistri , Ioana Vatajelu , Vincent Beroulle
29th IEEE International Symposium on On-Line Testing and Robust System Design (IOLTS 2023), Jul 2023, Chania, Greece
Communication dans un congrès hal-04169632v1
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Security EDA Extension through P1687.1 and 1687 Callbacks

Michele Portolan , V. Reynaud , Paolo Maistri , Régis Leveugle , Giorgio Di Natale
IEEE International Test Conference (ITC 2021), Oct 2021, Anaheim (CA), United States. pp.344-353, ⟨10.1109/ITC50571.2021.00050⟩
Communication dans un congrès hal-03629319v1
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A Comprehensive Approach to a Trusted Test Infrastructure

Marc Merandat , Vincent Reynaud , Emanuele Valea , Jerome Quevremont , Nicolas Valette
IVSW 2019 - 4th IEEE International Verification and Security Workshop, Jul 2019, Rhodes, Greece. pp.43-48, ⟨10.1109/IVSW.2019.8854428⟩
Communication dans un congrès lirmm-02306980v1
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The case of using CMOS FD-SOI rather than CMOS bulk to harden ICs against laser attacks

Jean-Max Dutertre , Vincent Beroulle , Philippe Candelier , Louis-Barthelemy Faber , Marie-Lise Flottes
IOLTS: International On-Line Testing Symposium, Jul 2018, Platja d’Aro, Spain. pp.214-219, ⟨10.1109/IOLTS.2018.8474230⟩
Communication dans un congrès emse-01856000v1
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Laser fault injection at the CMOS 28 nm technology node: an analysis of the fault model

Jean-Max Dutertre , Vincent Beroulle , Philippe Candelier , Stephan de Castro , Louis-Barthelemy Faber
FDTC: Fault Diagnosis and Tolerance in Cryptography, Sep 2018, Amsterdam, Netherlands. pp.1-6, ⟨10.1109/FDTC.2018.00009⟩
Communication dans un congrès emse-01856008v1
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Laser-Induced Fault Effects in Security-Dedicated Circuits

Vincent Beroulle , Philippe Candelier , Stephan de Castro , Giorgio Di Natale , Jean-Max Dutertre
VLSI-SoC: Very Large Scale Integration and System-on-Chip, Oct 2014, Playa del Carmen, Mexico. pp.220-240, ⟨10.1007/978-3-319-25279-7_12⟩
Communication dans un congrès hal-01383737v1
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Ensuring High Testability without Degrading Security

Marie-Lise Flottes , Giorgio Di Natale , Paolo Maistri , Bruno Rouzeyre , Régis Leveugle
ETS: European Test Symposium, May 2009, Seville, Spain
Communication dans un congrès lirmm-00407163v1