Jean-Christophe Le Lann
Présentation
I am researcher and lecturer ("enseignant-chercheur") at ENSTA-Bretagne, an engineering school located in Brest, France. I am also member of LabSticc , a major research laboratory in France. My main research activities are related to Hardware-software Codesign of Embedded Systems and Cyber-physical systems (CPS) : modeling, DSL design, transformation, simulation, compilation onto real architectures organized around a network of processing elements like RISC processors, FPGAs, multicores, sensors and actuators. All these topics have no meaning without another keyword : Models of Computation (MoCs). As Wikipedia explains : in model-driven engineering, the model of computation explains how the behaviour of the whole system is the result of the behaviour of each of its components. I am involved in many concrete designs in the field of multimedia, communication and robotics, that ensure that my research is still rooted in the ground. I spent 10 years as IC Design Engineer for Thomson R & D France (now Technicolor) and I am cofounder of Modae Technologies, that delivered a high-level modeling, simulation and behavioral synthesis framework for FPGAs starting from Python and Ruby DSLs, as a possible alternative to Matlab/Simulink. Modae was awarded twice by the French Ministry of Research and OSEO (now Bpi France).
Publications
Publications
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Detection of AIS Messages Falsifications and Spoofing by Checking Messages Compliance with TDMA ProtocolDigital Signal Processing, 2023, 136, pp.103983. ⟨10.1016/j.dsp.2023.103983⟩ |
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Extended overlay architectures for heterogeneous FPGA cluster managementJournal of Systems Architecture, 2017, 78, pp.1-14. ⟨10.1016/j.sysarc.2017.06.001⟩ |
Model-Driven Toolset for Embedded Reconfigurable Cores: Flexible Prototyping and Software-like DebuggingScience of Computer Programming, 2014, pp.1. ⟨10.1016/j.scico.2014.02.015⟩ |
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Polychrony for system designJournal of Systems Architecture, 2002, 12, pp.261--304 |
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An Iterative Design and Validation Methodology for RISC-V Custom ExtensionInternational Conference on Electronics Circuits and Systems, Nov 2025, Marrakech, Morocco |
Efficient Hardware Primitives for Interval Contractors in Robotics and Integration to a Custom RISC-V ISA Extension2025 23rd IEEE Interregional NEWCAS Conference (NEWCAS), Jun 2025, Paris, France. pp.548-552, ⟨10.1109/NewCAS64648.2025.11107029⟩ |
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An HLS algorithm for the direct synthesis of complex control flow graphs into finite state machines with implicit datapath27th Euromicro Conference Series on Digital System Design, Aug 2024, Paris, France |
Acceleration of contractor algebra on RISCV in the context of mobile roboticSummer Workshop on Interval Methods, Jun 2023, Angers, France |
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HLS-based Accelerated Simulation of Large Scale Cyber-Physical Systems on FPGAsIEEE International NEWCAS Conference, Jul 2022, Montreal, Canada. ⟨10.1109/NEWCAS52662.2022.9842250⟩ |
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Stratégie de détection des Falsifications des Positions des Messages AIS Basée sur l'Application du Filtre IMMGretsi'22 XXVIIIème Colloque Francophone de Traitement du Signal et des Images, Sep 2022, Nancy, France |
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A new interval arithmetic to generate the complementary of contractorsSummer Workshop on Interval Methods, Jul 2022, Hannover, Germany |
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Émulation de Systèmes Cyber-Physiques sur FPGAGRETSI'22 XXVIIIème Colloque Francophone de Traitement du Signal et des Images, Sep 2022, Nancy, France. pp.481-484 |
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Opportunistic IP Birthmarking using Side Effects of Code Transformations on High-Level SynthesisDATE'21 Design Automation and Test in Europe, Feb 2021, Grenoble (virtuel), France |
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Towards a Hardware DSL Ecosystem: RubyRTL and FriendsOSDA'2020 Open Source Hardware Design, colocated with DATE'20, Mar 2020, Grenoble, France |
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Transient Key-based Obfuscation for HLS in an Untrusted Cloud Environment2019 Design, Automation & Test in Europe Conference & Exhibition, DATE 2019, Mar 2019, Florence, Italy |
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LiteX: an open-source SoC builder and library based on Migen Python DSLOSDA 2019, colocated with DATE 2019 Design Automation and Test in Europe, Mar 2019, Florence, Italy |
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An Integrated Toolchain for Overlay-centric System-on-chip13th International Symposium on Reconfigurable Communication-centric Systems-on-Chip 2018 (ReCoSoC 2018), Jul 2018, Lille, France. ⟨10.1109/ReCoSoC.2018.8449388⟩ |
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Soft timing closure for soft programmable logic cores: The ARGen approachARC 2017 - 13th International Symposium on Applied Reconfigurable Computing, Delft University of Technology Apr 2017, Delft, Netherlands |
A Cost-effective Approach for Efficient Time-sharing of Reconfigurable ArchitecturesFPGA4GPC'2017, May 2017, Hambourg, Germany. ⟨10.1109/FPGA4GPC.2017.8008959⟩ |
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Overlay Architectures For FPGA Resource VirtualizationGDR SOC SIP, Jun 2016, Nantes, France |
Speeding Up Robot Control Software Through Seamless Integration With FPGASHARC'16, Jun 2016, Brest, France |
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Overlay Architectures for Heterogeneous FPGA Cluster Management.DASIP 2016, Oct 2016, Rennes, France |
ZeFF : Une plateforme pour l’intégration d’architectures overlay dans le CloudCOMPAS 2016, Jul 2016, Lorient, France |
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CaRDIN: An Agile Environment for EdgeComputing on Reconfigurable Sensor Networks3rd IEEE International Conference on Computational Science and Computational Intelligence (CSCI 2016), Dec 2016, Las Vegas, United States |
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Communication-aware Parallelization Strategies for High Performance Applications.ISVLSI'15 - IEEE Computer Society Annual Symposium on VLSI, Jul 2015, Montpellier, France |
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A High-Level Programming Model to Ease Pipeline Parallelism Expression On Shared Memory Multicore ArchitecturesHPC 2014, Apr 2014, Tampa, FL, United States. pp.XX |
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A Prototyping Platform for Virtual Reconfigurable UnitsRECOSOC 2014, May 2014, Montpellier, France |
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Tackling Real-Time Signal Processing Applications on Shared Memory Multicore Architectures Using XPUERTS 2014, Feb 2014, Toulouse, France |
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DESIGN AND IMPLEMENTATION OF A CACHE HIERARCHY-AWARE TASK SCHEDULING FOR PARALLEL LOOPS ON MULTICORE ARCHITECTURESPDCTA 2014, Feb 2014, Sydney, Australia |
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Early exploring design alternatives of smart sensor software with Model of Computation implemented with actorsESUG 2013 - 21th International Smalltalk Conference, Sep 2013, Annecy, France |
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Modélisation algorithmique et synthèse d'architectures assistées par model-checkingCAL 2012-, May 2012, Montpellier, France |
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MHPM : Multi-Scale Hybrid Programming Model A flexible parallelization MedthodologyHPCC 2012, Jun 2012, Liverpool, United Kingdom |
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AN EXPERIMENTAL TOOLCHAIN BASED ON HIGH-LEVEL DATAFLOW MODELS OF COMPUTATION FOR HETEROGENEOUS MPSOCDASIP, Oct 2012, Karlsruhe, Germany |
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From system-level models to heterogeneous embedded systemsRITF 2012 - Recherche et Innovation pour les Transports du Futur, Nov 2012, Paris, France. pp.XX |
MoPCoM Methodology: Focus on Models of Computation6th European Conference on Modelling Foundations and Applications (ECMFA'10), Jun 2010, Paris, France. pp.Non renseigne |
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JOG : une approche haut niveau des systèmes embarqués via Armadeus et Java3èmes Journées Démonstrateurs 2010, Nov 2010, Angers, France |
UML/MARTE Process for SoC/SoPCEmbedded Real Time Software and Systems Symposium, 2010, Toulouse, France. pp.201,209 |
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Using MARTE in the MOPCOM SoC/SoPC MethodologyWorkshop MARTE, Colocated with DATE, Mar 2008, Munich, Germany |
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Using MARTE in a Co-Design MethodologyMARTE UML profile workshop co-located with DATE'08, Mar 2008, Munich, Germany. 6 p |
CDFG Platform in MORPHEUSAETHER - MORPHEUS Workshop AMWAS'07, Oct 2007, Paris, France |
Protecting Behavioral IPs During Design Time: Key-Based Obfuscation Techniques for HLS in the CloudBehavioral Synthesis for Hardware Security, Springer International Publishing; Springer International Publishing, pp.71-93, 2022, ⟨10.1007/978-3-030-78841-4_5⟩ |
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XPU: A C++ Metaprogramming Approach to Ease Parallelism Expression: Parallelization Methodology, Internal Design and Practical ApplicationParallel Programming: Practical Aspects, Models and Current Limitations, NOVA publishers, pp.175-198, 2014, 978-1-60741-263-2 |
Procédé de configuration d'un circuit logique programmable, circuit logique programmable et dispositif pour implémenter le procédéFrance, N° de brevet: FR3115134. 2022 |
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Context adaptive arithmetic decoding method and deviceFrance, Patent n° : WO2007118811. 2007, pp.24 |
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Polychrony for system design[Research Report] RR-4715, INRIA. 2003 |
Simulation et synthèse de circuits s'appuyant sur le Modèle SynchroneInformatique [cs]. Université de rennes 1, 2002. Français. ⟨NNT : ⟩ |
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Contributions aux méthodologies et outils de conception des System-on-Chip : capture applicative, architecture et sécuritéIngénierie assistée par ordinateur. Université de Bretagne Occidentale, 2025 |