Jean-Luc Danger
Publications
Publications
|
|
Multi-Sensor Data Fusion for Enhanced Detection of Laser Fault Injection Attacks in Cryptographic Hardware: Practical Results2025 Design, Automation & Test in Europe Conference (DATE), Mar 2025, Lyon, France. pp.1 - 2, ⟨10.23919/date64628.2025.10992902⟩ |
|
|
Robust and Reliable PUF Protocol Exploiting Non-Monotonic Quantization and Neyman-Pearson LemmaCASCADE 2025, Apr 2025, St-Étienne, France |
TEE-Time: A Dynamic Cache Timing Analysis Tool for Trusted Execution Environments2024 25th International Symposium on Quality Electronic Design (ISQED), Apr 2024, San Francisco, California, United States. pp.1-8, ⟨10.1109/ISQED60706.2024.10528744⟩ |
|
|
|
EM Fault Injection-Induced Clock Glitches: From Mechanism Analysis to Novel Sensor Design30th IEEE International Symposium on On-Line Testing and Robust System Design (IOLTS) (2024), Jul 2024, Rennes, France. ⟨10.1109/IOLTS60994.2024.10616074⟩ |
High-Order Collision Attack Vulnerabilities in Montgomery Ladder Implementations of RSASPACE, Dec 2023, Roorkee, India, India. pp.139-161, ⟨10.1007/978-3-031-51583-5_9⟩ |
|
|
|
A Tale of Two Models: Discussing the Timing and Sampling EM Fault Injection ModelsFDTC 2023 – Twentieth Workshop on Fault Diagnosis and Tolerance in Cryptography, Sep 2023, Prague, Czech Republic |
|
|
Aging-Induced Failure Prognosis via Digital SensorsGLSVLSI '23: Great Lakes Symposium on VLSI 2023, Jun 2023, Knoxville TN USA, United States. pp.703-708, ⟨10.1145/3583781.3590204⟩ |
|
|
Special Session: Security Verification & Testing for SR-Latch TRNGs2023 IEEE 41st VLSI Test Symposium (VTS), Apr 2023, San Diego, United States. pp.1-10, ⟨10.1109/VTS56346.2023.10140057⟩ |
|
|
Reliability of ring oscillator PUFs with reduced helper data18th International Workshop on Security (IWSEC 2023), Aug 2023, Yokohama, Japan |
A gem5 based Platform for Micro-Architectural Security AnalysisHASP '23: Hardware and Architectural Support for Security and Privacy 2023, Oct 2023, Toronto Canada, Canada. pp.91-99, ⟨10.1145/3623652.3623674⟩ |
|
|
|
Highlighting Two EM Fault Models While Analyzing a Digital Sensor Limitations2023 Design, Automation & Test in Europe Conference & Exhibition (DATE), Apr 2023, Antwerp, Belgium. pp.1-2, ⟨10.23919/DATE56975.2023.10137124⟩ |
|
|
Challenges in Generating True Random Numbers Considering the Variety of Corners, Aging, and Intentional Attacks2023 International Conference on IC Design and Technology (ICICDT), Sep 2023, Tokyo, Japan. pp.10-15, ⟨10.1109/ICICDT59917.2023.10332319⟩ |
Here comes SAID: A SOME/IP Attention-based mechanism for Intrusion Detection2023 Fourteenth International Conference on Ubiquitous and Future Networks (ICUFN), Jul 2023, Paris, France. pp.462-467, ⟨10.1109/ICUFN57995.2023.10200508⟩ |
|
RISC-V Extension for Lightweight Cryptography, Protection against SCAWorkshop on Practical Hardware Innovations in Security Implementation and Characterization (PHISIC 2022), May 2022, Gardanne, France |
|
SASIMI: Evaluation Board for EM Information Leakage from Large Scale Cryptographic Circuits2022 IEEE International Symposium on Electromagnetic Compatibility & Signal/Power Integrity (EMCSI), Aug 2022, Spokane, United States. pp.299-302, ⟨10.1109/EMCSI39492.2022.9889445⟩ |
|
|
|
On the Practicality of Relying on Simulations in Different Abstraction Levels for Pre-silicon Side-Channel Analysis19th International Conference on Security and Cryptography, Jul 2022, Lisbon, Portugal. pp.661-668, ⟨10.5220/0011307600003283⟩ |
Parasite: Mitigating Physical Side-Channel Attacks Against Neural NetworksSPACE, Dec 2021, Calcutta, India, India. pp.148-167, ⟨10.1007/978-3-030-95085-9_8⟩ |
|
|
|
Detecting Laser Fault Injection Attacks via Time-to-Digital Converter Sensors2022 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), Jun 2022, McLean, United States. pp.97-100, ⟨10.1109/HOST54066.2022.9840318⟩ |
|
|
Unsupervised Network Intrusion Detection System for AVTP in Automotive Ethernet Networks2022 IEEE Intelligent Vehicles Symposium (IV), Jun 2022, Aachen, Germany. pp.1731-1738, ⟨10.1109/IV51971.2022.9827285⟩ |
|
|
Cache-Timing Attack on the SEAL Homomorphic Encryption Library11th International Workshop on Security Proofs for Embedded Systems (PROOFS 2022), Sep 2022, Leuven, Belgium |
|
|
CAN-BERT do it? Controller Area Network Intrusion Detection System based on BERT Language Model2022 IEEE/ACS 19th International Conference on Computer Systems and Applications (AICCSA), Dec 2022, Abu Dhabi, United Arab Emirates. pp.1-8, ⟨10.1109/AICCSA56895.2022.10017800⟩ |
|
|
Leakage Power Analysis in Different S-Box Masking Protection Schemes2022 Design, Automation & Test in Europe Conference & Exhibition (DATE), Mar 2022, Antwerp, Belgium. pp.1263-1268, ⟨10.23919/DATE54114.2022.9774763⟩ |
Making Obfuscated PUFs Secure Against Power Side-Channel Based Modeling Attacks2021 Design, Automation & Test in Europe Conference & Exhibition (DATE), Feb 2021, Grenoble, France. pp.1000-1005, ⟨10.23919/DATE51398.2021.9474137⟩ |
|
|
|
Laser Fault Injection in a 32-bit Microcontroller: from the Flash Interface to the Execution Pipeline2021 Workshop on Fault Detection and Tolerance in Cryptography (FDTC), Sep 2021, Milan, Italy. pp.74-85, ⟨10.1109/FDTC53659.2021.00020⟩ |
RSM Protection of the PRESENT Lightweight Cipher as a RISC-V Extension2021 24th Euromicro Conference on Digital System Design (DSD), Sep 2021, Palermo, Italy. pp.325-332, ⟨10.1109/DSD53832.2021.00056⟩ |
|
|
|
SOME/IP Intrusion Detection using Deep Learning-based Sequential Models in Automotive Ethernet NetworksIEEE IEMCON 2021, Oct 2021, Vancouver, Canada |
Water- PUF: An Insider Threat Resistant PUF Enrollment Protocol Based on Machine Learning Watermarking2021 IEEE 20th International Symposium on Network Computing and Applications (NCA), Nov 2021, Boston, United States. pp.1-10, ⟨10.1109/NCA53618.2021.9685239⟩ |
|
|
|
Analysis of a Laser-induced Instructions Replay Fault Model in a 32-bit Microcontroller2021 24th Euromicro Conference on Digital System Design (DSD), Sep 2021, Palermo, Italy. pp.363-370, ⟨10.1109/DSD53832.2021.00061⟩ |
Processor Anchor to Increase the Robustness Against Fault Injection and Cyber AttacksConstructive Side-Channel Analysis and Secure Design. COSADE 2020, Apr 2020, Lugano, Switzerland. pp.254-274, ⟨10.1007/978-3-030-68773-1_12⟩ |
|
Telepathic Headache: Mitigating Cache Side-Channel Attacks on Convolutional Neural NetworksApplied Cryptography and Network Security (ACNS), Jun 2021, Kamakura, Japan. pp.363-392, ⟨10.1007/978-3-030-78372-3_14⟩ |
|
|
|
Highly Reliable PUFs for Embedded Systems, Protected Against TamperingINISCOM 2021 : International Conference on Industrial Networks and Intelligent Systems, Apr 2021, Hanoi (Vietnam), Vietnam. pp.167-184, ⟨10.1007/978-3-030-77424-0_14⟩ |
Testing and Reliability Enhancement of Security Primitives2021 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), Oct 2021, Athens, Greece. pp.1-8, ⟨10.1109/DFT52944.2021.9568297⟩ |
|
|
|
Virtual Platform to Analyze the Security of a System on Chip at Microarchitectural LevelEuroS&PW 2021 - IEEE European Symposium on Security and Privacy Workshops, Sep 2021, Vienne, Austria. pp.96-102, ⟨10.1109/EuroSPW54576.2021.00017⟩ |
|
|
Multiple and Reproducible Fault Models on Micro-Controller using Electromagnetic Fault Injection2021 JOINT IEEE INTERNATIONAL SYMPOSIUM ON ELECTROMAGNETIC COMPATIBILITY, SIGNAL & POWER INTEGRITY, AND EMC EUROPE, Jul 2021, Virtuel, France. ⟨10.1109/EMC/SI/PI/EMCEurope52599.2021.9559288⟩ |
Effect of Aging on PUF Modeling Attacks based on Power Side-Channel Observations2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), Mar 2020, Grenoble, France. pp.454-459, ⟨10.23919/DATE48585.2020.9116428⟩ |
|
|
|
Single-bit Laser Fault Model in NOR Flash Memories2020 Workshop on Fault Detection and Tolerance in Cryptography (FDTC), Sep 2020, Milan, Italy. pp.41-48, ⟨10.1109/FDTC51366.2020.00013⟩ |
|
|
On the Effect of Aging on Digital Sensors2020 33rd International Conference on VLSI Design and 2020 19th International Conference on Embedded Systems (VLSID), Jan 2020, Bangalore, India. pp.189-194, ⟨10.1109/VLSID49098.2020.00050⟩ |
Cross-PUF Attacks on Arbiter-PUFs through their Power Side-Channel2020 IEEE International Test Conference (ITC), Nov 2020, Washington, United States. pp.1-5, ⟨10.1109/ITC44778.2020.9325241⟩ |
|
|
|
The Big Picture of Delay-PUF Dependability24th European Conference on Circuit Theory and Design (ECCTD), IEEE, Sep 2020, Sofia, Bulgaria |
RISC-V Extension for Lightweight Cryptography2020 23rd Euromicro Conference on Digital System Design (DSD), Aug 2020, Kranj, Slovenia. pp.222-228, ⟨10.1109/DSD51259.2020.00045⟩ |
|
|
|
Using Digital Sensors to Leverage Chips' Security2020 IEEE Physical Assurance and Inspection of Electronics (PAINE), Dec 2020, Washington, United States. pp.1-6, ⟨10.1109/PAINE49178.2020.9337730⟩ |
On-Chip Voltage and Temperature Digital Sensor for Security, Reliability, and Portability2020 IEEE 38th International Conference on Computer Design (ICCD), Oct 2020, Hartford, United States. pp.506-509, ⟨10.1109/ICCD50377.2020.00091⟩ |
|
Failure and Attack Detection by Digital Sensors2020 IEEE European Test Symposium (ETS), May 2020, Tallinn, Estonia. pp.1-2, ⟨10.1109/ETS48528.2020.9131580⟩ |
|
Characterization of Electromagnetic Fault Injection on a 32-bit Microcontroller Instruction Buffer2020 Asian Hardware Oriented Security and Trust Symposium (AsianHOST), Dec 2020, Kolkata, India. pp.1-6, ⟨10.1109/AsianHOST51057.2020.9358270⟩ |
|
|
|
PUF Enrollment and Life Cycle Management: Solutions and Perspectives for the Test CommunityIEEE European Test Symposium (ETS 2020), May 2020, Tallinn, Estonia. pp.1-10 |
|
|
Experimental Analysis of the Electromagnetic Instruction Skip Fault Model15th Design & Technology of Integrated Systems in Nanoscale Era (DTIS 2020), Apr 2020, Marrakech, Morocco. ⟨10.1109/DTIS48698.2020.9081261⟩ |
|
|
Precise Spatio-Temporal Electromagnetic Fault Injections on Data Transfers2019 Workshop on Fault Diagnosis and Tolerance in Cryptography (FDTC), Aug 2019, Atlanta, United States. pp.1-8, ⟨10.1109/FDTC.2019.00009⟩ |
Acceleration of Lightweight Block Ciphers on MicroprocessorsCryptArchi 2019, Jun 2019, Prague, Poland |
|
Method for Identifying Individual Electronic Devices Focusing on Differences in Spectrum Emissions2019 Joint International Symposium on Electromagnetic Compatibility and Asia-Pacific International Symposium on Electromagnetic Compatibility, Sep 2019, Sapporo, Japan |
|
Two-Metric Helper Data for Highly Robust and Secure Delay PUFs2019 IEEE 8th International Workshop on Advances in Sensors and Interfaces (IWASI), Jun 2019, Otranto, Italy. pp.184-188, ⟨10.1109/IWASI.2019.8791249⟩ |
|
|
|
Impact of Intentional Electromagnetic Interference on Pure Combinational Logic2019 International Symposium on Electromagnetic Compatibility - EMC EUROPE, Sep 2019, Barcelone, Spain. pp.398-403 |
|
|
Generic Architecture for Lightweight Block Ciphers: A First Step Towards Agile Implementation of Multiple Ciphers12th IFIP International Conference on Information Security Theory and Practice (WISTP), Dec 2018, Brussels, Belgium. pp.28-43, ⟨10.1007/978-3-030-20074-9_4⟩ |
LAOCOÖN: A Run-Time Monitoring and Verification Approach for Hardware Trojan Detection2019 22nd Euromicro Conference on Digital System Design (DSD), Aug 2019, Kallithea, Greece. pp.269-276, ⟨10.1109/DSD.2019.00047⟩ |
|
|
|
Characterization at Logical Level of Magnetic Injection Probes2019 Joint International Symposium on Electromagnetic Compatibility and Asia-Pacific International Symposium on Electromagnetic Compatibility, Jun 2019, Sapporo, Japan |
|
|
Laser-induced Single-bit Faults in Flash Memory: Instructions Corruption on a 32-bit Microcontroller2019 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), May 2019, McLean, United States. pp.1-10, ⟨10.1109/HST.2019.8741030⟩ |
|
|
Prediction-Based Intrusion Detection System for In-Vehicle Networks Using Supervised Learning and Outlier-Detection12th IFIP International Conference on Information Security Theory and Practice (WISTP), Dec 2018, Brussels, Belgium. pp.109-128, ⟨10.1007/978-3-030-20074-9_9⟩ |
Classification of Lightweight Block Ciphers for Specific Processor Accelerated Implementations2019 26th IEEE International Conference on Electronics, Circuits and Systems (ICECS), Nov 2019, Genoa, Italy. pp.747-750, ⟨10.1109/ICECS46596.2019.8965156⟩ |
|
|
|
Detecting Faults in Inner-Product Masking Scheme - IPM-FD: IPM with Fault Detection8th International Workshop on Security Proofs for Embedded Systems, 2019, Aug 2019, atlanta, United States. pp.17-32, ⟨10.29007/fv2n⟩ |
On the Effect of Aging in Detecting Hardware Trojan Horses with Template Analysis.IOLTS, Jul 2018, Platja d'Aro, Spain. ⟨10.1109/IOLTS.2018.8474089⟩ |
|
Reliability and entropy of delay PUFs: A theoretical analysis16th International Workshop on Cryptographic Architectures Embedded in Logic Devices (CryptArchi 2018), Jun 2018, Lorient, France |
|
|
|
An improved analysis of reliability and entropy for delay PUFsEuromicro Conference on Digital System Design (DSD'18), Aug 2018, Prague, Czech Republic. ⟨10.1109/DSD.2018.00096⟩ |
Impact of Aging on Template AttacksGLSVLSI, May 2018, Chicago, United States. pp.455-458, ⟨10.1145/3194554.3194638⟩ |
|
CCFI-Cache: A Transparent and Flexible Hardware Protection for Code and Control-Flow Integrity2018 21st Euromicro Conference on Digital System Design (DSD), Aug 2018, Prague, Czech Republic. pp.529-536, ⟨10.1109/DSD.2018.00093⟩ |
|
|
|
Challenge codes for physically unclonable functions with Gaussian delays: A maximum entropy problemLatin American Workshop on Coding and Information, Jul 2018, Unicamp-Campinas, Brazil |
Analysis of Mixed PUF-TRNG Circuit Based on SR-Latches in FD-SOI Technology2018 21st Euromicro Conference on Digital System Design (DSD), Aug 2018, Prague, Czech Republic. pp.508-515 |
|
Formalism to assess and enhance the entropy and reliability of a Loop-PUFCRYPTO'IC, Sep 2017, Chengdu, China |
|
Formalism to assess the entropy and reliability of the loop-PUF15th International Workshop on Cryptographic Architectures Embedded in Reconfigurable Devices (CryptArchi 2017), Jun 2017, Smolenice, Slovakia |
|
Analyzing security breaches of countermeasures throughout the refinement process in hardware design flowDATE, Dec 2017, lausanne, Switzerland. ⟨10.23919/DATE.2017.7927159⟩ |
|
A 2.5ns-Latency 0.39pJ/b 289µm2/Gb/s Ultra-Light-Weight PRINCE Cryptographic ProcessorSymposium on VLSI Circuits, Jun 2017, Kyoto, Japan. pp.C266-C267 |
|
Impact of the switching activity on the aging of delay-PUFsETS, May 2017, Limassol, Greece. ⟨10.1109/ETS.2017.7968223⟩ |
|
Overview of Protections Against IC Counterfeiting and Hardware Trojan HorsesISSCC, Jan 2016, Sab Francisco, United States |
|
Delay PUF Assessment Method Based on Side-Channel and Modeling AnalyzesTrustCom-16, Aug 2016, Tianjin, China |
|
Correlated Extra-Reductions Defeat Blinded Regular ExponentiationCryptographic Hardware and Embedded Systems – CHES 2016, Aug 2016, Santa Barbara, United States. pp.Pages 3-22 |
|
|
|
On the Entropy of Physically Unclonable Functions2016 IEEE International Symposium on Information Theory (ISIT'16), Jul 2016, Barcelona, Spain. ⟨10.1109/ISIT.2016.7541835⟩ |
Predictive Aging of Reliability of Two Delay PUFsSPACE, Dec 2016, Hyderabad, India. ⟨10.1007/978-3-319-49445-6_12⟩ |
|
A challenge code for maximizing the entropy of PUF responsesCryptographic Architectures Embedded in Reconfigurable Devices (CryptArchi 2016), Jun 2016, Montpellier, France |
|
|
|
Correlated Extra-Reductions Defeat Blinded Regular Exponentiation18th International Conference on Cryptographic Hardware and Embedded Systems (CHES 2016), Aug 2016, Santa Barbara, CA, United States. pp.3-22, ⟨10.1007/978-3-662-53140-2⟩ |
|
|
PUFs: Standardization and Evaluation2nd IEEE Workshop on Mobile System Technologies (MST 2016), Sep 2016, Milano, Italy. ⟨10.1109/MST.2016.11⟩ |
|
|
PLL to the rescue: a novel EM fault countermeasureDAC, Jun 2016, Austin, United States. ⟨10.1145/2897937.2898065⟩ |
|
|
Inter-Class vs. Mutual Information as Side-Channel Distinguishers2016 IEEE International Symposium on Information Theory (ISIT'16), Jul 2016, Barcelona, Spain. ⟨10.1109/ISIT.2016.7541410⟩ |
Dismantling Real-World ECC with Horizontal and Vertical Template AttacksConstructive Side-Channel Analysis and Secure Design - COSADE 2016, Apr 2016, Graz, Austria. pp 88-108 |
|
A novel methodology for testing hardware security and trust exploiting On-Chip Power noise MeasurementASP-DAC, Jan 2015, Tokyo, Japan. ⟨10.1109/ASPDAC.2015.7059100⟩ |
|
IC variability : Pros and cons for security blocksTRUDEVICE, Mar 2015, Grenoble, France |
|
Countering Early Propagation and Routing Imbalance of DPLInternational Conference on IC Design and Technology (ICICDT), Jun 2015, Leuven, Belgium. ⟨10.1109/ICICDT.2015.7165897⟩ |
|
|
|
Hardware property checker for run-time Hardware Trojan detectionEuromicro Conference on Digital System Design (DSD) 2015, Aug 2015, Trondheim, Norway. ⟨10.1109/ECCTD.2015.7300085⟩ |
|
|
High Precision Fault Injections on the Instruction Cache of ARMv7-M ArchitecturesHOST 2015: IEEE International Symposium on Hardware-Oriented Security and Trust, May 2015, Washington, United States. ⟨10.1109/HST.2015.7140238⟩ |
|
|
Linear complementary dual code improvement to strengthen encoded circuit against hardware Trojan horsesIEEE International Symposium on Hardware Oriented Security and Trust (HOST) 2015, May 2015, McLean, United States. ⟨10.1109/HST.2015.7140242⟩ |
Underneath the FPGA Clothes: Enhancing Security25th International Conference Field Programmable Logic and Applications, FPL 2015, Sep 2015, Londre, United Kingdom |
|
|
|
Private Circuits II versus Fault Injection AttacksReconfig 2015, Dec 2015, Mayan Riviera, Mexico |
|
|
Integrated Sensor: A Backdoor for Hardware Trojan Insertions?Euromicro Conference on Digital System Design (DSD) 2015, Aug 2015, Funchal, Portugal. ⟨10.1109/DSD.2015.119⟩ |
|
|
Hardware Trojan Detection by Delay and Electromagnetic MeasurementsDesign, Automation and Test in Europe 2015, Mar 2015, Grenoble, France. ⟨10.7873/DATE.2015.1103⟩ |
|
|
From theory to practice of private circuit: A cautionary note33rd IEEE International Conference on Computer Design (ICCD), Oct 2015, New York, United States. ⟨10.1109/ICCD.2015.7357117⟩ |
NICV: Normalized Inter-Class Variance for Detection of Side-Channel LeakageEMC, May 2014, Tokyo, Japan |
|
How to get a trusted FPGA ?Workshop INRIA, May 2014, Rennes, France |
|
Analysis and Improvements of the DPA Contest v4 ImplementationSPACE, Oct 2014, Pune, India. ⟨10.1007/978-3-319-12060-7_14⟩ |
|
|
|
Side-channel leakage and trace compression using normalized inter-class variance.HASP, Jun 2014, Minneapolis, United States. ⟨10.1145/2611765.2611772⟩ |
HCODE: Hardware-Enhanced Real-Time CFIPPREW@ACSAC 2014, Dec 2014, New Orleans, United States. ⟨10.1145/2689702.2689708⟩ |
|
Side-channel leakage on silicon substrate of CMOS cryptographic chipHOST, May 2014, Washington DC, United States. ⟨10.1109/HST.2014.6855564⟩ |
|
Cryptoprocessor with Native Resistance against Side Channel and Fault Injection AttacksWseas, Dec 2014, Istanbul, Turkey |
|
A Look into SIMON from a Side-channel PerspectiveHOST, May 2014, Washington DC, United States. ⟨10.1109/HST.2014.6855568⟩ |
|
Side channel analysis on an embedded hardware fingerprint biometric comparator & low cost countermeasures.HASP, Jun 2014, Minneapolis, United States. ⟨10.1145/2611765.2611771⟩ |
|
Hardware-enforced Protection against Software Reverse-Engineering based on an Instruction Set EncodingPPREW, Jan 2014, San Diego, United States. ⟨10.1145/2556464.2556469⟩ |
|
|
|
Hacking and protecting IC hardwareDATE 2014 - 17th Design, Automation and Test in Europe Conference and Exhibition, Mar 2014, Dresden, Germany. ⟨10.7873/DATE.2014.112⟩ |
|
|
Cryptographically secure shieldsHOST 2014 - IEEE International Symposium on Hardware-Oriented Security and Trust, May 2014, Washington, United States. pp.25 - 31, ⟨10.1109/HST.2014.6855563⟩ |
|
|
A Pre-processing Composition for Secret Key Recovery on Android Smartphone8th IFIP International Workshop on Information Security Theory and Practice (WISTP), Jun 2014, Heraklion, Crete, Greece. pp.76-91, ⟨10.1007/978-3-662-43826-8_6⟩ |
Physical Security Evaluation at an Early Design-Phase: A Side-Channel Aware Simulation MethodologyES4CPS, Mar 2014, Dresden, Germany. ⟨10.1145/2559627.2559628⟩ |
|
Balancing WDDL dual-rail logic in a tree-based FPGA to enhance physical securityFPL 2014 - 24th International Conference on Field Programmable Logic and Applications, Sep 2014, Munich, Germany. pp.1--4, ⟨10.1109/FPL.2014.6927422⟩ |
|
Methods to Enhance the Reliability of Key Generation from Physically Unclonable FunctionsPROOFS, Sep 2014, Busan, South Korea |
|
|
|
Boosting High-Order Correlation Attacks by Dimensionality ReductionSPACE, Oct 2014, Pune, India. ⟨10.1007/978-3-319-12060-7_13⟩ |
|
|
Method Taking into Account Process Dispersions to Detect Hardware Trojan Horse by Side-ChannelPROOFS: Security Proofs for Embedded Systems 2014, Sep 2014, BUSAN, South Korea |
|
|
Encoding the State of Integrated Circuits: a Proactive and Reactive Protection against Hardware Trojans HorsesWorkshop on Embedded Systems Security (WESS 2014), Oct 2014, New Delhi, India. ⟨10.1145/2668322.2668329⟩ |
Hacking and Protecting IC HardwareDATE 2014 - 17th Design, Automation and Test in Europe Conference and Exhibition, Mar 2014, Dresden, Germany. ⟨10.7873/DATE.2014.112⟩ |
|
Design Methodology of an ASIC TRNG based on an open-loop delay chainNEWCAS, Jun 2013, Paris, France. ⟨10.1109/NEWCAS.2013.6573654⟩ |
|
Introduction to Recent Research on EM Information LeakageAsia-Pacific Symposium on Electromagnetic Compatibility (APEMC2013), May 2013, Melbourne, Australia. pp.320-323 |
|
FPGA design of an Open-Loop True Random Number Generator16th euromicro conference on digital system design, Sep 2013, Santander, Spain. pp.615-622, ⟨10.1109/DSD.2013.73⟩ |
|
|
|
Evaluation of Delays PUFs on CMOS 65 nm Technology: ASIC vs FPGAWorkshop on Trustworthy Manufacturing and Utilization of Secure Devices, TRUDEVICE 2013, May 2013, Avignon, France |
Evaluation of Delay PUFs on CMOS 65 nm Technology: ASIC vs FPGAInternational Workshops on Cryptographic Architectures Embedded in Reconfigurable Devices CryptArchi 2013, Jun 2013, Fréjus, France |
|
|
|
Time-frequency analysis for second-order attacksSmart Card Research and Advanced Application Conference (CARDIS 2013), Nov 2013, Berlin, Germany. pp.108-122, ⟨10.1007/978-3-319-08302-5_8⟩ |
|
|
Hardware Trojan Horses in Cryptographic IP CoresFDTC (Fault Detection and Tolerance in Cryptography), Aug 2013, Santa Barbara, United States. pp.15-29, ⟨10.1109/FDTC.2013.15⟩ |
Low-Cost Countermeasure against RPACARDIS 2012, Nov 2012, Graz, Austria. pp.106-122 |
|
Evaluation of delay PUFs on CMOS 65nm technology: ASIC vs FPGAInternational Workshop on Hardware and Architectural Support for Security and Privacy, HASP 2013, Jun 2013, Tel-Aviv, Israel. pp.Article n° 4 |
|
Stochastic model of a Metastability-based True Random Number GeneratorTRUST, Jun 2013, Londres, United Kingdom. ⟨10.1007/978-3-642-38908-5_7⟩ |
|
A Low-Entropy First-Degree Secure Provable Masking Scheme for Resource-Constrained DevicesWESS, Sep 2013, Montreal, Canada. ⟨10.1145/2527317.2527324⟩ |
|
On-Chip Power Noise Measurements of Cryptographic VLSI Circuits and Interpretation for Side-Channel AnalysisInternational Symposium on Electromagnetic Compatibility (EMC Europe), Sep 2013, Brugge, Belgium. pp.405-410 |
|
Wavelet Transform Based Pre-processing for Side Channel AnalysisHASP, Dec 2012, Vancouver, Canada. ⟨10.1109/MICROW.2012.15⟩ |
|
|
|
Physically Unclonable Functions CharacterisationColloque du GDR SoC-SiP, Jun 2012, Paris, France |
|
|
An Easy-to-Design PUF based on a Single Oscillator: the Loop PUF15th Euromicro Conference on Digital System Design(DSD), Sep 2012, Cesme, Izmir, Turkey. 7 p |
|
|
3D Hardware CanariesCHES 2012 - 14th International Workshop Cryptographic Hardware and Embedded Systems, Sep 2012, Leuven, Belgium. pp.1-22, ⟨10.1007/978-3-642-33027-8_1⟩ |
|
|
System-Level Methods to Prevent Reverse-Engineering, Cloning, and Trojan InsertionICISTM, Mar 2012, Grenoble, France. pp.433-438, ⟨10.1007/978-3-642-29166-1_41⟩ |
|
|
On the Optimality of Correlation Power Attack on Embedded Cryptographic Systems6th International Workshop on Information Security Theory and Practice (WISTP), Jun 2012, Egham, United Kingdom. pp.169-178, ⟨10.1007/978-3-642-30955-7_15⟩ |
Towards Different Flavors of Combined Side Channel AttacksCT-RSA, Feb 2012, San Francisco, United States. pp.245-259, ⟨10.1007/978-3-642-27954-6_16⟩ |
|
From cryptography to hardware: analyzing embedded Xilinx BRAM for cryptographic applicationsHASP, Dec 2012, Vancouver, Canada. ⟨10.1109/MICROW.2012.11⟩ |
|
A Fault Model for Conducted Intentional ElectroMagnetic InterferencesEMC, Aug 2012, Pittsburgh, United States. pp.788-793, ⟨10.1109/ISEMC.2012.6351664⟩ |
|
|
|
Comparison between Side-Channel Analysis Distinguishers14th International Conference on Information and Communications Security (ICICS'2012), Oct 2012, Hong Kong, China. pp.331-340, ⟨10.1007/978-3-642-34129-8_30⟩ |
|
|
Random Active ShieldFault Diagnosis and Tolerance in Cryptography, Sep 2012, Leuven, Belgium. 11 p., ⟨10.1109/FDTC.2012.11⟩ |
Same Values Power Analysis Using Special Points on Elliptic CurvesCOSADE 2012 - Third International Workshop Constructive Side-Channel Analysis and Secure Design, May 2012, Darmstadt, Germany. pp.Cédric Murdica, ⟨10.1007/978-3-642-29912-4_14⟩ |
|
Some results about the distinction of side-channel distinguishers based on distributions10th International Workshop on Cryptographic Architectures Embedded in Reconfigurable Devices (CryptArchi 2012), Jun 2012, Saint-Etienne, France |
|
Measurement of side-channel information from cryptographic devices on security evaluation platform: Demonstration of SPACES projectSICE Annual Conference, Aug 2012, Akita, Japan |
|
Register Leakage Masking Using Gray CodeHOST, Jun 2012, San Francisco, United States. ⟨10.1109/HST.2012.6224316⟩ |
|
|
|
RSM: a Small and Fast Countermeasure for AES, Secure against 1st and 2nd-order Zero-Offset SCAsDesign Automation and Test in Europe, Mar 2012, Desden, Germany. pp.1173-1178 |
Delay PUF OverviewGDR Soc-SIP, Nov 2012, Paris, France |
|
A First-Order Leak-Free Masking CountermeasureCT-RSA, Feb 2012, San Francisco, CA, United States. pp.156-170, ⟨10.1007/978-3-642-27954-6_10⟩ |
|
Optimal First-Order Masking with Linear and Non-Linear BijectionsAfricaCrypt, Jul 2012, Ifrane, Morocco. ⟨10.1007/978-3-642-31410-0_22⟩ |
|
Efficient mapping of EM radiation associated with information leakage for cryptographic devicesEMC, Aug 2012, Pittsburgh, United States. pp.794-799, ⟨10.1109/ISEMC.2012.6351663⟩ |
|
Leakage Squeezing of Order TwoIndoCypt, Dec 2012, Kolkata, India. ⟨10.1007/978-3-642-34931-7_8⟩ |
|
A formal study of two physical countermeasures against side channel attacksPROOFS, Sep 2012, Leuven, Belgium. ⟨10.1007/s13389-013-0054-6⟩ |
|
A Small and High-performance Coprocessor for Fingerprint Match-On-CardDSD, Sep 2012, Cesme/Izmir, Turkey. ⟨10.1109/DSD.2012.14⟩ |
|
|
|
Leakage Squeezing Countermeasure against High-Order Attacks5th Workshop on Information Security Theory and Practices (WISTP), Jun 2011, Heraklion, Crete, Greece. pp.208-223, ⟨10.1007/978-3-642-21040-2_14⟩ |
|
|
Vade Mecum on Side-Channels Attacks and Countermeasures for the Designer and the EvaluatorDesign & Technology of Integrated Systems, Apr 2011, Athens, Greece. pp.6, ⟨10.1109/DTIS.2011.5941419⟩ |
|
|
Formal Framework for the Evaluation of Waveform Resynchronization Algorithms5th Workshop on Information Security Theory and Practices (WISTP), Jun 2011, Heraklion, Crete, Greece. pp.100-115, ⟨10.1007/978-3-642-21040-2_7⟩ |
|
|
Performance Evaluation of Silicon Physically Unclonable Function by Studing Physicals Values9th IEEE International NEWCAS conference 2011, Jun 2011, Bordeaux, France. pp.482-485 |
A Multiresolution Time-Frequency Analysis Based Side Channel AttacksWIFS Poster Session, Nov 2011, Iguacu Falls, Brazil |
|
|
|
Entropy-based Power AttackHardware-Oriented Security and Trust, Jun 2010, Anaheim, CA, United States. pp.1-6, ⟨10.1109/HST.2010.5513124⟩ |
De la roue au radar : quelques innovations en métrologie radar5éme Colloque Interdisciplinaire en Instrumentation (C2I), Jan 2010, Le Mans, France. pp.110-118 |
|
|
|
Fault Injection ResilienceFault Diagnosis and Tolerance in Cryptography, Aug 2010, Santa Barbara, United States. pp.51-65, ⟨10.1109/FDTC.2010.15⟩ |
|
|
Evaluation of Countermeasure Implementations Based on Boolean Masking to Thwart Side-Channel AttacksSCS, Nov 2009, Jerba, Tunisia. 6 p., ⟨10.1109/ICSCS.2009.5412597⟩ |
|
|
Combined SCA and DFA Countermeasures Integrable in a FPGA Design FlowReConFig, Dec 2009, Cancún, Mexico. pp.213 - 218, ⟨10.1109/ReConFig.2009.50⟩ |
|
|
Successful Attack on an FPGA-based WDDL DES Cryptoprocessor Without Place and Route Constraints.Design, Automation & Test in Europe Conference & Exhibition, 2009. DATE '09., Apr 2009, NICE, France. pp.640-645 |
Updates on the Potential of Clock-Less Logics to Strengthen Cryptographic Circuits against Side-Channel AttacksIEEE International Conference on Electronics and Systems (ICECS'09), Dec 2009, Hammamet, Tunisia. pp.351 - 354, ⟨10.1109/ICECS.2009.5411008⟩ |
|
|
|
WDDL is Protected Against Setup Time Violation AttacksCHES, Sep 2009, Lausanne, Switzerland. pp.73-83, ⟨10.1109/FDTC.2009.40⟩ |
Place-and-route impact on the security of DPL designs in FPGAs2008 IEEE International Workshop on Hardware-Oriented Security and Trust (HOST), Jun 2008, Anaheim, United States. pp.26-32, ⟨10.1109/HST.2008.4559042⟩ |
|
|
|
Shall we trust WDDL?Future of Trust in Computing, Jun 2008, Berlin, Germany. pp.208-215, ⟨10.1007/978-3-8348-9324-6_22⟩ |
A Secure Programmable Architecture with a Dedicated Tech-mapping Algorithm: Application to a Crypto-Processor23rd International Conference on Design of Circuits and Integrated Systems (DCIS'08), Nov 2008, Grenoble, France. pp.session 3b3 |
|
|
|
Area Optimization of Cryptographic Co-Processors Implemented in Dual-Rail with Precharge Positive LogicInternational Conference on Field Programmable Logic and Applications, Sep 2008, Heidelberg, Germany. pp.161-166, ⟨10.1109/FPL.2008.4629925⟩ |
|
|
Silicon-level Solutions to Counteract Passive and Active AttacksFDTC, Aug 2008, Washington, DC, United States. pp.3-17, ⟨10.1109/FDTC.2008.18⟩ |
|
|
Evaluation of Power-Constant Dual-Rail Logic as a Protection of Cryptographic Applications in FPGAsSecure System Integration and Reliability Improvement, Jul 2008, Yokohama, Japan. pp.16-23, ⟨10.1109/SSIRI.2008.31⟩ |
Efficient tiling patterns for reconfigurable gate arraysFPGA08: ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Feb 2008, Monterey California USA, United States. pp.257-257, ⟨10.1145/1344671.1344709⟩ |
|
An 8x8 run-time reconfigurable FPGA embedded in a SoCDAC '08: The 45th Annual Design Automation Conference 2008, Jun 2008, Anaheim California, United States. pp.120-125, ⟨10.1145/1391469.1391500⟩ |
|
Efficient Modeling and Floorplanning of Embedded-FPGA Fabric2007 International Conference on Field Programmable Logic and Applications, Aug 2007, Amsterdam, Netherlands. pp.665-669, ⟨10.1109/FPL.2007.4380741⟩ |
|
|
|
A Novel Asynchronous e-FPGA Architecture for Security ApplicationsICFPT 2007 - IEEE International Conference on Field-Programmable Technology, Dec 2007, Kitakyusyu, Japan. pp.369-372, ⟨10.1109/FPT.2007.4439288⟩ |
FASE: An Open Run-Time Reconfigurable FPGA Architecture for Tamper-Resistant and Secure Embedded Systems2006 IEEE International Conference on Reconfigurable Computing and FPGA's, Sep 2006, San Luis Potosi, France. pp.1-9, ⟨10.1109/RECONF.2006.307752⟩ |
|
Lambda-Min Decoding Algorithm of Regular and Irregular LDPC Codes3nd International Symposium on Turbo Codes and Related Topics, Sep 2003, Brest, France. pp.451-454 |
|
Décodage des codes LDPC par l'algorithme lambda-minGRETSI 2003, Sep 2003, Paris, France |
|
|
|
lambda-Min Decoding Algorithm of Regular and Irregular LDPC Codes3nd International Symposium on Turbo Codes & Related Topics, 2003, Brest, France |
|
|
Etude d'un algorithme itératif d'annulation de repliement spectral lors d'une conversion A/N parallèleJRNDM 2002 : 5èmes Journées Nationales du Réseau Doctoral en Microélectronique, Apr 2002, Grenoble, France |
|
|
Bit Error Rate Calculation for a Multiband Non Coherent On-Off Keying DemodulationIEEE International Conference On Communications (ICC 2002), Apr 2002, New-York, NY, United States. pp.202-206, ⟨10.1109/ICC.2002.996845⟩ |
|
|
Efficient FPGA Implementation of Gaussian Noise Generator for Communication Channel Emulation7th IEEE International Conference on Electronicsm Circuits & Systemes (ICECS'2K), Dec 2001, Kaslik, Lebanon. pp.1 |
|
|
Rényi Entropy Estimation for Secure Silicon FingerprintsIEEE Information Theory and Applications Workshop (ITA 2020), Feb 2020, Sans Diego, United States. , 2020 |
|
|
Power and Electromagnetic Analysis for Template AttacksTRUDEVICE, Mar 2015, Grenoble, France. , 2015 |
Efficient tiling patterns for reconfigurable gate arraysSLIP08: International Workshop on System Level Interconnect Prediction, Apr 2008, Newcastle United Kingdom, United Kingdom. ACM, pp.11-18, 2008, ⟨10.1145/1353610.1353613⟩ |
Foundations and practice of security : 6th international symposium, FPS 2013, La Rochelle, France, October 21-22, 2013, revised selected papersSpringer, 8352, pp.444, 2014, Lecture Notes in Computer Science, Lecture Notes in Computer Science, 978-3-319-05302-8 |
|
Security Trends for FPGASB. Badrignans, J.L. Danger, V. Fischer, G. Gogniat, L. Torres. Springer, 282 p., 2011, 978-94-007-1337-6 |
|
|
Self-secured PUF: Protecting the Loop PUF by MaskingProceedings of COSADE workshop, pp.293-314, 2021, ⟨10.1007/978-3-030-68773-1_14⟩ |
Enhancing the Resiliency of Multi-bit Parallel Arbiter-PUF and Its Derivatives Against Power AttacksConstructive Side-Channel Analysis and Secure Design, 12910, Springer International Publishing, pp.303-321, 2021, Lecture Notes in Computer Science, ⟨10.1007/978-3-030-89915-8_14⟩ |
|
|
|
Analysis and Protection of the Two-Metric Helper Data SchemeConstructive Side-Channel Analysis and Secure Design, 12910, Springer International Publishing, pp.279-302, 2021, Lecture Notes in Computer Science, ⟨10.1007/978-3-030-89915-8_13⟩ |
|
|
Multi-source Fault Injection Detection Using Machine Learning and Sensor FusionSecurity and Privacy, 1497, Springer International Publishing, pp.93-107, 2021, Communications in Computer and Information Science, ⟨10.1007/978-3-030-90553-8_7⟩ |
|
|
Security Evaluation Against Side-Channel Analysis at Compilation TimeSpringer. Algebra, Codes and Cryptology (A2C), pp.129-148, 2019, ⟨10.1007/978-3-030-36237-9_8⟩ |
|
|
Development of the Unified Security Requirements of PUFs During the Standardization ProcessInnovative Security Solutions for Information Technology and Communications. 11th International Conference, SecITC 2018, Bucharest, Romania, November 8–9, 2018, Revised Selected Papers, LNCS (11359), Springer, pp.314-330, 2019, 978-3-030-12942-2. ⟨10.1007/978-3-030-12942-2_24⟩ |
Identifier Randomization: An Efficient Protection Against CAN-Bus AttacksCyber-Physical Systems Security, Springer International Publishing, pp.219-254, 2018, ⟨10.1007/978-3-319-98935-8_11⟩ |
|
Attack Tree Construction and Its Application to the Connected VehicleCyber-Physical Systems Security, Springer International Publishing, pp.175-190, 2018, ⟨10.1007/978-3-319-98935-8_9⟩ |
|
|
|
Physical Security Versus Masking SchemesCyber-Physical Systems Security, Springer International Publishing, pp.269-284, 2018, ⟨10.1007/978-3-319-98935-8_13⟩ |
Physically Unclonable Function: Principle, Design and Characterization of the Loop PUFTrusted Computing for Embedded Systems, SPRINGER, pp.115-133, 2015, ⟨10.1007/978-3-319-09420-5_6⟩ |
|
|
|
Information theoretic comparison of side-channel distinguishers: Inter-class distance, confusion, and successBernard Candaele; Dimitrios Soudris; Iraklis Anagnostopoulos. Trusted Computing for European Embedded Systems, Springer, pp.187-225, 2015, 978-3-319-09419-9. ⟨10.1007/978-3-319-09420-5_10⟩ |
17 : Global Fault on Cryptographic CircuitsFault Analysis in Cryptography, Springer, pp.295-312, 2012 |
|
|
|
Security FPGA Analysis Security Trends for FPGAS |
|
|
Unrolling Cryptographic Circuits: A Simple Countermeasure Against Side-Channel AttacksJosef Pieprzyk. Topics in Cryptology - CT-RSA 2010. The 10th Cryptographers' Track at the RSA Conference 2010, San Francisco, CA, USA, March 1-5, 2010. Proceedings, 5985, Springer Berlin Heidelberg, pp.195-207, 2010, Lecture Notes in Computer Science, 978-3-642-11924-8. ⟨10.1007/978-3-642-11925-5_14⟩ |
Physical Design of FPGA Interconnect to Prevent Information LeakageWoods, R.; Compton, K.; Bourganis, C.; Diniz, P.C. Reconfigurable Computing: Architecture, Tools, and Applications, 4943, Springer, pp.87-98, 2008, Lecture Notes in Computer Science, ⟨10.1007/978-3-540-78610-8_11⟩ |
|
|
Overview of Dual Rail with Precharge Logic Styles to Thwart Implementation-Level Attacks on Hardware Cryptoprocessors2009 |
|
|
EM Channel Estimation in a Low-cost UWB Receiver based on Energy Detection2008 |
A Reconfigurable Programmable Logic Block for a Multi-Style Asynchronous FPGA resistant to Side-Channel Attacks2024 |
|
|
|
Chi-squared Distribution Approximation for Probabilistic Energy Equalizer Implementation in Impulse-Radio UWB Receiver2008 |
|
|
Successful Attack on an FPGA-based Automatically Placed and Routed WDDL+ Crypto Processor.2008 |
Dynamic Countermeasure Against the Zero Power Analysis[Research Report] IACR Cryptology ePrint Archive 2013: 764 (2013), 2013 |