Laurent Fesquet

Présentation

Maître de conférences

Laboratoire TIMA

Equipe CDSI (Design of Integrated devices, Circuits and Systems)

Publications

Article dans une revue (33)

Favoriser l’émergence des compétences recherche et innovation avant la thèse Laurent Fesquet,Xavier Lesage,Cristiano Merio,Ali Naimi,Sylvain Engels Journal sur l'enseignement des sciences et technologies de l'information et des systèmes, 2024, 23 (Hors série 1), 6 p. ⟨10.1051/j3ea/20241006⟩ Article dans une revue hal-04652438v1
Wideband Tunable N-Path Mixer With Calibrated Harmonic Rejection Including the 7th LO Harmonic Sana Ibrahim,Ali Alshakoush,Serge Subias,Loïc Vincent,Manuel Barraganet al. IEEE Transactions on Circuits and Systems I: Regular Papers, 2024, pp.1-12. ⟨10.1109/TCSI.2024.3414183⟩ Article dans une revue hal-04633997v1
Velocity and Color Estimation Using Event-Based Clustering Xavier Lesage,Rosalie Tran,Stéphane Mancini,Laurent Fesquet Sensors, 2023, 23 (24), pp.9768. ⟨10.3390/s23249768⟩ Article dans une revue hal-04343977v1
L’apprentissage par projet en microélectronique numérique Vers l’acquisition d’un savoir-faire Grégoire Lehouque,Antoine Costani,Michele Portolan,Laurent Fesquet Journal sur l'enseignement des sciences et technologies de l'information et des systèmes, 2022, 21 (1015), pp.7. ⟨10.1051/j3ea/20221015⟩ Article dans une revue hal-04018033v1
An Area and Power Efficient Stochastic Number Generator for Bayesian Sensor Fusion Circuits Jérémy Belot,Abdelkarim Cherkaoui,Raphael Laurent,Laurent Fesquet IEEE Design & Test, 2021, 38 (6), pp.69-77. ⟨10.1109/mdat.2021.3050694⟩ Article dans une revue hal-03662193v1
A dynamical approach to generate chaos in a micromechanical resonator Martial Defoort,Libor Rufer,Laurent Fesquet,Skandar Basrour Microsystems & Nanoengineering, 2021, 7 (17), ⟨10.1038/s41378-021-00241-6⟩ Article dans une revue hal-03165694v1
Design and Characterization of an Asynchronous Fixed Priority Tree Arbiter for SPAD Array Readout Enagnon Aguenounon,Safa Razavinejad,Jean-Baptiste Schell,Mohammadreza Dolatpoor Lakeh,Wassim Khaddouret al. Sensors, 2021, 21 (12), pp.3949. ⟨10.3390/s21123949⟩ Article dans une revue hal-03245660v1
Trojan Detection Test for Clockless Circuits R. Aquino Guazzelli,Matheus Garay Trindade,Leonel Acunha Guimarães,Thiago Ferreira de Paiva Leite,Laurent Fesquetet al. Journal of Electronic Testing: : Theory and Applications, 2020, ⟨10.1007/s10836-020-05857-6⟩ Article dans une revue hal-02472910v1
Clocked and event-driven redundant adjustable precision computing A. Skaf,M. Ezzadeen,Mounir Benabdenbi,Laurent Fesquet Microelectronics Reliability, 2020, 111, pp.113729. ⟨10.1016/j.microrel.2020.113729⟩ Article dans une revue hal-02900886v1
Learning-Based Reliability Assessment Method for Detection of Permanent Faults in Clockless Circuits R. Aquino Guazzelli,Matheus Garay Trindade,Laurent Fesquet,Rodrigo Possamai Bastos Microelectronics Reliability, 2019, 100, ⟨10.1016/j.microrel.2019.06.057⟩ Article dans une revue hal-03080316v1
A High Level Current Modeling for Shaping Electromagnetic Emissions in Micropipeline Circuits Sophie Germain,Sylvain Engels,Laurent Fesquet Journal of Low Power Electronics and Applications, 2019, 9 (1), ⟨10.3390/jlpea9010006⟩ Article dans une revue hal-02165140v1
Variance Analysis in 3D Integration: A statistically Unified Model with Distance Correlations Alexandre Ayres de Sousa,Olivier Rozeau,Bertrand Borot,Laurent Fesquet,Perrine Batudeet al. IEEE Transactions on Electron Devices, 2019, 66 (1), pp.633 - 640. ⟨10.1109/TED.2018.2879680⟩ Article dans une revue hal-01971015v1
A body built-in cell for detecting transient faults and dynamically biasing subcircuits of integrated systems Thiago Ferreira de Paiva Leite,Laurent Fesquet,Rodrigo Possamai Bastos Microelectronics Reliability, 2018, 88-90, pp.122-127. ⟨10.1016/j.microrel.2018.07.069⟩ Article dans une revue istex hal-01893707v1
Multi-phase low-noise digital ring oscillators with sub-gate-delay resolution Oussama Elissati,Abdelkarim Cherkaoui,Assia El Hadbi,Sébastien Rieubon,Laurent Fesquet AEÜ - International Journal of Electronics and Communications / Archiv für Elektronik und Übertragungstechnik, 2018, 84, pp.74 - 83. ⟨10.1016/j.aeue.2017.11.022⟩ Article dans une revue istex hal-01726767v1
Nanobob: a CubeSat mission concept for quantum communication experiments in an uplink configuration Erik Kerstel,Arnaud Gardelein,Mathieu Barthelemy,Yves Gilot,Etienne Lecoareret al. European physical journal quantum technology, 2018, 5 (6), pp.1-30. ⟨10.1140/epjqt/s40507-018-0070-7⟩ Article dans une revue hal-01929079v1
An accurate time-to-digital converter based on a self-timed ring oscillator for on-the-fly time measurement Assia El Hadbi,A. Cherkaoui,Jean Simatic,Oussama Elissati,Laurent Fesquet Analog Integrated Circuits and Signal Processing, 2018, 97 (3), pp.471-481. ⟨10.1007/s10470-018-1223-4⟩ Article dans une revue hal-01827393v1
Architectures of Bulk Built-In Current Sensors for Detection of Transient Faults in Integrated Circuits Rodrigo Possamai Bastos,Leonel Acunha Guimarães,Frank Sill Torres,Laurent Fesquet Microelectronics Journal, 2017, 71, pp.70-79. ⟨10.1016/j.mejo.2017.11.006⟩ Article dans une revue istex hal-01721110v1
Exploiting reliable features of asynchronous circuits for designing low-voltage components in FD-SOI technology O. Rolloff,Rodrigo Possamai Bastos,Laurent Fesquet Microelectronics Reliability, 2015, 55 (9-10), pp.1302-1306. ⟨10.1016/j.microrel.2015.07.028⟩ Article dans une revue istex hal-01334697v1
Un projet de microélectronique numérique original : Contrôle autonome d'un micro-drone par caméras externes Laurent Fesquet,Katell Morin-Allory,Robin Rolland-Girod Journal sur l'enseignement des sciences et technologies de l'information et des systèmes, 2015, 14 (2009), pp.9. ⟨10.1051/j3ea/2015021⟩ Article dans une revue hal-01334687v1
A Robust and Energy-Efficient DVFS Control Algorithm for GALS-ANoC MPSoC in Advanced Technology under Process Variability Constraints Sylvain Durand,Hatem Zakaria,Laurent Fesquet,Nicolas Marchand Advances in Computer Science : an International Journal, 2014, 3 (1), pp.97-105 Article dans une revue hal-01141136v1
Adaptive rate filtering a computationally efficient signal processing approach S.-M. Qaisar,Laurent Fesquet,Marc Renaudin Signal Processing, 2014, 94, pp.620-630. ⟨10.1016/j.sigpro.2013.07.019⟩ Article dans une revue istex hal-01137857v1
An asynchronous FPGA block with its tech-mapping algorithm dedicated to security applications T. Beyrouthy,Laurent Fesquet International Journal of Reconfigurable Computing, 2013, 2013 (Article ID 517947), 12 p. ⟨10.1155/2013/517947⟩ Article dans une revue hal-00819126v1
Non-uniform Filter interpolation in the frequency domain Brigitte Bidégaray-Fesquet,Laurent Fesquet Sampling Theory in Signal and Image Processing, 2011, 10 (1-2), pp.17-35. ⟨10.1007/BF03549532⟩ Article dans une revue hal-00646536v1
Designing a Process Variability Robust Energy-Efficient Control for Complex SoCs H. Zakaria,Laurent Fesquet IEEE Journal on Emerging and Selected Topics in Circuits and Systems, 2011, 1 (2), pp.160 - 172. ⟨10.1109/JETCAS.2011.2159284⟩ Article dans une revue hal-00646549v1
IIR digital filtering of non-uniformly sampled signals via state representation Laurent Fesquet,Brigitte Bidégaray-Fesquet Signal Processing, 2010, 90 (10), pp.2811-2821. ⟨10.1016/j.sigpro.2010.03.030⟩ Article dans une revue hal-00493354v1
Adaptative Rate Sampling and Filtering based on level crossing sampling S.-M. Qaisar,Laurent Fesquet,Marc Renaudin Eurasip Advances in Signal Processing, 2009, Article ID 971656, 12 p. ⟨10.1155/2009/971656⟩ Article dans une revue hal-00422320v1
Constrained Asynchronous Ring Structures for Robust Digital Oscillators J. Hamon,Laurent Fesquet,B. Miscopein,Marc Renaudin IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2009, 17 (7), pp.907-919. ⟨10.1109/TVLSI.2008.2011801⟩ Article dans une revue hal-00422313v1
A Signal Driven Adaptive Resolution Short-Time Fourier Transform S.-M. Qaisar,Laurent Fesquet,Marc Renaudin International Journal of Signal Processing, 2009, 5 (3), pp.180-188 Article dans une revue hal-00378808v1
Signal Driven Sampling and Filtering : A Promising Approach for Time Varying Signals Processing S.-M. Qaisar,Laurent Fesquet,Marc Renaudin International Journal of Signal Processing, 2009, 5 (3), pp.189-197 Article dans une revue hal-00378813v1
An Adaptive Resolution Computationally Efficient Short-Time Fourier Transform Saeed-Mian Qaisar,Laurent Fesquet,Marc Renaudin Research Letters in Signal Processing, 2008, 2008 (Article ID 932068), 5pp. ⟨10.1155/2008/932068⟩ Article dans une revue hal-00288750v1
Asynchronous level crossing analog to digital converters E. Allier,Laurent Fesquet,Marc Renaudin,G. Sicard Measurement - Journal of the International Measurement Confederation (IMEKO), 2005, Volume 37, Issue 4 June, pp.296-309. ⟨10.1016/j.measurement.2005.03.002⟩ Article dans une revue istex hal-00012072v1
A new type of Asynchronous Analog to Digital Interface E. Allier,G. Sicard,Laurent Fesquet,M. Renaudin Measurement - Journal of the International Measurement Confederation (IMEKO), 2004, 35 (2) Article dans une revue hal-01457059v1
Asynchronous technology for energy reduction in embedded systems Laurent Fesquet,M. Es Salhiene,Marc Renaudin Annals of Telecommunications - annales des télécommunications, 2004, 59 (7-8), pp.984-997 Article dans une revue hal-01334912v1

Communication dans un congrès (256)

Ultra-Thin-Body and Buried Oxide FD-SOI next generation nodes and eNVM technologies for advanced IC design Claire Fenouillet-Beranger,Laurent Fesquet,Rihab Chouk,Gabriel Pares,Baudouin Martineauet al. IEEE 28th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2025), May 2025, Lyon, France. ⟨10.1109/DDECS63720.2025.11006678⟩ Communication dans un congrès hal-05085365v1
ASTEERICS - AMI-CMA C2FM : un projet destiné à établir le Centre de Compétences français dans le domaine de la microélectronique Olivier Bonnaud,Laurent Fesquet 18ème Journées Pédagogiques du CNFM (JPCNFM 2025), Dec 2025, Saint-Malo, France Communication dans un congrès hal-05534252v1
A standard EDA-based Design Flow for Asynchronous Circuits Laurent Fesquet,Cristiano Merio,Adrien Godard,Gaël Ousset,Ismael de Almeidaet al. IHP Seminar 2025, Jul 2025, Frankfurt (Oder), Germany Communication dans un congrès hal-05193351v1
Pulsed ElectroMagnetic Fault Injection Attack on a Time Measurement-based Arbiter-PUF Azzadine Thajte,Sami El Amraoui,Paolo Maistri,Régis Leveugle,Giorgio Di Nataleet al. 28th Euromicro Conference Series on Digital System Design (DSD 2025), Sep 2025, Salerne, Italy Communication dans un congrès hal-05250505v1
A Microbolometer-Based Time-to-First-Spike Pixel for Infrared Imaging Ayoub Talbi,Laurent Fesquet,Marco Erickson Passy Kengani,Skandar Basrour,Mohamed Akraraiet al. 32nd IEEE International Conference on Electronics, Circuits and Systems (ICECS 2025), Nov 2025, Marrakech, Morocco. ⟨10.1109/ICECS66544.2025.11270545⟩ Communication dans un congrès hal-05534291v1
Analysis of Representative Critical Path as Delay Line for Bundled-Data Circuits Jéssica Gonsalves Santos,Ismael de Almeida,Sylvain Engels,Robin M. Wilson,Laurent Fesquet 38th SBC/SBMicro/IEEE Symposium on Integrated Circuits and Systems Design (SBCCI 2025), Aug 2025, Manaus, Brazil. ⟨10.1109/SBCCI66862.2025.11218679⟩ Communication dans un congrès hal-05398855v1
TIMA-PUF: Time Measurement based Arbiter PUF Azzadine Thajte,Laurent Fesquet,Giorgio Di Natale IEEE International Symposium on On-Line Testing and Robust System Design (IOLTS 2025), Jul 2025, Ischia, Italy. ⟨10.1109/IOLTS65288.2025.11117113⟩ Communication dans un congrès hal-05191534v1
Concevoir un GPU en projet microélectronique Chadi Bou Tanos,João Marqueti,Laurent Fesquet 18ème Journées Pédagogiques du CNFM (JPCNFM 2025), Dec 2025, Saint-Malo, France Communication dans un congrès hal-05534180v1
TIMA-PUF: A reliable arbiter PUF architecture Azzadine Thajte,Laurent Fesquet,Giorgio Di Natale 20th CryptArchi Workshop, Jun 2025, Autrans, France Communication dans un congrès hal-05192577v1
Data-driven Processing Element for Sparse Convolutional Neural Networks Xavier Lesage,Cristiano Merio,Fernando Welzel,Luca Sauer de Araujo,Sylvain Engelset al. 22nd IEEE International NEWCAS Conference (NewCAS 2024), Jun 2024, Sherbrooke, Canada Communication dans un congrès hal-04791419v1
Sensing Images with Event-Based Techniques Laurent Fesquet,Xavier Lesage,Ayoub Talbi,Mohamed Akrarai,Gilles Sicard GdR IASIS, Capteurs de vision et caméra intelligentes - Focus Architectures pour la Vision et l'IA, May 2024, Paris, France Communication dans un congrès hal-04791293v1
Designing asynchronous circuits with standard EDA tools Laurent Fesquet,Cristiano Merio,Adrien Godard,Xavier Lesage,Ali Naimiet al. 37th Symposim on Integrated Circuits and Systems Design (SBCCI 2024), SB Micro, Sep 2024, João Pessoa, Brazil, Brazil Communication dans un congrès hal-04791450v1
A New Control Law for N-Path Mixer Switches Enhancing Harmonic Rejection Hasan Moussa,Estelle Lauga-Larroze,Laurent Fesquet IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC 2024), Oct 2024, Tanger, Morocco Communication dans un congrès hal-04791351v1
Time-to-Digital Converter based Self-Timed Ring Oscillator: an FPGA Implementation Assia El Hadbi,Oussama El Issati,Laurent Fesquet Laurent Fesquet, “Time-to-Digital Converter based Self-Timed Ring Oscillator: an FPGA Implementation”, IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC 2024), Oct 2024, Tanger, Morocco Communication dans un congrès hal-04791382v1
Standard EDA tools based asynchronous design flow Adrien Godard,Cristiano Merio,Xavier Lesage,Ali Naimi,Sylvain Engelset al. IP-SoC Conference 2024, Dec 2024, Grenoble, France Communication dans un congrès hal-04851132v1
Spiking Neuron Model for Event-Based Vision : Examples, Training and Applications Xavier Lesage,Cristiano Merio,Fernando Welzel,Luca Sauer de Araujo,Rosalie Tranet al. GdR IASIS, Capteurs de vision et caméra intelligentes - Focus Architectures pour la Vision et l'IA, May 2024, Paris, France Communication dans un congrès hal-04791324v1
Precise Time-of-Flight Measurements Using a Novel High-Resolution Time-to-Digital Converter Architecture Assia El Hadbi,Oussama El Issati,Laurent Fesquet European Frequency and Time Forum (EFTF 2024), Jun 2024, Neuchâtel, Switzerland Communication dans un congrès hal-04791401v1
A Generic CDC Modeling for Data Stability Verification Diana Kalel,Jean-Christophe Brignone,Laurent Fesquet,Katell Morin-Allory IEEE 30th International Conference on Electronics, Circuits and Systems (ICECS 2023), Dec 2023, Istanbul, Turkey Communication dans un congrès hal-04331999v1
Making Digital N-Path Mixers Hasan Moussa,Jéssica Gonsalves Santos,Estelle Lauga-Larroze,Sana Ibrahim,Florence Podevinet al. 38th Conference on Design of Circuits and Integrated Systems (DCIS 2023), Nov 2023, Malaga, Spain Communication dans un congrès hal-04331937v1
Low-Throughput Event-Based Image Sensors and Processing Laurent Fesquet,Rosalie Tran,Xavier Lesage,Mohamed Akrarai,Stéphane Manciniet al. Design, Automation & Test in Europe Conference & Exhibition (DATE 2023), Apr 2023, Antwerp, Belgium. ⟨10.23919/DATE56975.2023.10137168⟩ Communication dans un congrès hal-04143308v1
Gestion du flot de conception sur une plateforme CAO Laurent Fesquet 17èmes journées pédagogiques du CNFM (JPCNFM 2023), Nov 2023, Toulouse, France Communication dans un congrès hal-04332013v1
Data-driven Pruning for Bundled-data Circuits Cristiano Merio,Xavier Lesage,Ali Naimi,Sylvain Engels,Katell Morin-Alloryet al. 28th International Symposium on Asynchronous Circuits and Systems (ASYNC 2023, Jul 2023, Beijing, China Communication dans un congrès hal-04331929v1
Sensing and Processing Image at Low-Power Laurent Fesquet FMNT/Summit Workshop, Low-power for a sustainable electronic, Mar 2023, Grenoble, France Communication dans un congrès hal-04331927v1
Event-based Image Sensing and Processing for Low-Power Applications Laurent Fesquet IEEE Vision workshop, Sensors and smart (AI) processing, Oct 2023, Nancy, France Communication dans un congrès hal-04331928v1
Method for Data-Driven Pruning in Micropipeline Circuits Cristiano Merio,Xavier Lesage,Ali Naimi,Sylvain Engels,Katell Morin-Alloryet al. 31st IFIP/IEEE Conference on Very Large Scale Integration (VLSI-SoC 2023), Oct 2023, Sharjah, United Arab Emirates Communication dans un congrès hal-04331953v1
Développer la compétence recherche en école d’ingénieurs Laurent Fesquet,Xavier Lesage,Cristiano Merio,Ali Naimi,Sylvain Engels 17èmes journées pédagogiques du CNFM (JPCNFM 2023), Nov 2023, Toulouse, France Communication dans un congrès hal-04332030v1
Innovation and education in microelectronics to face the society needs in semiconductors Olivier Bonnaud,Laurent Fesquet 7th Forum on Research and Technologies for Society and Industry Innovation: latest developments for a better world (RTSI 2022), IEEE France, Aug 2022, Paris, France Communication dans un congrès hal-04023662v1
Self-Timed Ring Oscillators for Non-Overlapping and Overlapping Phases Synthesis Hasan Moussa,Sana Ibrahim,Estelle Lauga-Larroze,Florence Podevin,Sylvain Bourdelet al. 20th IEEE International NEWCAS Conference (NEWCAS 2022), Jun 2022, Québec City, Canada. ⟨10.1109/NEWCAS52662.2022.9901390⟩ Communication dans un congrès hal-04023658v1
Mélangeur N-Path à 5 chemins rejetant jusqu'à l'harmonique 8 inclus pour récepteurs multistandards basse consommation Ali Alshakoush,Sana Ibrahim,Serge Subias,Loïc Vincent,Estelle Lauga-Larrozeet al. 22èmes Journées Nationales Microondes (JNM 2022), Jun 2022, Limoges, France Communication dans un congrès hal-04023663v1
Designing Event-Based Electronics Laurent Fesquet 8th International Conference on Event-based Control, Communication, and Signal Processing (EBCCSP 2022), Jun 2022, Cracow, Poland Communication dans un congrès hal-04023655v1
N-Path Mixer with Wide Rejection Including the 7 th Harmonic for Low Power Multi-standard Receivers Ali Al Shakoush,Sana Ibrahim,Serge Subias,Florence Podevin,Manuel J. Barraganet al. 20th IEEE Interregional NEWCAS Conference (NEWCAS 2022), IEEE, Jun 2022, Quebec City, Canada. pp.256-260, ⟨10.1109/NEWCAS52662.2022.9901392⟩ Communication dans un congrès hal-03852364v1
A Novel Event-Based Method for ASK Demodulation Rodrigo Iga,Sylvain Engels,Laurent Fesquet IEEE 13th Latin America Symposium on Circuits and System (LASCAS 2022), Mar 2022, Puerto Varas, Chile. pp.1-4, ⟨10.1109/LASCAS53948.2022.9789085⟩ Communication dans un congrès hal-04023660v1
An improved event-by-event clustering algorithm for noisy acquisition Xavier Lesage,Rosalie Tran,Stéphane Mancini,Laurent Fesquet 8th International Conference on Event-Based Control, Communication, and Signal Processing (EBCCSP 2022), Jun 2022, Krakow, Poland. pp.1-8, ⟨10.1109/EBCCSP56922.2022.9845512⟩ Communication dans un congrès hal-03772278v1
Distance learning is not an online face-to-face – Observations in microelectronic education Olivier Bonnaud,Laurent Fesquet 13th annual International Conference on Education and New Learning Technologies (EduLearn 2021), Jul 2021, Virtual event, Spain. ⟨10.21125/edulearn.2021⟩ Communication dans un congrès hal-03352870v1
An asynchronous hybrid pixel image sensor Mohamed Akrarai,Nils Margotat,G. Sicard,Laurent Fesquet 27th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2021), Sep 2021, Beijing, China. ⟨10.1109/ASYNC48570.2021.00016⟩ Communication dans un congrès hal-03432105v1
A hybrid event-based pixel for low-power image Sensing Mohamed Akrarai,Nils Margotat,Gilles Sicard,Laurent Fesquet 28th IEEE International Conference on Electronics Circuits and Systems (ICECS 2021), Nov 2021, Dubai, United Arab Emirates. ⟨10.1109/ICECS53924.2021.9665509⟩ Communication dans un congrès hal-03662342v1
Comparison between an ASK Event-Based Demodulation and a Digital IQ Demodulation Rodrigo Iga Jadue,Sylvain Engels,Laurent Fesquet 7th International Conference on Event-Based Control, Communication, and Signal Processing (EBCCSP 2021), Jun 2021, Krakow, Poland. ⟨10.1109/EBCCSP53293.2021.9502367⟩ Communication dans un congrès hal-03432059v1
Self-Timed Ring Oscillator Based Time-to-Digital Converter: a 0.35μm CMOS Proof-of-Concept Prototype Assia El Hadbi,Oussama Elissati,Laurent Fesquet IEEE International Instrumentation & Measurement Technology Conference (I2MTC 2021), May 2021, Glasgow, United Kingdom. ⟨10.1109/I2MTC50364.2021.9460031⟩ Communication dans un congrès hal-03352864v1
An Energy Efficient Multi-Rail Architecture for Stochastic Computing: A Bayesian Sensor Fusion Case Study Jérémy Belot,Abdelkarim Cherkaoui,Raphael Laurent,Laurent Fesquet 28th IEEE International Conference on Electronics Circuits and Systems (ICECS 2021), Nov 2021, Dubai, United Arab Emirates. ⟨10.1109/ICECS53924.2021.9665535⟩ Communication dans un congrès hal-03662362v1
A Novel Continuous TDC Measurement Technique Rodrigo Iga Jadue,Sylvain Engels,Laurent Fesquet 27th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2021), Sep 2021, Portland, United States Communication dans un congrès hal-03662324v1
A High-Level Design Flow for Locally Body-Biased Asynchronous Circuits Yoan Decoudu,Katell Morin-Allory,Laurent Fesquet 29th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC 2021), Oct 2021, Singapore, Singapore. ⟨10.1109/VLSI-SoC53125.2021.9606977⟩ Communication dans un congrès hal-03662244v1
Improved π-Delayed Harmonic Rejection N-Path Mixer for Low Power Consumption and Multistandard Receiver A Al Shakoush,Estelle Lauga-Larroze,Florence Podevin,S Ibrahim,Laurent Fesquetet al. 18th IEEE International New Circuits and Systems Conference (NEWCAS 2020), IEEE, Jun 2020, Montreal, Canada. ⟨10.1109/newcas49341.2020.9159792⟩ Communication dans un congrès hal-04453751v1
A Self-Timed Ring based PUF Grégoire Gimenez,A. Cherkaoui,Laurent Fesquet 26th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2020), May 2020, Snowbird, United States. pp.69-77 Communication dans un congrès hal-02952904v1
A Novel Event Based Image Sensor with Spatial and Temporal Redundancy Suppression Mohamed Akrarai,Nils Margotat,Gilles Sicard,Laurent Fesquet 18th IEEE International NEWCAS Conference (NEWCAS 2020), IEEE, Jun 2020, Montreal, Canada. pp.238-241, ⟨10.1109/NEWCAS49341.2020.9159847⟩ Communication dans un congrès hal-02956198v1
From High-Level Synthesis to Bundled-Data Circuits Yoan Decoudu,Jean Simatic,Katell Morin-Allory,Laurent Fesquet International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS 2020), Jul 2020, Samos, Greece Communication dans un congrès hal-02956234v1
Arbiterless Event-Based Imager Architecture with temporal and spatial redundancies suppression Mohamed Akrarai,Nils Margotat,G. Sicard,Laurent Fesquet 2020 6th International Conference on Event-Based Control, Communication, and Signal Processing (EBCCSP), Sep 2020, Krakow, Poland. ⟨10.1109/EBCCSP51266.2020.9291345⟩ Communication dans un congrès hal-03106821v1
Body-Bias Micro-Generators for Activity-Driven Power Management Laurent Fesquet,Yoan Decoudu,Rodrigo Iga Jadue,Thiago Ferreira de Paiva Leite,O. Rolloffet al. FDSOI workshop at DATE Conference 2020, Mar 2020, Grenoble, France Communication dans un congrès hal-02956260v1
At-speed DfT Architecture for Bundled-data Design Ricardo Aquino Guazzelli,Laurent Fesquet International Test Conference (ITC 2020), Nov 2020, Washington, United States. ⟨10.1109/ITC44778.2020.9325261⟩ Communication dans un congrès hal-03352862v1
An Effective QRS Selection Based on the Level-Crossing Sampling and Activity Selection S.-M. Qaisar,Laurent Fesquet 6th International Conference on Event-Based Control, Communication, and Signal Processing (EBCCSP 2020), Sep 2020, Krakow, Poland Communication dans un congrès hal-03106771v1
A Novel Event Based Image Sensor Architecture Mohamed Akrarai,G. Sicard,Laurent Fesquet IPSoC 2019, Dec 2019, Grenoble, France Communication dans un congrès hal-02956168v1
On-Line Adjustable Precision Computing A. Skaf,M. Ezzadeen,Mounir Benabdenbi,Laurent Fesquet Design & Technologies of Integrated Systems (DTIS 2019), Apr 2019, Mykonos, Greece Communication dans un congrès hal-02169965v1
Skilled manpower shortage in microelectronics A challenge for the french education microelectronics network Olivier Bonnaud,Laurent Fesquet,Ahmad Bsiesy 18th International Conference on Information Technology Based Higher Education and Training, ITHET 2019, Sep 2019, Magdeburg, Germany. pp.8937384, ⟨10.1109/ITHET46829.2019.8937384⟩ Communication dans un congrès hal-02472806v1
Microelectronics at the heart of the digital society: technological and training challenges Olivier Bonnaud,Laurent Fesquet 34th SBMicro – Symposium on Microelectronics and Devices, Aug 2019, Sao Paolo, Brazil Communication dans un congrès hal-02170143v1
An Event-Based Strategy for ASK demodulation Rodrigo Iga Jadue,Sylvain Engels,Laurent Fesquet 5th International Conference on Event-Based Control, Communication, and Signal Processing, May 2019, Vienna, Austria Communication dans un congrès hal-02157360v1
Asynchronous circuits for new computation paradigms Laurent Fesquet,Raphael Frisch,M. Faix,Jérémy Belot,Jean Simaticet al. IEEE International Nanodevices & Computing Conference (INC 2019), Apr 2019, Grenoble, France Communication dans un congrès hal-02165199v1
A Distributed Body-Biasing Strategy for Asynchronous Circuits Laurent Fesquet,Yoan Decoudu,Rodrigo Iga Jadue,Thiago Ferreira de Paiva Leite,O. Rolloffet al. 27th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC 2019), Oct 2019, Cuzco, Peru Communication dans un congrès hal-02170157v1
Learning-Based Reliability Assessment Method for Detection of Permanent Faults in Clockless Circuits R. Aquino Guazzelli,Matheus Garay Trindade,Laurent Fesquet,Rodrigo Possamai Bastos 30th European Symposium on Reliability of Electron Devices, Failure Physics and Analysis (ESREF 2019), Aug 2019, Toulouse, France Communication dans un congrès hal-02165113v1
Exploring a Non-conventional Testing Technique for Asynchronous Circuits R. Aquino Guazzelli,Matheus Garay Trindade,Laurent Fesquet,Rodrigo Possamai Bastos 21èmes Journées Nationales du Réseau Doctoral en Microélectronique (JNRDM 2019), Jun 2019, Montpellier, France Communication dans un congrès hal-03100560v1
Event-Based Image Sensors Laurent Fesquet,G. Sicard,Mamadou Diallo 5th International Conference on Event-Based Control, Communication, and Signal Processing (EBCCSP 2019), May 2019, Vienna, Austria Communication dans un congrès hal-02157361v1
An FPGA Implementation of High-Precision STR-based Time-to-Digital Converter Assia El Hadbi,Oussama Elissati,Laurent Fesquet 25th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2019), May 2019, Hirosaki, Japan Communication dans un congrès hal-02170005v1
Comparison of Synchronous and Asynchronous FIR Filter Architecture Yoan Decoudu,Jean Simatic,Pauline Alexandre,Katell Morin-Allory,Laurent Fesquet 5th International Conference on Event-Based Control, Communication, and Signal Processing, May 2019, Vienna, Austria Communication dans un congrès hal-02157364v1
Time-to-Digital Converters: A Literature Review and New Perspectives Assia El Hadbi,Oussama Elissati,Laurent Fesquet 3rd International Nordic-Mediterranean Workshop on Time-to-Digital Converters and Applications (NoMe–TDC 2019), May 2019, Vienna, Austria Communication dans un congrès hal-02170131v1
Desynchronizing Circuits Synthesized with CatapultC Yoan Decoudu,Jean Simatic,Katell Morin-Allory,Laurent Fesquet IPSoC 2019, Dec 2019, Grenoble, France Communication dans un congrès hal-02956177v1
A new synthesis approach for non-uniform filters in the log-scale: proof of concept Brigitte Bidégaray-Fesquet,Laurent Fesquet 5th International Conference on Event-Based Control, Communication, and Signal Processing, May 2019, Vienna, Austria. pp.1-7, ⟨10.1109/EBCCSP.2019.8836919⟩ Communication dans un congrès hal-02157365v1
From Signal Transition Graphs to Timing Closure – Application to Bundle-Data Circuits Grégoire Gimenez,Jean Simatic,Laurent Fesquet 25th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2019), May 2019, Hirosaki, Japan Communication dans un congrès hal-02299076v1
Stochastic sampling machine for Bayesian inference Raphael Frisch,M. Faix,Jérémy Belot,Laurent Fesquet,E. Mazer IEEE International Nanodevices & Computing Conference (INC 2019), May 2019, Grenoble, France Communication dans un congrès hal-02169995v1
Adjustable Precision Computing using Redundant Arithmetic Ali Skaf,Mona Ezzadeen,Mounir Benabdenbi,Laurent Fesquet 4th Workshop on Approximate Computing (AxC 2019), Mar 2019, Florence, Italy Communication dans un congrès hal-01971009v1
A Design Flow for Shaping Electromagnetic Emissions in Micropipeline Circuits Sophie Germain,Sylvain Engels,Laurent Fesquet 24th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2018), May 2018, Vienna, Austria Communication dans un congrès hal-01726928v1
Infinite Impulse Response Filters for Nonuniform Data Brigitte Bidégaray-Fesquet,Laurent Fesquet 3rd International Conference on Advances in Signal, Image and Video Processing (SIGNAL 2018), May 2018, Nice, France. pp.67-72 Communication dans un congrès hal-01802340v1
Level Shifter Architecture for Dynamically Biasing Ultra-Low Voltage Subcircuits of Integrated Systems Rodrigo Iga Jadue,Rodrigo Possamai Bastos,Thiago Ferreira de Paiva Leite,O. Rolloff,Mamadou Dialloet al. IEEE International Symposium on Circuits & Systems (ISCAS 2018), May 2018, Florence, Italy Communication dans un congrès hal-01726964v1
The practice in microelectronics: a mandatory complement of the online courses in the context of digital society Olivier Bonnaud,Laurent Fesquet 33rd Symposium on Microelectronics Technology and Devices (SBMICRO 2018), Aug 2018, Bento Gonçalves - Rio Grande do Sul, Brazil. ⟨10.1109/sbmicro.2018.8511430⟩ Communication dans un congrès hal-01827908v1
Strategy for Higher Education in electronic Circuits and Systems in the perspective of the up-coming digital society Olivier Bonnaud,Laurent Fesquet,Luc Hébrard IEEE 9th Latin American Symposium on Circuits & Systems (LASCAS 2018), Feb 2018, Puerto Vallarta, Mexico. ⟨10.1109/lascas.2018.8399942⟩ Communication dans un congrès hal-01726789v1
Sensing and sampling for low-power applications Laurent Fesquet Third International Conference on Advances in Signal, Image and Video Processing (SIGNAL 2018), May 2018, Nice, France Communication dans un congrès hal-01827401v1
Asynchronous Filters Laurent Fesquet,Brigitte Bidégaray-Fesquet 4th International Conference on Event-Based Control, Communications, and Signal Processing (EBCCSP 2018), Jun 2018, Perpignan, France Communication dans un congrès hal-01827398v1
Low Phase-Noise CMOS Quadrature Oscillator Based on a (Nx4)-stage Self-Timed Ring Oussama Elissati,Assia El Hadbi,Abdelkarim Cherkaoui,Sébastien Rieubon,Laurent Fesquet Conference on Design of Circuits and Integrated Systems (DCIS 2018), Nov 2018, Lyon, France Communication dans un congrès hal-01971021v1
Subthreshold Logic for Low-Area and Energy Efficient True Random Number Abdelkarim Cherkaoui,Mathieu Coustans,Laurent Fesquet,Christian Terrier,Stephanie Salgadoet al. IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL Chips, Apr 2018, Yokohama, Japan Communication dans un congrès hal-01827411v1
A Non-Intrusive Testing Technique for Detection of Trojans in Asynchronous Circuits Leonel Acunha Guimarães,Rodrigo Possamai Bastos,Thiago Ferreira de Paiva Leite,Laurent Fesquet Design, Automation and Test in Europe (DATE 2018), Mar 2018, Dresden, Germany. pp.1516-1519 Communication dans un congrès hal-01726979v1
A body built-in cell for detecting transient faults and dynamically biasing subcircuits of integrated systems Thiago Ferreira de Paiva Leite,Laurent Fesquet,Rodrigo Possamai Bastos European Symposium on Reliability of Electron Devices, Failure Physics and Analysis (ESREF'2018), Oct 2018, Aalborg, Denmark Communication dans un congrès hal-01986346v1
Static Timing Analysis of Asynchronous Bundled-data Circuits Grégoire Gimenez,Abdelkarim Cherkaoui,Guillaume Cognard,Laurent Fesquet 24th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2018), May 2018, Vienna, Austria Communication dans un congrès hal-01726936v1
Shaping Electromagnetic Emissions of Event-Driven Circuits Thanks to Genetic Algorithms Sophie Germain,Sylvain Engels,Laurent Fesquet Third International Conference on Advances in Signal, Image, and Video Processing (SIGNAL 2018), May 2018, Nice, France Communication dans un congrès hal-01827416v1
Fine Grain Body-Biasing: A strategy for asynchronous circuits Thiago Ferreira de Paiva Leite,Rodrigo Iga Jadue,Sylvain Engels,Rodrigo Possamai Bastos,Laurent Fesquet European Nanoelectronics Applications, Design and Technology Conference (ADTC), Jun 2018, Grenoble, France Communication dans un congrès hal-01828009v1
Event-based processing: a new paradigm for low-power Laurent Fesquet,Sophie Germain,Jean Simatic,Abdelkarim Cherkaoui,Tugdual Le Pelleteret al. 19th IEEE Mediterranean Electrotechnical Conference (IEEE Melecon’18), May 2018, Marrakesh, Morocco Communication dans un congrès hal-01726778v1
Innovation for education on Internet of things Olivier Bonnaud,Laurent Fesquet International Conference on Advanced Technology Innovation (ICATI 2018), Jun 2018, Krabi, Thailand Communication dans un congrès hal-01726922v1
An Asynchronous Fixed Priority Arbiter for High Throughput Time Correlated Single Photon Counting Systems Timothé Turko,Wilfried Uhring,Foudil Dadouche,Laurent Fesquet International Conference on Electronics, Circuits, and Systems (ICEC 2018), Dec 2018, Bordeaux, France. pp.765-768, ⟨10.1109/ICECS.2018.8618023⟩ Communication dans un congrès hal-01971018v1
Benchmarking of shared and distributed memory strategy for stochastic Bayesian machines Raphael Frisch,T. Hirtzlin,M. Faix,A. Cherkaoui,D. Querliozet al. IEEE International Conference on Rebooting Computing (ICRC 2018), Nov 2018, Washington DC, United States Communication dans un congrès hal-02170183v1
A cognitive stochastic machine based on Bayesian inference: a behavioral analysis Raphael Frisch,Marvin Faix,Emmanuel Mazer,Laurent Fesquet,Augustin Lux ICCI*CC 2018 - 17th IEEE International Conference on Cognitive Informatics and Cognitive Computing, Jul 2018, Berkeley, United States. pp.1-8 Communication dans un congrès hal-01867789v1
From events to data-driven processing Laurent Fesquet,Jean Simatic,Amani Darwish,Abdelkarim Cherkaoui,Sophie Germain 3rd International Conference on Event-Based Control, Communication and Signal Processing (EBCCSP 2017), May 2017, Funchal, Portugal Communication dans un congrès hal-01514219v1
On-the-fly and sub-gate-delay resolution TDC based on self-timed ring: A proof of concept Assia El Hadbi,Abdelkarim Cherkaoui,Oussama Elissati,Jean Simatic,Laurent Fesquet 15th IEEE International New Circuits and Systems Conference (NEWCAS), Jun 2017, Strasbourg, France. pp.305-308, ⟨10.1109/NEWCAS.2017.8010166⟩ Communication dans un congrès hal-01627367v1
A Subthreshold 30pJ/bit Self-timed Ring Based True Random Number Generator for Internet of Everything Mathieu Coustans,Christian Terrier,Thomas Eberhardt,Stephanie Salgado,Abdelkarim Cherkaouiet al. IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (IEEE S3S), Oct 2017, San Francisco, CA, United States. ⟨10.1109/S3S.2017.8308744⟩ Communication dans un congrès hal-01627338v1
IDEFI-FINMINA: a French educative project for the awareness, innovation and multidisciplinarity in microelectronics Olivier Bonnaud,Ahmad Bsiesy,Laurent Fesquet,Béatrice Pradarelli 27th European Association for Education in Electrical and Information Engineering Annual Conference (EAEEIE 2017), Jun 2017, Grenoble, France. ⟨10.1109/EAEEIE.2017.8768621⟩ Communication dans un congrès hal-01827895v1
CAR: on the highway towards desynchronization François Bertrand,Jean Simatic,Abdelkarim Cherkaoui,Anthony Maure,Laurent Fesquet 24th IEEE International Conference on Electronics, Circuits and Systems (ICECS), Dec 2017, Batumi, Georgia. pp.339-343, ⟨10.1109/ICECS.2017.8292047⟩ Communication dans un congrès hal-01626177v1
High Level Synthesis of an Event-Driven Windowing Process Saeed Mian Qaisar,Jean Simatic,Laurent Fesquet 3rd International Conference on Event-Based Control, Communication and Signal Processing (EBCCSP 2017), May 2017, Funchal, Portugal. pp.1-8, ⟨10.1109/EBCCSP.2017.8022807⟩ Communication dans un congrès hal-01514220v1
Detection of Layout-Level Trojans by Injecting Current Into Substrate and Digitally Monitoring Built-In Sensors Leonel Acunha Guimarães,Rodrigo Possamai Bastos,Laurent Fesquet Design Automation Conference, Jun 2017, Austin, TX, United States Communication dans un congrès hal-01627374v1
Event-Based Design Strategy for Circuit Electromagnetic Compatibility Sophie Germain,Sylvain Engels,Laurent Fesquet 3rd International Conference on Event-Based Control, Communication and Signal Processing (EBCCSP 2017), May 2017, Funchal, Portugal. pp.1-7, ⟨10.1109/EBCCSP.2017.8022808⟩ Communication dans un congrès hal-01514356v1
Body Bias Control Cells based on Negative- and Positive-Level Shifter Architectures in Technology FD-SOI 28 nm O. Rolloff,Rodrigo Iga Jadue,Thiago Ferreira de Paiva Leite,Rodrigo Possamai Bastos,Laurent Fesquet Journées Nationales du Réseau Doctoral en Micro-nanoélectronique (JNRDM 2017), Nov 2017, Strasbourg, France Communication dans un congrès hal-01721072v1
Self-timed Ring based True Random Number Generator: Threat model and countermeasures Grégoire Gimenez,Abdelkarim Cherkaoui,Raphael Frisch,Laurent Fesquet IEEE 2nd International Verification and Security Workshop (IVSW), Jul 2017, Thessaloniki, Greece. pp.31-38, ⟨10.1109/IVSW.2017.8031541⟩ Communication dans un congrès hal-01627350v1
Detection of Layout-Level Trojans by Monitoring Substrate with Preexisting Built-in Sensors Leonel Acunha Guimarães,Rodrigo Possamai Bastos,Laurent Fesquet IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2017), Jul 2017, Bochum, Germany. pp.290-295, ⟨10.1109/ISVLSI.2017.58⟩ Communication dans un congrès hal-01627346v1
Fine Body Biasing Island Strategy in FD-SOI Rodrigo Iga Jadue,Thiago Ferreira de Paiva Leite,O. Rolloff,Mamadou Diallo,Rodrigo Possamai Bastoset al. 20th IP-SoC Conference (IP-SOC), Dec 2017, Grenoble, France Communication dans un congrès hal-01721571v1
Back-end Limitations in Advanced Nodes and Alternatives Andrea Ayres,Olivier Rozeau,Bertrand Borot,Laurent Fesquet,Gérald Cibrarioet al. International Conference on Simulation of Semiconductor Processes and Devices (SISPAD 2017), Sep 2017, Kamakura, Japan Communication dans un congrès hal-01827898v1
A practical framework for specification, verification and design of self-timed pipelines Jean Simatic,Abdelkarim Cherkaoui,Bertrand François,Rodrigo Possamai Bastos,Laurent Fesquet 23rd IEEE International Symposium on Asynchronous Circuits and Systems (Async 2017), May 2017, San Diego, CA, United States. pp.65-72, ⟨10.1109/ASYNC.2017.16⟩ Communication dans un congrès hal-01512247v1
Innovative practice in the French microelectronics education targeting the industrial needs Olivier Bonnaud,Laurent Fesquet IEEE International Conference on Microelectronic Systems Education (MSE), May 2017, Banff, Canada. pp.15-18, ⟨10.1109/MSE.2017.7945075⟩ Communication dans un congrès hal-01627371v1
A Bayesian stochastic machine for sound source localization Raphael Frisch,Raphaël Laurent,Marvin Faix,Laurent Girin,Laurent Fesquetet al. ICRC 2017 - IEEE International Conference on Rebooting Computing, Nov 2017, Washington, DC, United States. pp.1-8, ⟨10.1109/ICRC.2017.8123681⟩ Communication dans un congrès hal-01644346v1
Nouveau dispositif ultra-précis de mesure du temps basé sur un oscillateur auto-séquencé Assia El Hadbi,Abdelkarim Cherkaoui,Oussama Elissati,Laurent Fesquet Colloque GdR SoC-SiP, Jun 2017, Talence, France Communication dans un congrès hal-01627376v1
High Precision Time Measurement using Self-Timed Ring Oscillator based TDC Assia El Hadbi,Abdelkarim Cherkaoui,Oussama Elissati,Laurent Fesquet European Frequency and Time Forum & International Frequency Control Symposium (EFTF 2017), Jul 2017, Besançon, France. pp.77-78, ⟨10.1109/FCS.2017.8088805⟩ Communication dans un congrès hal-01627362v1
Towards consistency checking between HDL and UPF descriptions Arthur Kalsing,Laurent Fesquet,Chouki Aktouf Forum on Specification & Design Languages (FDL 2017), Sep 2017, Verona, Italy. pp.1-6, ⟨10.1109/FDL.2017.8303897⟩ Communication dans un congrès hal-01627341v1
Event-driven Image Sensor Application: Event-driven Image Segmentation Amani Darwish,Hassan Abbas,Laurent Fesquet,Gilles Sicard 3rd International Conference on Event Based Control, Communication and Signal Processing (EBCCSP 2017), May 2017, Funchal, Portugal. pp.1-6, ⟨10.1109/EBCCSP.2017.8022820⟩ Communication dans un congrès hal-01514221v1
Seeking Low-power Synchronous/Asynchronous Systems: A FIR Implementation Case Study Ali Skaf,Jean Simatic,Laurent Fesquet IEEE International Symposium on Circuits and Systems (ISCAS 2017), May 2017, Baltimore, MD, United States. pp.1-4, ⟨10.1109/ISCAS.2017.8050379⟩ Communication dans un congrès hal-01514224v1
High-level synthesis for event-based systems Jean Simatic,Rodrigo Possamai Bastos,Laurent Fesquet Second International Conference on Event-Based Control, Communications, and Signal Processing (EBCCSP 2016), Jun 2016, Krakow, Poland. pp.1-7, ⟨10.1109/EBCCSP.2016.7605252⟩ Communication dans un congrès hal-01345745v1
AHLS_DESYNC: A Desynchronization Tool For High-Level Synthesis of Asynchronous Circuits Jean Simatic,Rodrigo Possamai Bastos,Laurent Fesquet Design, Automation and Test in Europe (DATE 2016), Mar 2016, Dresden, Germany Communication dans un congrès hal-01293842v1
MOOC and practices in electrical and information engineering: Complementary approaches Olivier Bonnaud,Laurent Fesquet 15th International Conference on Information Technology Based Higher Education and Training, ITHET 2016, Sep 2016, Istanbul, Turkey. ⟨10.1109/ITHET.2016.7760732⟩ Communication dans un congrès hal-01484547v1
Innovation in Higher Education: specificity of the microelectronics field Olivier Bonnaud,Laurent Fesquet 31st Symposium on Microelectronics Technology and Devices (SBMicro 2016), Aug 2016, Belo Horizonte, Brazil. pp.1-4, ⟨10.1109/SBMicro.2016.7731342⟩ Communication dans un congrès hal-01479178v1
QDI asynchronous circuits for low power applications: a comparative study in technology FD-SOI 28 nm Thiago Ferreira de Paiva Leite,Rodrigo Possamai Bastos,Laurent Fesquet Journées Nationales du Réseau Doctoral en Micro-Nanoélectronique (JNRDM'16), May 2016, Toulouse, France Communication dans un congrès hal-01524092v1
Simple Tri-State Logic Trojans Able to Upset Properties of Ring Oscillators Leonel Acunha Guimarães,Rodrigo Possamai Bastos,Thiago Ferreira de Paiva Leite,Laurent Fesquet 11th International Conference on Design &Technology of Integrated Systems in Nanoscale Era (DTIS'16), Apr 2016, Istanbul, Turkey. pp.1-6, ⟨10.1109/DTIS.2016.7483811⟩ Communication dans un congrès hal-01431177v1
Event-based design for mitigating energy in electronic systems Laurent Fesquet,Jean Simatic,Amani Darwish,Abdelkarim Cherkaoui OAGM & ARW Joint Workshop on "Computer Vision and Robotics" , May 2016, Wels, Austria Communication dans un congrès hal-01345715v1
Asynchronous implementation of an event-driven adaptive filter Taha Beyrouthy,Ahmed Roshdy,Mohammad Salman,Saeed Mian Qaisar,Laurent Fesquet Second International Conference on Event-Based Control, Communications, and Signal Processing (EBCCSP 2016), Jun 2016, Krakow, Poland. pp.1-4, ⟨10.1109/EBCCSP.2016.7605274⟩ Communication dans un congrès hal-01345748v1
Practice in microelectronics education as a mandatory supplement to the future digital-based pedagogy: Strategy of the French national network Olivier Bonnaud,Laurent Fesquet 2016 11th European Workshop on Microelectronics Education (EWME), May 2016, Southampton, United Kingdom. pp.1-6, ⟨10.1109/EWME.2016.7496460⟩ Communication dans un congrès hal-01995588v1
Low-power event-driven image sensor Laurent Fesquet,Amani Darwish,G. Sicard The First International Conference on Advances in Signal, Image and Video Processing (SIGNAL 2016), Jun 2016, Lisbon, Portugal Communication dans un congrès hal-01345718v1
New asynchronous protocols for enhancing area and throughput in bundle-data pipelines Jean Simatic,Abdelkarim Cherkaoui,Rodrigo Possamai Bastos,Laurent Fesquet 29th Symposium on Integrated Circuits and Systems Design (SBCCI 2016), Aug 2016, Belo Horizonte, Brazil. pp.1-6, ⟨10.1109/SBCCI.2016.7724066⟩ Communication dans un congrès hal-01345749v1
Analysis of granularity for automatic biasing control in FDSOI technology with low-voltage supply O. Rolloff,Thiago Ferreira de Paiva Leite,Rodrigo Possamai Bastos,Laurent Fesquet Journées Nationales du Réseau Doctoral en Micro-Nanoélectronique (JNRDM'16), May 2016, Toulouse, France Communication dans un congrès hal-01524090v1
Comparison of Low-Voltage Scaling in Synchronous and Asynchronous FD-SOI Circuits Thiago Ferreira de Paiva Leite,Rodrigo Possamai Bastos,Rodrigo Iga Jadue,Laurent Fesquet 26th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS'16), Sep 2016, Bremen, Germany Communication dans un congrès hal-01524087v1
Delay partitioning helps reducing variability in 3DVLSI A. Ayres,O. Rozeau,B. Borot,Laurent Fesquet,M. Vinet 42nd European Solid-State Circuits Conference (ESSCIRC'16), Sep 2016, Lausanne, Switzerland. pp.75-78, ⟨10.1109/ESSCIRC.2016.7598246⟩ Communication dans un congrès hal-01524088v1
Levels, peaks, slopes... which sampling for which purpose? Brigitte Bidégaray-Fesquet,Laurent Fesquet Second International Conference on Event-Based Control, Communications, and Signal Processing, Jun 2016, Krakow, Poland. pp.1-6, ⟨10.1109/EBCCSP.2016.7605261⟩ Communication dans un congrès hal-01324990v1
Design of a Fully Asynchronous Image Sensor Reading System Amani Darwish,Leandro M.G. Rocha,Laurent Fesquet,G. Sicard Conference on Design of Circuits and Integrated Systems (DCIS), Nov 2015, Estoril, Spain. ⟨10.1109/DCIS.2015.7388583⟩ Communication dans un congrès hal-01293867v1
Guidelines on 3D VLSI design regarding the intermediate BEOL process influence A. Ayres,O. Rozeau,B. Borot,Laurent Fesquet,G. Cibrarioet al. IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), Oct 2015, Sonoma Valley, CA, United States. pp.1-2 Communication dans un congrès hal-01393435v1
Exploiting reliable features of asynchronous circuits for designing low-voltage components in FD-SOI technology O. Rolloff,Rodrigo Possamai Bastos,Laurent Fesquet 26th European Symposium on Reliability of Electron Devices, Failure Physics and Analysis (ESREF'15), Oct 2015, Toulouse, France Communication dans un congrès hal-01393437v1
A New Proposition on Hardware Trojan Activation Leonel Acunha Guimarães,Rodrigo Possamai Bastos,Laurent Fesquet Journées Nationales du Réseau Doctoral en Micro-nanoélectronique (JNRDM'15), May 2015, Bordeaux, France Communication dans un congrès hal-01524097v1
Data Sampling and Processing: Uniform vs. Non-Uniform Schemes Taha Beyrouthy,Laurent Fesquet,Robin Rolland 1st IEEE International Conference on Event-Based Control, Communication, and Signal Processing (EBCCSP), Jun 2015, Krakow, Poland. ⟨10.1109/EBCCSP.2015.7300665⟩ Communication dans un congrès hal-01293879v1
Sampling circuits for 1D and 2D sensors for low-power purpose Laurent Fesquet,A. Darwish,G. Sicard 11th International Conference on Sampling Theory and Applications (SampTA'15), May 2015, Washington, DC, United States. pp.430-434 Communication dans un congrès hal-01187353v1
Flot de conception pour l'ultra-faible consommation : échantillonage non-uniforme et électronique asynchrone Jean Simatic,Rodrigo Possamai Bastos,Laurent Fesquet Journées Nationales du Réseau Doctoral en Micro-nanoélectronique (JNRDM'15), May 2015, Bordeaux, France Communication dans un congrès hal-01524095v1
Correctly Sizing FIR Filter Architecture in the Framework of Non-uniform Sampling Jean Simatic,Laurent Fesquet,Brigitte Bidégaray-Fesquet 11th International Conference on Sampling Theory and Applications (SampTA'15), May 2015, Washington, DC, United States. pp.269-273, ⟨10.1109/SAMPTA.2015.7148894⟩ Communication dans un congrès hal-01187290v1
Communicating and smart objects: Multidisciplinary topics for the innovative education in microelectronics and its applications Olivier Bonnaud,Laurent Fesquet 2015 International Conference on Information Technology Based Higher Education and Training (ITHET), Jun 2015, Lisbon, Portugal. pp.1-5 Communication dans un congrès hal-01995598v1
A new methodology for implementing a distributed clock management system for low-power design Chadi Al Khatib,Mohamed Gana,Chouki Aktouf,Laurent Fesquet Workshop on High Performance Embedded Systems (HiPEAC'15), Jan 2015, Amsterdam, Netherlands Communication dans un congrès hal-01165604v1
Design of a Fully Asynchronous Image Sensor Reading A. Darwish,L. A. Rocha,Laurent Fesquet,G. Sicard Conference on Design of Circuits and Integrated Systems (DCIS'15), Nov 2015, Estoril, Portugal Communication dans un congrès hal-01444993v1
A Generic Clock Controller for Low Power Systems: Experimentation on an AXI Bus Chadi Al Khatib,Claire Aupetit,Cyril Chevalier,Chouki Aktouf,Gilles Sicardet al. IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC'15) , Oct 2015, Daejeon, North Korea Communication dans un congrès hal-01393420v1
Data Sampling and Processing: Uniform vs. Non-Uniform Schemes T. Beyrouthy,Laurent Fesquet,B. Rolland 1st IEEE International Conference on Event-Based Control, Communication and Signal Processing (EBCCSP'15), Jun 2015, Krakow, Poland Communication dans un congrès hal-01393405v1
Towards multidisciplinarity for microelectronics education: a strategy of the French national network Olivier Bonnaud,Laurent Fesquet International Conference on Microelectronic Systems Education (MSE'15), May 2015, Pittsburgh, PA, United States. pp.1-4 Communication dans un congrès hal-01187288v1
RTL Simulation of an Asynchronous Reading Architecture for an Event-driven Image Sensor A. Darwish,Laurent Fesquet,G. Sicard 1st IEEE International Conference on Event-Based Control, Communication and Signal Processing (EBCCSP'15), Jun 2015, Krakow, Poland Communication dans un congrès hal-01393402v1
A Self-timed Ring based True Random Number Generator with Monitoring and Entropy Assessment A. Cherkaoui,Laurent Fesquet,V. Fischer,A. Aubert University Booth at DATE 2015, Mar 2015, Grenoble, France. pp.session UB02.1 Communication dans un congrès hal-01166869v1
RTL Simulation of an Asynchronous Reading Architecture for an Event-driven Image Sensor Amani Darwish,Laurent Fesquet,G. Sicard 1st IEEE International Conference on Event-Based Control, Communication, and Signal Processing (EBCCSP), Jun 2015, Krakow, Poland. ⟨10.1109/EBCCSP.2015.7300666⟩ Communication dans un congrès hal-01293872v1
A method to automatically determine the Level-Crossing thresholds in non-uniform sampling and Processing Cansu Arslan,Julien Poujaud,Laurent Fesquet 1st IEEE International Conference on Event-Based Control, Communication, and Signal Processing (EBCCSP), Jun 2015, Krakow, Poland. ⟨10.1109/EBCCSP.2015.7300663⟩ Communication dans un congrès hal-01293857v1
A method to automatically determine the Level-Crossing thresholds in non-uniform sampling and Processing C. Arslan,J. Poujaud,Laurent Fesquet 1st IEEE International Conference on Event-Based Control, Communication and Signal Processing (EBCCSP'15), Jun 2015, Krakow, Poland Communication dans un congrès hal-01393400v1
Mitigating the data-deluge by an adequate sampling for low-power systems Laurent Fesquet,Tugdual Le Pelleter,Amani Darwish,Taha Beyrouthy,Brigitte Bidégaray-Fesquet ICCHA5 - 5th International Conference on Computational Harmonic Analysis, May 2014, Nashville, United States. pp.17 Communication dans un congrès hal-01061132v1
Self-timed rings as low-phase noise programmable oscillators Laurent Fesquet,Abdelkarim Cherkaoui,Oussama Elissati The 12th IEEE International New Circuits and Systems Conference (NEWCAS 2014), Jun 2014, Trois-Rivières, Canada. 4 p Communication dans un congrès ujm-01011287v1
A prospective on Education of New Generations of Devices in the FDSOI and FinFET Technologies: from the technological process to the Circuit Design Specifications Olivier Bonnaud,Laurent Fesquet SBMicro'2014, SBMicro (Brazil), Sep 2014, Aracaju, Brazil. pp.1-4, ⟨10.1109/SBMicro.2014.6940081⟩ Communication dans un congrès hal-01094543v1
Low data rate architecture for smart image sensor A. Darwish,G. Sicard,Laurent Fesquet Image Sensors and Imaging Systems, Feb 2014, San Francisco, California, United States. pp.9022-5 Communication dans un congrès hal-01060442v1
An asynchronous CMOS probabilistic computer Idea M. Faix,E. Mazer,Laurent Fesquet 20th International Symposium on Asynchronous Circuits and Systems (ASYNC), Fresh Idea Session, May 2014, Postdam, Germany Communication dans un congrès hal-01061108v1
Improvement of doctoral studies in Electrical and Information Engineering through the High level courses in Europe Olivier Bonnaud,Anne-Claire Salaün,Laurent Fesquet,Ahmad Bsiesy 25th Annual EAEEIE’14 International Conference, May 2014, Cesmes, Turkey Communication dans un congrès hal-01995619v1
Designing ultra-low power systems with non-uniform sampling and event-driven logic G. Roa,T. Le Pelleter,Agnès Bonvilain,A. Chagoya,Laurent Fesquet 27th Symposium on Integrated Circuits and Systems Design (SBCCI'14), Sep 2014, Aracaju, Sergipe, Brazil. pp.1-6 Communication dans un congrès hal-01131860v1
1-level Crossing Sampling Scheme for Low Data Rate Image Sensors A. Darwish,Laurent Fesquet,G. Sicard 12th IEEE International New Circuits and Systems Conference (NEWCAS'14), Jun 2014, Trois-Rivières, Canada. pp.289-292 Communication dans un congrès hal-01130645v1
Distributed Asynchronous Controllers for Clock Management in Low Power Systems Chadi Al Khatib,Claire Aupetit,Alexandre Chagoya,Cyril Chevalier,Gilles Sicardet al. 21st IEEE International Conference on Electronics Circuits and Systems (ICECS'14), Dec 2014, Marseille, France. pp.379-382 Communication dans un congrès hal-01132018v1
Trends in Nanoelectronic Education: From FDSOI and FinFET Technologies to Circuit Design Specifications Olivier Bonnaud,Laurent Fesquet The 10th European Workshop on Microelectronics Education (EWME 2014), May 2014, Tallinn, Estonia. pp.106 - 111, ⟨10.1109/EWME.2014.6877406⟩ Communication dans un congrès hal-01061123v1
Contrôle autonome d'un nano-drone par caméra externe Laurent Fesquet,Katell Morin-Allory,R. Robin Journées pédagogiques du CNFM (JPCNFM), Nov 2014, Saint-Malo, France Communication dans un congrès hal-01166159v1
Trends in nanoelectronic education from FDSOI and FinFET technologies to circuit design specifications Olivier Bonnaud,Laurent Fesquet 2014 10th European Workshop on Microelectronics Education (EWME), May 2014, Tallinn, France. pp.106-111 Communication dans un congrès hal-01995621v1
Innovating projects as a pedagogical strategy for the French network for education in microelectronics and nanotechnologies Olivier Bonnaud,Laurent Fesquet International Conference on Microelectronic Systems Education (MSE 2013), Jun 2013, Austin, Texas, United States. pp.5-8, ⟨10.1109/MSE.2013.6566690⟩ Communication dans un congrès hal-00862833v1
Empirical recovery of input nonlinearity in distributed element models P. Sliwinski,L. Berezowski,P. Wachel,G. Sicard,Laurent Fesquet 11th IFAC International Workshop on Adaptation and Learning in Control and Signal Processing (ALCOSP), Jul 2013, Caen, France. Paper ThS6T3.5 Communication dans un congrès hal-00862807v1
Statistical Static Timing Analysis of Conditional Asynchronous Circuits Using Model-Based Simulation E. Yahya,Laurent Fesquet,Y. Ismail,Marc Renaudin 19th International Symposium on Asynchronous Circuits and Systems (ASYNC), May 2013, Santa Monica, United States. pp.67-74 Communication dans un congrès hal-00842226v1
The new strategy based on Innovative Projects in Microelectronics and Nanotechnologies Olivier Bonnaud,Laurent Fesquet 28th Symposium on Microelectronics Technology and Devices (SBMicro 2013), Sep 2013, Curitiba, Brazil Communication dans un congrès hal-00919993v1
A Very High Speed True Random Number Generator with Entropy Assessment Abdelkarim Cherkaoui,Viktor Fischer,Laurent Fesquet,Alain Aubert Cryptographic Hardware and Embedded Systems -- CHES 2013 15th International Workshop on Cryptographic Hardware and Embedded Systems -- CHES 2013, Aug 2013, Santa Barbara, California, United States. pp.179-196 Communication dans un congrès ujm-00859906v1
True Random Numbers Generation Using Asynchronous Circuits Abdelkarim Cherkaoui,Viktor Fischer,Alain Aubert,Laurent Fesquet Journées scientifiques SEmba 2013, May 2013, St Germain au Mont d'Or, France Communication dans un congrès ujm-00840445v1
Non-uniform sampling pattern recognition based on atomic decomposition T. Le Pelleter,T. Beyrouthy,B. Rolland,Agnès Bonvilain,Laurent Fesquet 10th International Conference on Sampling Theory and Applications (SampTA 2013), Jul 2013, Bremen, Germany Communication dans un congrès hal-00842215v1
Low-power signal processing platform based on non-uniform sampling and event-driven circuitry T. Le Pelleter,T. Beyrouthy,Y. Leroy,Agnès Bonvilain,R. Rollandet al. Design, Automation and Test in Europe (DATE'13), Mar 2013, Grenoble, France Communication dans un congrès hal-00841614v1
A Self-timed Ring Based True Random Number Generator Abdelkarim Cherkaoui,Viktor Fischer,Alain Aubert,Laurent Fesquet International symposium on advanced research in asynchronous circuits and systems - ASYNC 2013, May 2013, Santa Monica - California, United States. pp.99-106 Communication dans un congrès ujm-00840593v1
New pedagogical experiment leading to awareness in nanosciences and nanotechnologies for young generations at secondary school E. Excoffon,F. Papillon,Laurent Fesquet,Ah. Bsiesy,Olivier Bonnaud International Conference on Information Technology Based Higher Education and Training (ITHET'12), Jun 2012, Istanbul, Turkey. pp.1-4, ⟨10.1109/ITHET.2012.6246049⟩ Communication dans un congrès hal-00747415v1
Self-Timed Rings as Entropy Sources A. Cherkaoui,Laurent Fesquet,V. Fischer,A. Aubert 18th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), May 2012, Copenhagen, Denmark Communication dans un congrès hal-00747383v1
Self-Timed Rings as Sources of Entropy A. Cherkaoui,V. Fischer,A. Aubert,Laurent Fesquet 6ème colloque du GDR SOC-SIP du CNRS, Jun 2012, Paris, France Communication dans un congrès hal-00747474v1
Comparison of Self-Timed Ring and Inverter Ring Oscillators as Entropy Sources in FPGAs Abdelkarim Cherkaoui,Viktor Fischer,Alain Aubert,Laurent Fesquet Design Automation and Test in Europe (DATE 2012), Mar 2012, Dresden, Germany. pp.1-6 Communication dans un congrès ujm-00667639v1
Méthode à faible coût de calcul et robuste pour la détection d'un motif dans un signal T. Le Pelleter,Agnès Bonvilain,Laurent Fesquet 15ème Journées Nationales du Réseau Doctoral en Microélectronique (JNRDM'12), Jun 2012, Marseille, France. pp.Oral 1-04 Communication dans un congrès hal-00749388v1
A New Robust True Random Numbers Generator Using Self-Timed Rings Abdelkarim Cherkaoui,Viktor Fischer,Laurent Fesquet,Alain Aubert Cryptographic architectures embedded in reconfigurable devices - Cryptarchi 2012, Jun 2012, Saint-Etienne, France Communication dans un congrès ujm-00712552v1
Asynchronous circuit performance analysis, fundamentals and efficient tools E. Yahya,Laurent Fesquet,Marc Renaudin 18th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), May 2012, Copenhagen, Denmark Communication dans un congrès hal-00749396v1
Vérification formelle Katell Morin-Allory,Laurent Fesquet 12èmes Journées Pédagogiques de la Coordination Nationale pour la Formation en Micro et nanoélectronique (JPCNFM’12), Nov 2012, Saint-Malo, France Communication dans un congrès hal-01413187v1
Self-Timed Rings: A Promising Solution for Generating High-Speed High Resolution Low-Phase Noise Clocks O. Elissati,S. Rieubon,E. Yahya,Laurent Fesquet 18th International Conference on Very Large Scale Integration (VLSISOC), Sep 2010, Madrid, Spain. pp.22-42, ⟨10.1007/978-3-642-28566-0_2⟩ Communication dans un congrès hal-00750195v1
Controling variability and energy by design Laurent Fesquet CMOS Emerging Technologies, Jul 2012, Vancouver, BC, Canada Communication dans un congrès hal-00747376v1
Model of a Simple yet effective Operational Amplifier F. Paugnat,Laurent Fesquet,Katell Morin-Allory International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD'12), Sep 2012, Seville, Spain. pp.165-168, ⟨10.1109/SMACD.2012.6339443⟩ Communication dans un congrès hal-00746450v1
A Performance Comparison Between the SystemC-AMS Models of Computation F. Paugnat,L. Bousquet,Katell Morin-Allory,Laurent Fesquet edaWorkshop, May 2011, Dresden, Germany. pp.13-18 Communication dans un congrès hal-00652944v1
An event-driven FIR filter: Design and implementation T. Beyrouthy,Laurent Fesquet 22nd IEEE International Symposium on Rapid System Prototyping (RSP'11), May 2011, Karlsruhe, Germany. pp.59 - 65, ⟨10.1109/RSP.2011.5929976⟩ Communication dans un congrès hal-00646298v1
Analog Design Abstraction Levels and SystemC AMS Models of Computation F. Paugnat,L. Bousquet,Laurent Fesquet SystemC-AMS Day 2011: Industry Adoption of the SystemC AMS Standard, May 2011, Dresden, Germany Communication dans un congrès hal-00646292v1
Process variability robust energy-efficient control for nano-scaled complex SoCs H. Zakaria,Laurent Fesquet 10th Edition of Faible Tension Faible Consommation (FTFC'11), May 2011, Marrakech, Morocco. pp.95 - 98, ⟨10.1109/FTFC.2011.5948928⟩ Communication dans un congrès hal-00646301v1
Synthesis of Quasi Delay Insensitive Monitors A. Porcher,Katell Morin-Allory,Laurent Fesquet 7th Conference on PhD Research in Microelectronics and Electronics (PRIME'11), Jul 2011, Madonna Di Campiglio (Trento), Italy. pp.225 - 228, ⟨10.1109/PRIME.2011.5966274⟩ Communication dans un congrès hal-00646662v1
An Asynchronous FIR Filter Architecture coupled to a Level-Crossing ADC T. Beyrouthy,Laurent Fesquet,M. Greitans,R. Shavelis,R. Robin 9th International Conference on Sampling Theory and Applications (SampTA'11), May 2011, Singapore, Singapore. pp.Fr2S12.2 - P0190 Communication dans un congrès hal-00646262v1
C-elements for hardened self-timed circuits F. Ouchet,Katell Morin-Allory,Laurent Fesquet 21st International Workshop on Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation (PATMOS'11), Sep 2011, Madrid, Spain. pp.247-256, ⟨10.1007/978-3-642-24154-3_25⟩ Communication dans un congrès istex hal-00652365v1
Asynchronous Self-Timed Rings for Randomness Generation Abdelkarim Cherkaoui,Alain Aubert,Viktor Fischer,Laurent Fesquet International Workshops on Cryptographic Architectures Embedded in Reconfigurable Devices, Jun 2011, bochum, Germany Communication dans un congrès ujm-00667827v1
Ring Oscillators : The Asynchronous Alternative O. Elissati,S. Rieubon,Laurent Fesquet 10th Edition of Faible Tension Faible Consommation (FTFC'11), May 2011, Marrakech, Morocco. pp.34-37, ⟨10.1109/FTFC.2011.5948910⟩ Communication dans un congrès hal-00646552v1
Does Asynchronous technology bring robustness in synchronous circuit monitoring? A. Porcher,Katell Morin-Allory,Laurent Fesquet Forum on specification & Design Languages (FDL'11), Sep 2011, Oldenburg, Germany Communication dans un congrès hal-00646699v1
Non-Uniform Filter Design in the Log-Scale Brigitte Bidégaray-Fesquet,Laurent Fesquet SampTA'11- 9th International Conference on Sampling Theory and Applications, May 2011, Singapore, Singapore. pp.art. 150 Communication dans un congrès hal-00646287v1
Formal Verification of C-element Circuits C. Yan,Laurent Fesquet,F. Ouchet,Katell Morin-Allory IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'11), Apr 2011, Ithaca (NY), United States. pp.55 - 64, ⟨10.1109/ASYNC.2011.14⟩ Communication dans un congrès hal-00624249v1
Configurable Self-Timed Ring Oscillators J. Hamon,Laurent Fesquet 9th IEEE International NEWCAS Conference, Jun 2011, Bordeaux, France. pp.249 - 252, ⟨10.1109/NEWCAS.2011.5981302⟩ Communication dans un congrès hal-00646646v1
Tiempo Asynchronous Design Flow Tutorial - Modeling and Debug N. Leblond,A. Porcher,Laurent Fesquet Design Automation Conference (DAC'11), Jun 2011, San Diego, United States Communication dans un congrès hal-00646693v1
A refinement process for top-down mixed-signal designs thanks to SystemC-AMS F. Paugnat,Katell Morin-Allory,Laurent Fesquet IEEE 9th International New Circuits and Systems Conference (NEWCAS), Jun 2011, Bordeaux, France. pp.378 - 381, ⟨10.1109/NEWCAS.2011.5981249⟩ Communication dans un congrès hal-00646654v1
Thinking and Designing Differently: The Asynchronous Alternative Laurent Fesquet Dresden Microelectronic Academy, Sep 2011, Dresden, Germany Communication dans un congrès hal-00671323v1
A modular synthesis method for low-power QDI state machines K. Alsayeg,Laurent Fesquet,G. Sicard,Marc Renaudin 9th IEEE International NEWCAS Conference, Jun 2011, Bordeaux, France. pp.185 - 188, ⟨10.1109/NEWCAS.2011.5981286⟩ Communication dans un congrès hal-00646564v1
Combined Peak and Level-Crossing Sampling Scheme M. Greitans,R. Shavelis,Laurent Fesquet,T. Beyrouthy 9th International Conference on Sampling Theory and Applications (SampTA'11), May 2011, Singapore, Singapore. pp.Fr2S12.1 - P0158 Communication dans un congrès hal-00646274v1
Delay Insensitivity Does Not Mean Slope Insensitivity! F. Ouchet,Katell Morin-Allory,Laurent Fesquet IEEE Symposium on Asynchronous Circuits and Systems (ASYNC'10), May 2010, Grenoble, France. pp.176 - 184, ⟨10.1109/ASYNC.2010.27⟩ Communication dans un congrès hal-00492923v1
Targeting ultra-low power consumption with non-uniform sampling and filtering Laurent Fesquet,Gilles Sicard,Brigitte Bidégaray-Fesquet ISCAS'10 - IEEE International Symposium on Circuits and Systems, May 2010, Paris, France. pp.3585-3588, ⟨10.1109/ISCAS.2010.5537804⟩ Communication dans un congrès hal-00517684v1
A novel High-Speed Multi-Phase Oscillator on Asynchronous Rings O. Elissati,E. Yahya,Laurent Fesquet,S. Rieubon IEEE International Conference on Microelectronics ICM'2010, Dec 2010, Cairo, Egypt Communication dans un congrès hal-00556662v1
A High-Speed High-Resolution Low-Phase Noise Oscillator Using Self-Timed Rings O. Elissati,E. Yahya,S. Rieubon,Laurent Fesquet 18th IEEE/IFIP International Conference on VLSI and System-on-Chip (VLSI-SoC), Sep 2010, Madrid, Spain. pp.173-178 Communication dans un congrès hal-00547400v1
Optimizing and Comparing CMOS Implementations of the C-element in 65nm technology: Self-Timed Ring Case O. Elissati,E. Yahya,S. Rieubon,Laurent Fesquet International Workshop on Power And Timing Modeling, Optimization and Simulation (PATMOS 2010), Sep 2010, Grenoble, France Communication dans un congrès hal-00569495v1
Synthesis of asynchronous monitors for critical electronic systems A. Porcher,Katell Morin-Allory,Laurent Fesquet IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS'10), Apr 2010, Vienna, Austria. pp.329 - 334, ⟨10.1109/DDECS.2010.5491756⟩ Communication dans un congrès hal-00517676v1
Conception conjointe logiciel-matériel et microprocesseur embarqué, validation sur plateforme FPGA Vincent Fristot,Sylvain Huet,Laurent Fesquet,Robin Rolland CETSIS 2010 - 8ème Colloque sur l'Enseignement des Technologies et des Sciences de l'Information et des Systèmes, Mar 2010, Grenoble, France. pp.n.c Communication dans un congrès hal-00505110v1
Integrated Asynchronous Regulation for Nanometric Technologies Hatem Zakaria,Sylvain Durand,Nicolas Marchand,Laurent Fesquet VARI 2010 - 1st European workshops on CMOS Variability, May 2010, Montpellier, France. pp.86-91 Communication dans un congrès hal-00492946v1
Updates on the Potential of Clock-Less Logics to Strengthen Cryptographic Circuits against Side-Channel Attacks Sylvain Guilley,Sumanta Chaudhuri,Laurent Sauvage,Jean-Luc Danger,Taha Beyrouthyet al. IEEE International Conference on Electronics and Systems (ICECS'09), Dec 2009, Hammamet, Tunisia. pp.351 - 354, ⟨10.1109/ICECS.2009.5411008⟩ Communication dans un congrès hal-00472064v1
A fully nonuniform approach to FIR filtering Brigitte Bidégaray-Fesquet,Laurent Fesquet SAMPTA'09 - International Conference on Sampling Theory and Applications, May 2009, Marseille, France. pp.129: 1-4 Communication dans un congrès hal-00453350v1
Asynchronous Design: A Promising Paradigm for Electronic Circuits and Systems E. Yahya,Laurent Fesquet IEEE International Conference on Electronics and Systems (ICECS'09), Dec 2009, Hammamet, Tunisia. pp.339 - 342, ⟨10.1109/ICECS.2009.5411009⟩ Communication dans un congrès hal-00472069v1
Programmable/Stoppable Oscillator Based on Self-Timed Rings E. Yahya,O. Elissati,H. Zakaria,Laurent Fesquet,Marc Renaudin 15th IEEE Symposium on Asynchronous Circuits and Systems (ASYNC '09), May 2009, UNC Chapel Hill, United States. pp.3-12, ⟨10.1109/ASYNC.2009.12⟩ Communication dans un congrès hal-00417834v1
DPA robust S-BOX implementation on a secure asynchronous FPGA T. Beyrouthy,Laurent Fesquet Cryptarchi Conference, Czech republic, June 24-27, Jun 2009, Prague, Czech Republic Communication dans un congrès hal-00422280v1
Direct mapping of sequential QDI controllers K. Alsayeg,Laurent Fesquet,G. Sicard,D. Rios,Marc Renaudin DATE 2009, Ph D Forum poster, Apr 2009, Nice, France Communication dans un congrès hal-00422286v1
Controlling Energy and Process Variability in System-on-Chips: needs for control theory Laurent Fesquet,H. Zakaria 3rd IEEE Multi-conference on Systems and Control (MSC'09), Jul 2009, Saint Petersburg, Russia. pp.302-307 Communication dans un congrès hal-00422305v1
Optimizing speed and consumption of QDI controllers using direct mapping synthesis K. Alsayeg,Laurent Fesquet,G. Sicard,D. Rios,Marc Renaudin Joint 7th International IEEE Northeast Workshop on Circuits and Systems and TAISA Conference (NEWCAS-TAISA'09), Jun 2009, Toulouse, France. pp.151-154 Communication dans un congrès hal-00421682v1
A secure asynchronous FPGA for an embedded system Laurent Fesquet,T. Beyrouthy PhD Forum DATE, Apr 2009, Nice, France Communication dans un congrès hal-00416804v1
RAT-based formal verification of QDI asynchronous controllers K. Alsayeg,Katell Morin-Allory,Laurent Fesquet Forum on specifications and Design Languages (FDL'09), Sep 2009, Nice, Sophia Antipolis, France. pp.1-6 Communication dans un congrès hal-00471574v1
Oscillation Period and Power Consumption in Configurable Self-Timed Rings Oscillators O. Elissati,E. Yahya,Laurent Fesquet,S. Rieubon Joint 7th International IEEE Northeast Workshop on Circuits and Systems and TAISA ConferenceIEEE NEWCAS-TAISA Conference, Jun 2009, Toulouse, France. pp.131-134, ⟨10.1109/NEWCAS.2009.5290439⟩ Communication dans un congrès hal-00418905v1
Effective Resolution of an Adaptive Rate ADC Saeed Mian Qaisar,Laurent Fesquet,Marc Renaudin SAMPTA'09, May 2009, Marseille, France. Special session on sampling and industrial applications Communication dans un congrès hal-00451847v1
Computationally Efficient Adaptive Rate Sampling and Adaptive Resolution Analysis Saeed-Mian Qaisar,Laurent Fesquet,Marc Renaudin Fifth International Conference on Computer Vision, Image and Signal Processing (CVISP 2008), Jul 2008, Prague, Czech Republic. pp.85-90 Communication dans un congrès hal-00323944v1
An Improved Quality Adaptative Rate Filtering Technique Based on the Level Crossing Sampling Saeed-Mian Qaisar,Laurent Fesquet,Marc Renaudin Fifth International Conference on Computer Vision, Image and Signal Processing (CVISP 2008), Jul 2008, Prague, Czech Republic. pp.79-84 Communication dans un congrès hal-00323939v1
Self-Timed Implementation of an Impulse Radio Synchronisation Acquisition Algorithm J. Hamon,B. Miscopein,J. Schwoerer,Laurent Fesquet,Marc Renaudin Conference on Design and Architectures for Signal and Image Processing (DASIP'08), Nov 2008, Bruxelles, Belgium Communication dans un congrès hal-00354345v1
A secure asynchronous configurable cell: an embedded programmable logic for smartcards Laurent Fesquet,Taha Beyrouthy Workshop on Cryptographic Architectures embedded in reconfigurable devices (CryptArchi 2008), Jun 2008, Tregastel, France Communication dans un congrès hal-00293681v1
Initiation à la conception de VLSI numériques Lorena Anghel,Laurent Fesquet,Katell Morin-Allory 10èmes journées pédagogiques CNFM, Nov 2008, Saint-Malo, France Communication dans un congrès hal-00385508v1
High-level time-accurate model for the design of self-timed ring oscillators Jérémie Hamon,Laurent Fesquet,Benoit Miscopein,Marc Renaudin 14th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'08), Apr 2008, Newcastle upon Tyne, United Kingdom. pp.29-38, ⟨10.1109/ASYNC.2008.16⟩ Communication dans un congrès hal-00288379v1
Integrated Asynchronous Regulation for Nanometric Technologies: Application to an Embedded Parallel System H. Zakaria,Laurent Fesquet,S. Durand,Carolina Albea-Sanchez,Y. Thonnardet al. MINATEC CROSSROADS'08, Jun 2008, Grenoble, France Communication dans un congrès hal-00561636v1
Synthesis of asynchronous QDI FSM based on optimized sequencers K. Alsayeg,Laurent Fesquet,G. Sicard,D. Rios,Marc Renaudin 34th European Conference on Solid-States Circuits (ESSCIRC'08), ESS Fringe Poster Session, Sep 2008, Edinburgh, United Kingdom Communication dans un congrès hal-00354513v1
An improved quality filtering technique for time varying signals based on the level crossing sampling S.-M. Qaisar,Laurent Fesquet,Marc Renaudin International Conference of Signals and Electronic Systems 2008 (ICSES'08), Sep 2008, Krakow, Poland. pp.355-358 Communication dans un congrès hal-00327665v1
Implémentation en logique asynchrone d'un algorithme de synchronisation de signaux radio impulsionnelle Jérémie Hamon,Benoit Miscopein,Jean Schwoerer,Laurent Fesquet,Marc Renaudin 7ème journées d'études Faible Tension Faible Consommation (FTFC'08), May 2008, Louvain, Belgique Communication dans un congrès hal-00291826v1
A Secure Programmable Architecture with a Dedicated Tech-mapping Algorithm: Application to a Crypto-Processor T. Beyrouthy,Laurent Fesquet,Alin Razafindraibe,S. Chaudhuri,S. Guilleyet al. 23rd International Conference on Design of Circuits and Integrated Systems (DCIS'08), Nov 2008, Grenoble, France. pp.session 3b3 Communication dans un congrès hal-00346734v1
Secure Asynchronous FPGA for Embedded Systems (SAFE) T. Beyrouthy,Alin Razafindraibe,Laurent Fesquet,Marc Renaudin Colloque du GDR SoC-SiP, Jun 2007, Paris, France Communication dans un congrès hal-00178955v1
Adaptive Rate Filtering for a Signal Driven Sampling Scheme S.-M. Qaisar,Laurent Fesquet,Marc Renaudin 32nd IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP'07), Apr 2007, Honolulu, Hawaï, United States. pp.1465 - 1468, ⟨10.1109/ICASSP.2007.367124⟩ Communication dans un congrès hal-00174460v1
A Reconfigurable Cell for a Multi-Style Asynchronous FPGA Philippe Hoogvorst,Sylvain Guilley,Alin Razafindraibe,Taha Beyrouthy,Laurent Fesquet RecoSoC: Reconfigurable Communication-centric Systems-on-Chip, Jun 2007, Montpellier, France. pp.15-22 Communication dans un congrès hal-00222887v1
A Novel Asynchronous e-FPGA Architecture for Security Applications Taha Beyrouthy,Alin Razafindraibe,Laurent Fesquet,Marc Renaudin,Sumanta Chaudhuriet al. ICFPT 2007 - IEEE International Conference on Field-Programmable Technology, Dec 2007, Kitakyusyu, Japan. pp.369-372, ⟨10.1109/FPT.2007.4439288⟩ Communication dans un congrès hal-04510604v1
Adaptive Rate Sampling and Filtering for Low Power Embedded Systems S.-M. Qaisar,Laurent Fesquet,Marc Renaudin International Workshop on Sampling Theory and Applications (SampTA'07), Jun 2007, Thessaloniki, Greece Communication dans un congrès hal-00174475v1
Asynchronous online monitoring of logical and temporal assertions Katell Morin-Allory,Laurent Fesquet,D. Borrione 10th Forum on Specification and Design Languages (FDL'07), Sep 2007, Barcelona, Spain Communication dans un congrès hal-00222895v1
Computationally Efficient Adaptive Rate Sampling and Filtering S.-M. Qaisar,Laurent Fesquet,Marc Renaudin 15th European Signal Processing Conference (EUSIPCO'07), Sep 2007, Poznan, Poland. pp.2139-2143 Communication dans un congrès hal-00178982v1
State-holding in Look-Up Tables: application to asynchronous logic Laurent Fesquet,Bertrand Folco,M. Steiner,Marc Renaudin 14th IFIP International Conference on Very Larage Scale Integration (VLSI-SoC’06), 2006, Nice, France. pp.12-18 Communication dans un congrès hal-00130402v1
Spectral analysis of a signal driven sampling scheme S.-M. Qaisar,Laurent Fesquet,Marc Renaudin 14th European Signal Processing Conference (EUSIPCO’06), 2006, Florence, France. 5 p Communication dans un congrès hal-00130550v1
Asynchronous Assertion Monitors for multi-Clock Domain System Verification Katell Morin-Allory,Laurent Fesquet,D. Borrione Seventeenth IEEE International Workshop on Rapid System Prototyping (RSP'06), IEEE, 2006, Chania, Crète, Greece. pp.98- 102, ⟨10.1109/RSP.2006.9⟩ Communication dans un congrès hal-00134475v1
Asynchronous on-line monitoring of PSL assertions Katell Morin-Allory,Laurent Fesquet,D. Borrione Seventeenth IEEE International Workshop on Rapid System Prototyping (RSP'06), IEEE, 2006, Chania, Crète, Greece. pp.98 102, ⟨10.1109/RSP.2006.9⟩ Communication dans un congrès hal-00130525v1
Gals systems prototyping using multiclock fpgas and asynchronous network-on-chips Laurent Fesquet,J. Quartana,Marc Renaudin,S. Renane,A. Baixas Field Programmable Logic and Applications, 2005. International Conference on, 2005, Tampere, Finland. pp.299-304 Communication dans un congrès hal-00012722v1
FPGA architecture for multi-style asynchronous logic [full-adder example] N. Huot,H. Dubreuil,Laurent Fesquet,Marc Renaudin Design, Automation and Test in Europe, 2005. Proceedings, 2005, Los Alamitos, CA, United States. pp.32 - 33 Vol. 1, ⟨10.1109/DATE.2005.15⟩ Communication dans un congrès hal-00009568v1
On-Line Assertion-Based Verification with Proven Correct Monitors D. Borrione,Z.W. Liu,Katell Morin-Allory,P. Ostier,Laurent Fesquet 3rd IEEE International Conference on Information and Communication Technology (ICICT'05), December 5-6, 2005, 2005, cairo, Egypt. pp.123-143 Communication dans un congrès hal-00078798v1
PSL-based online monitoring of digital systems D. Borrione,M. Liu,P. Ostier,Laurent Fesquet Forum on specification and Design Languages (FDL'05), 2005, Lausanne, Switzerland. pp.465-478 Communication dans un congrès hal-00103450v1
Spectral analysis of level crossing sampling scheme F. Aeschlimann,E. Allier,Laurent Fesquet,M. Renaudin International Workshop on Sampling theory and application (SAMPTA'05), Jul 2005, Samsun, Turkey Communication dans un congrès hal-01393272v1
Secure asynchronous circuits design and prototyping Marc Renaudin,Ghislain Fraidy Bouesse,Y. Monnet,Laurent Fesquet 3rd International Workshop on Cryptographic Architectures Embedded in Reconfigurable Devices (CryptArchi'05), Jun 2005, Saint-Etienne, France Communication dans un congrès hal-00540339v1
A programmable logic architecture for prototyping clockless circuits Laurent Fesquet,Marc Renaudin 15th International Conference on Field Programmable Logic & Applications (FPL'05), 2005, Tampere, Finland. pp.293- 298, ⟨10.1109/FPL.2005.1515737⟩ Communication dans un congrès hal-00104360v1
Modular Asynchronous Network-on-Chip: Application to GALS Systems Rapid Prototyping J. Quartana,Laurent Fesquet,Marc Renaudin 15th IFIP International Conference on Very Large Scale Integration Systems (VLSI-SoC'05), 2005, Perth, Australia. pp.397-402 Communication dans un congrès hal-00104233v1
Technology Mapping for Area Optimized Quasi Delay Insensitive Circuits Bertrand Folco,V. Bregier,Laurent Fesquet,Marc Renaudin 15th IFIP Int. Conf. on Very Large Scale Integration Systems (VLSI-SoC'05), October 17-19, 2005, Perth, France. pp.146-151 Communication dans un congrès hal-00101464v1
FPGA Architecture for Multi-Style Asynchronous Logic N. Huot,H. Dubreuil,Laurent Fesquet,Marc Renaudin DATE'05, Mar 2005, Munich, Germany. pp.32-33 Communication dans un congrès hal-00181491v1
Asynchronous Systems on Programmable Logic Laurent Fesquet,J. Quartana,Marc Renaudin Reconfigurable Communication-centric SoCs (ReCoSoC'05), 2005, Montpellier, France. pp.105-112 Communication dans un congrès hal-00105236v1
Modeling and synthesis of multi-rail multi-protocol QDI circuits V. Bregier,Bertrand Folco,Laurent Fesquet,M. Renaudin Thirteenth International Workshop on Logic and Synthesis, Temecula Creek (IWLS'04), Jun 2004, Temecula, California, États-Unis Communication dans un congrès hal-01384270v1
Asynchronous FIR filters: towards a new digital processing chain F. Aeschlimann,E. Allier,Laurent Fesquet,Marc Renaudin Asynchronous Circuits and Systems, 2004. Proceedings. 10th International Symposium on, 2004, Crete, Greece. pp.198-206, ⟨10.1109/ASYNC.2004.1299302⟩ Communication dans un congrès hal-00009570v1
Asynchronous ADCs: Design Methodology and Case study G. Sicard,M. Renaudin,E. Allier,Laurent Fesquet 8th International Workshop on ADC modelling and testing (IWADC'03), Sep 2003, Perugia, Italie. pp.29-32 Communication dans un congrès hal-01391655v1
Estimation et optimisation de la consommation d'énergie des circuits asynchrones K. Slimani,A. Sirianni,Laurent Fesquet,Y. Remond,G. Sicardet al. 4èmes journées d'études Faible Tension, Faible Consommation (FTFC'03), May 2003, Paris, France. pp.59-64 Communication dans un congrès hal-01377243v1
Conversion analogique-numérique faible consommation : conception asynchrone et echantillonnage irrégulier G. Sicard,Marc Renaudin,E. Allier,Laurent Fesquet 4ème Colloque sur le Traitement Analogique de l'Information, du Signal, et ses Applications (TAISA'03), Sep 2003, Louvain-La-Neuve, Belgique. pp.53-56 Communication dans un congrès hal-01376269v1
A new class of asynchronous A/D converters based on time quantization E. Allier,G. Sicard,Laurent Fesquet,Marc Renaudin Proceedings-Ninth-International-Symposium-on-Asynchronous-Circuits-and-Systems, 2003, Vancouver, BC, Canada. pp.196-205, ⟨10.1109/ASYNC.2003.1199179⟩ Communication dans un congrès hal-00009583v1
High-level modeling and design of asynchronous arbiters for on-chip communication systems Jean-Baptiste Rigaud,J. Quartana,Laurent Fesquet,Marc Renaudin Proceedings-2002-Design,-Automation-and-Test-in-Europe-Conference-and-Exhibition., 2002, Paris, France. pp.1090, ⟨10.1109/DATE.2002.998447⟩ Communication dans un congrès hal-00009606v1
Low-power asynchronous A/D conversion E. Allier,Laurent Fesquet,Marc Renaudin,G. Sicard Integrated-Circuit-Design.-Power-and-Timing-Modeling,-Optimization-and-Simulation.-12th-International-Workshop,-PATMOS-2002.-Proceedings-Lecture-Notes-in-Computer-Science, 2002, Séville, Spain. pp.81-91 Communication dans un congrès hal-00009604v1
Implementing asynchronous circuits on LUT based FPGAs Quoc Thai-Ho,Jean-Baptiste Rigaud,Laurent Fesquet,Marc Renaudin,R. Rolland Field-Programmable-Logic-and-Applications.-Reconfigurable-Computing-Is-Going-Mainstream.-12th-International-Conference,-FPL-2002.-Proceedings-Lecture-Notes-in-Computer-Science-Vol.2438., 2002, Montpellier, France. pp.36-46 Communication dans un congrès hal-00009602v1
Synthesis of QDI asynchronous circuits from DTL-style petri-net Laurent Fesquet,Anh Vu Dinh Duc,M. Renaudin 11th IEEE/ACM International Workshop on Logic & Synthesis (IWLS'02), Jun 2002, New Orleans, Louisiana, États-Unis Communication dans un congrès hal-01391638v1
Dynamic voltage scheduling for real time asynchronous systems M.E. Salhiene,Laurent Fesquet,Marc Renaudin Integrated-Circuit-Design.-Power-and-Timing-Modeling,-Optimization-and-Simulation.-12th-International-Workshop,-PATMOS-2002.-Proceedings-Lecture-Notes-in-Computer-Science-, 2002, Séville, Spain. pp.390-9 Communication dans un congrès hal-00009603v1
Modeling and design of asynchronous priority arbiters for on-chip communication systems Laurent Fesquet,Marc Renaudin,Jean-Baptiste Rigaud,J. Quartana IFIP International Conference On Very Large Scale Integration (VLSI-SOC'01), Dec 2001, Montpellier, France. pp.313-324 Communication dans un congrès hal-00009605v1

Poster de conférence (2)

FINMINA: a French national project to promote Innovation in Higher Education in Microelectronics and Nanotechnologies Olivier Bonnaud,Laurent Fesquet,Pascal Nouet,Tayeb Mohammed-Brahim ITHET: Information Technology Based Higher Education and Training, Sep 2014, York, United Kingdom. Information Technology Based Higher Education and Training, 2014, ⟨10.1109/ITHET.2014.7155715⟩ Poster de conférence hal-01122242v1
Les technologies du futur: FDSOI et FinFET Olivier Bonnaud,Laurent Fesquet Conseil d'orientation 2013 du GIP-CNFM, Jan 2014, Paris, France Poster de conférence hal-01094646v1

Ouvrages (3)

Sampling Theory in Signal and Image Processing Laurent Fesquet,B. Torrésani Sampling Publishing ISSN: 1530-6429, pp.Vol. 10, N°1-2, 2011, Special Issue on 8th International Conference on Sampling Theory and Applications (SampTA'09, May 18-22, 2009 in Marseille) Ouvrages hal-00688417v1
SAMPTA'09, International Conference on SAMPling Theory and Applications Laurent Fesquet,Bruno Torrésani Laurent Fesquet and Bruno Torrésani. pp.384, 2010 Ouvrages hal-00495456v1
IEEE European Solid-State Circuits Conference (ESSCIRC) A. Kaiser,M. Brillouet,Laurent Fesquet,S. Cristoloveanu ieee, 2005, 0-7803-9205-1. ⟨10.1109/ESSCIR.2005.1541467⟩ Ouvrages hal-02162250v1

Chapitre d'ouvrage (12)

A Methodology for Automated Consistency Checking Between Different Power-Aware Descriptions Arthur Kalsing,Laurent Fesquet,C. Aktouf Languages, Design Methods, and Tools for Electronic System Design, springer, pp.107-127, 2018 Chapitre d'ouvrage hal-01989546v1
Digital Filtering with Nonuniformly Sampled Data: From the Algorithm to the Implementation Laurent Fesquet,Brigitte Bidégaray-Fesquet Marek Miskowicz. Event-Based Control and Signal Processing, CRC Press, 2015, 9781482256550 Chapitre d'ouvrage hal-01228969v1
Self Adaption in SoCs H. Zakaria,E. Yahya,Laurent Fesquet Phan Cong-Vinh. Autonomic Networking-on-Chip (Bio-inspired Specification, Development, and Verification), c, 287 p., 2011, Series: Embedded Multi-Core Systems Chapitre d'ouvrage hal-00653931v1
Optimizing and Comparing CMOS Implementations of the C-element in 65nm technology: Self-Timed Ring Case O. Elissati,E. Yahya,Laurent Fesquet,S. Rieubon Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation, 20th International Workshop, PATMOS 2010, Grenoble, France, September 7-10, 2010, Springer, pp.137-149, 2010, Lecture Notes in Computer Science, Vol. 6448 Chapitre d'ouvrage hal-00564558v1
Asynchronous on-line monitoring of logical and temporal assertions Katell Morin-Allory,Laurent Fesquet,Benjamin Roustan,Dominique Borrione Villar Eugenio. Embedded Systems Specification and Design Languages: Selected Contributions from FDL'07, 10, Springer, pp.243-253, 2008, Lecture Notes in Electrical Engineering, ⟨10.1007/978-1-4020-8297-9_17⟩ Chapitre d'ouvrage istex hal-00293779v1
Physical Design of FPGA Interconnect to Prevent Information Leakage Sumanta Chaudhuri,Sylvain Guilley,Philippe Hoogvorst,Jean-Luc Danger,Taha Beyrouthyet al. Woods, R.; Compton, K.; Bourganis, C.; Diniz, P.C. Reconfigurable Computing: Architecture, Tools, and Applications, 4943, Springer, pp.87-98, 2008, Lecture Notes in Computer Science, ⟨10.1007/978-3-540-78610-8_11⟩ Chapitre d'ouvrage istex hal-00299487v1
VLSI-SOC: From Systems to Chips, (selected contributions from VLSI-SoC 2005) Jérôme Quartana,Laurent Fesquet,Marc Renaudin VLSI-SOC: From Systems to Chips, (selected contributions from VLSI-SoC 2005), Springer, pp.195-207, 2007 Chapitre d'ouvrage emse-00429856v1
Technology mapping for area optimized quasi delay insensitive circuits Bertrand Folco,V. Brégier,Laurent Fesquet,Marc Renaudin Reis, Ricardo; Osseiran, Adam; Pfleiderer, Hans-Joerg. VLSI-SOC: From Systems to Silicon, Springer, pp.55-69, Vol. 240, 2007, Collection :: IFIP International Federation for Information Processing, ⟨10.1007/978-0-387-73661-7_5⟩ Chapitre d'ouvrage hal-00185940v1
Modular asynchronous Network-on-Chip: application to GALS systems rapid prototyping J. Quartana,Laurent Fesquet,Marc Renaudin VLSI-SOC: From Systems to Chips, (selected contributions from VLSI-SoC 2005), Springer, pp.195-207, 2007, IFIP International Federation for Information Processing, ⟨10.1007/978-0-387-73661-7_13⟩ Chapitre d'ouvrage hal-00192008v1
PSL-based online monitoring of digital systems D. Borrione,M. Liu,P. Ostier,Laurent Fesquet Vachoux A. in Advances in Design and Specification Languages for SoCs, Springer Verlag, Berlin, Germany, pp.5-22, 2006, CHDL series Chapitre d'ouvrage hal-00147582v1
Low Power Asynchronous Processors K. Slimani,J. Fragoso,Laurent Fesquet,Marc Renaudin Low-Power Electronics Design, CRC Press, 912p., Chapter 22; Volume: 1, 2004, Series: Computer Engineering Chapitre d'ouvrage hal-00016113v1
Modeling and design of asynchronous priority arbiters for on-chip Jean-Baptiste Rigaud,J. Quartana,Laurent Fesquet,Marc Renaudin SOC Design Methodologies Series: IFIP International Federation for Information Processing, Kluwer Academic Publishers, 496 p., pp.313-324, 2002, Vol. 90; Chapitre d'ouvrage hal-00016196v1

Brevet (12)

Système de mesure évènementielle comprenant un capteur maitre, et procédé de mesure associé Laurent Fesquet,Skandar Basrour,Marco Erickson Passy Kengani France, N° de brevet: FR3161947. 2025 Brevet hal-05534083v1
Chaotic physical true random number generator and associated method Martial Defoort,Skandar Basrour,Laurent Fesquet United States, Patent n° : 20230266945. 2023 Brevet hal-04190531v1
Mélangeur à N Chemins à réjection d’harmoniques Ali Alshakoush,Sylvain Bourdel,Florence Podevin,Estelle Lauga-Larroze,Laurent Fesquet France, N° de brevet: FR3125934A1. 2023 Brevet hal-04332066v1
Générateur physique chaotique de nombres aléatoires vrais et procédé associé Martial Defoort,Skandar Basrour,Laurent Fesquet France, N° de brevet: FR3112874. 2022 Brevet hal-03827179v1
Method for generating a unique data specific to an integrated silicon circuit Grégoire Gimenez,Abdelkarim Cherkaoui,Laurent Fesquet France, N° de brevet: FR3106424 (B1) 2022-02-11, EP3851995 (A1). 2021 Brevet hal-04023699v1
System and Method for Managing Requests in an Asynchronous Pipeline Sylvain Engels,Laurent Fesquet,Sophie Germain United States, Patent n° : US2020184110 (A1). 2020 Brevet hal-02952926v1
Circuit and Method for Protecting Asynchronous Circuits Laurent Fesquet,A. Cherkaoui,Grégoire Gimenez,Raphael Frisch France, Patent n° : WO/2020/008229. 2020 Brevet hal-02952917v1
Générateurs de nombres aléatoires vrais Laurent Fesquet,J. Hamon,A. Cherkaoui France, N° de brevet: FR 12 51079. 2012 Brevet hal-00750215v1
Signal Processing for AsynchronouS Systems (SPASS) Brigitte Bidégaray-Fesquet,Laurent Fesquet France, Patent n° : IDDN.FR.001.080019.000.S.P.2012.000.31235. 2012 Brevet hal-01910147v1
Logiciel D. Borrione,L. Ferro,Laurent Fesquet,Katell Morin-Allory,Y. Oddoset al. France, Patent n° : FR.001.220016.000.S.P.2009.000.31500. 2009 Brevet hal-00578146v1
Method and device for analog-digital conversion, comprises a comparator delivering a pair of control signals to an increment-decrement block for computing new digital value Marc Renaudin,G. Sicard,Laurent Fesquet,E. Allier France, Patent n° : FR2835365. http://v3.espacenet.com/textdoc?DB=EPODOC&IDX=FR2835365&F=0. 2005 Brevet hal-00008382v1
Procédé et dispositif de conversion analogique-numérique Marc Renaudin,G. Sicard,Laurent Fesquet,E. Allier France, N° de brevet: FR2835365. http://v3.espacenet.com/results?sf=a&FIRST=1&CY=ep&LG=fr&DB=EPODOC&TI=&AB=&PN=+FR2835365&AP=&PR=&PD=&PA=&IN=&EC=&IC=&=&=&=&=&=. 2003 Brevet hal-00008383v1

Autre publication scientifique (1)

A new synthesis approach for non-uniform filters in the log-scale: proof of concept Brigitte Bidégaray-Fesquet,Laurent Fesquet 2012, 12 p Autre publication scientifique hal-00750061v1

Pré-publication, Document de travail (2)

Non-uniform filter design Brigitte Bidégaray-Fesquet,Laurent Fesquet 2015 Pré-publication, Document de travail hal-01187269v1
A Reconfigurable Programmable Logic Block for a Multi-Style Asynchronous FPGA resistant to Side-Channel Attacks Philippe Hoogvorst,Sylvain Guilley,Sumanta Chaudhuri,Jean-Luc Danger,Taha Beyrouthyet al. 2024 Pré-publication, Document de travail hal-04510614v1

Rapport (1)

An Energy-Efficient Architecture for Nanometric Technologies with Strong Robustness to Process Variability : Design of a GALS node based on a MIPS R2000 processor Sylvain Durand,H. Zakaria,Laurent Fesquet,Nicolas Marchand [Research Report] GIPSA-lab. 2013 Rapport (rapport de recherche) hal-00675609v1

HDR (1)

Systèmes intégrés asynchrones et de traitement des signaux non uniformément échantillonnés Laurent Fesquet Micro et nanotechnologies/Microélectronique. Institut National Polytechnique de Grenoble - INPG, 2008 HDR tel-00280679v1