Laurent Sauvage
Publications
Publications
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Masked Vector Sampling for HQCSECRYPT 2025: 22nd International Conference on Security and Cryptography, Jun 2025, Bilbao, Spain. pp.750-758, ⟨10.5220/0013637400003979⟩ |
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EM Fault Injection-Induced Clock Glitches: From Mechanism Analysis to Novel Sensor Design30th IEEE International Symposium on On-Line Testing and Robust System Design (IOLTS) (2024), Jul 2024, Rennes, France. ⟨10.1109/IOLTS60994.2024.10616074⟩ |
High-Order Collision Attack Vulnerabilities in Montgomery Ladder Implementations of RSASPACE, Dec 2023, Roorkee, India, India. pp.139-161, ⟨10.1007/978-3-031-51583-5_9⟩ |
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A Tale of Two Models: Discussing the Timing and Sampling EM Fault Injection ModelsFDTC 2023 – Twentieth Workshop on Fault Diagnosis and Tolerance in Cryptography, Sep 2023, Prague, Czech Republic |
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Highlighting Two EM Fault Models While Analyzing a Digital Sensor Limitations2023 Design, Automation & Test in Europe Conference & Exhibition (DATE), Apr 2023, Antwerp, Belgium. pp.1-2, ⟨10.23919/DATE56975.2023.10137124⟩ |
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A Genetic Algorithm for a Spectre Attack Agnostic to Branch PredictorsSeventh Workshop on Computer Architecture Research with RISC-V (CARRV 2023), Jun 2023, Orlanda (Florida), United States |
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Formal Evaluation and Construction of Glitch-resistant Masked FunctionsIEEE International Symposium on Hardware Oriented Security and Trust, HOST 2021, Dec 2021, Virtual, United States |
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Multiple and Reproducible Fault Models on Micro-Controller using Electromagnetic Fault Injection2021 JOINT IEEE INTERNATIONAL SYMPOSIUM ON ELECTROMAGNETIC COMPATIBILITY, SIGNAL & POWER INTEGRITY, AND EMC EUROPE, Jul 2021, Virtuel, France. ⟨10.1109/EMC/SI/PI/EMCEurope52599.2021.9559288⟩ |
Detection of Side-channel Lleakage Through Glitches Using an Automated ToolInternational Conference on Defense Systems: Architectures and Technologies (DAT’2020), Apr 2020, Constantine, Algeria |
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Characterization of Electromagnetic Fault Injection on a 32-bit Microcontroller Instruction Buffer2020 Asian Hardware Oriented Security and Trust Symposium (AsianHOST), Dec 2020, Kolkata, India. pp.1-6, ⟨10.1109/AsianHOST51057.2020.9358270⟩ |
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Impact of Intentional Electromagnetic Interference on Pure Combinational Logic2019 International Symposium on Electromagnetic Compatibility - EMC EUROPE, Sep 2019, Barcelone, Spain. pp.398-403 |
Method for Identifying Individual Electronic Devices Focusing on Differences in Spectrum Emissions2019 Joint International Symposium on Electromagnetic Compatibility and Asia-Pacific International Symposium on Electromagnetic Compatibility, Sep 2019, Sapporo, Japan |
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Cache-Timing Attacks Still Threaten IoT Devices3rd International Conference on Codes, Cryptology, and Information Security (C2SI 2019), Apr 2019, Rabat, Morocco. pp.13-30, ⟨10.1007/978-3-030-16458-4_2⟩ |
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Characterization at Logical Level of Magnetic Injection Probes2019 Joint International Symposium on Electromagnetic Compatibility and Asia-Pacific International Symposium on Electromagnetic Compatibility, Jun 2019, Sapporo, Japan |
Pre-Silicon Embedded System Evaluation as new EDA for Security VerificationInternational Verification and Security Workshop (IVSW), Jun 2018, Platja d’Aro, Spain |
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Electromagnetic Fault Injection: from Attack to Countermeasure DesignCryptoIC, Sep 2017, Chengdu, China |
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Differential Fault Analysis on MidoriInformation and Communications Security - 18th International Conference, ICICS 2016, Singapore, November 29 - December 2, 2016, Proceedings, Sep 2016, Singapore, Singapore. pp.307-317, ⟨10.1007/978-3-319-50011-9_24⟩ |
Secure Silicon: Towards Virtual PrototypingTRUDEVICE, Nov 2016, Barcelona, Spain |
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Delay PUF Assessment Method Based on Side-Channel and Modeling AnalyzesTrustCom-16, Aug 2016, Tianjin, China |
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High Precision Fault Injections on the Instruction Cache of ARMv7-M ArchitecturesHOST 2015: IEEE International Symposium on Hardware-Oriented Security and Trust, May 2015, Washington, United States. ⟨10.1109/HST.2015.7140238⟩ |
Electromagnetic Fault injection: Impact on FPGAJournée Sécurité Numérique du GDR SoC-SiP, Jun 2015, Paris, France |
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Injection électromagnétique de fautes sur FPGA : caractérisation & contre-mesureCRYPTO'PUCES, May 2015, Porquerolles, France |
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A Pre-processing Composition for Secret Key Recovery on Android Smartphone8th IFIP International Workshop on Information Security Theory and Practice (WISTP), Jun 2014, Heraklion, Crete, Greece. pp.76-91, ⟨10.1007/978-3-662-43826-8_6⟩ |
Electric Probes for Fault Injection AttackAPEMC, Aug 2013, Melbourne, Australia |
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Hardware Trojan Horses in Cryptographic IP CoresFDTC (Fault Detection and Tolerance in Cryptography), Aug 2013, Santa Barbara, United States. pp.15-29, ⟨10.1109/FDTC.2013.15⟩ |
Limitations of Fault Injection Attack Based on Immunity to Radiated EM Field StandardsEMC Europe, Sep 2013, Brugge, Belgium |
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Introduction to Recent Research on EM Information LeakageAsia-Pacific Symposium on Electromagnetic Compatibility (APEMC2013), May 2013, Melbourne, Australia. pp.320-323 |
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A Fault Model for Conducted Intentional ElectroMagnetic InterferencesEMC, Aug 2012, Pittsburgh, United States. pp.788-793, ⟨10.1109/ISEMC.2012.6351664⟩ |
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Efficient mapping of EM radiation associated with information leakage for cryptographic devicesEMC, Aug 2012, Pittsburgh, United States. pp.794-799, ⟨10.1109/ISEMC.2012.6351663⟩ |
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A Small and High-performance Coprocessor for Fingerprint Match-On-CardDSD, Sep 2012, Cesme/Izmir, Turkey. ⟨10.1109/DSD.2012.14⟩ |
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Vade Mecum on Side-Channels Attacks and Countermeasures for the Designer and the EvaluatorDesign & Technology of Integrated Systems, Apr 2011, Athens, Greece. pp.6, ⟨10.1109/DTIS.2011.5941419⟩ |
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Fault Injection ResilienceFault Diagnosis and Tolerance in Cryptography, Aug 2010, Santa Barbara, United States. pp.51-65, ⟨10.1109/FDTC.2010.15⟩ |
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Successful Attack on an FPGA-based WDDL DES Cryptoprocessor Without Place and Route Constraints.Design, Automation & Test in Europe Conference & Exhibition, 2009. DATE '09., Apr 2009, NICE, France. pp.640-645 |
Updates on the Potential of Clock-Less Logics to Strengthen Cryptographic Circuits against Side-Channel AttacksIEEE International Conference on Electronics and Systems (ICECS'09), Dec 2009, Hammamet, Tunisia. pp.351 - 354, ⟨10.1109/ICECS.2009.5411008⟩ |
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Combined SCA and DFA Countermeasures Integrable in a FPGA Design FlowReConFig, Dec 2009, Cancún, Mexico. pp.213 - 218, ⟨10.1109/ReConFig.2009.50⟩ |
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Evaluation of Countermeasure Implementations Based on Boolean Masking to Thwart Side-Channel AttacksSCS, Nov 2009, Jerba, Tunisia. 6 p., ⟨10.1109/ICSCS.2009.5412597⟩ |
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Area Optimization of Cryptographic Co-Processors Implemented in Dual-Rail with Precharge Positive LogicInternational Conference on Field Programmable Logic and Applications, Sep 2008, Heidelberg, Germany. pp.161-166, ⟨10.1109/FPL.2008.4629925⟩ |
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Silicon-level Solutions to Counteract Passive and Active AttacksFDTC, Aug 2008, Washington, DC, United States. pp.3-17, ⟨10.1109/FDTC.2008.18⟩ |
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Evaluation of Power-Constant Dual-Rail Logic as a Protection of Cryptographic Applications in FPGAsSecure System Integration and Reliability Improvement, Jul 2008, Yokohama, Japan. pp.16-23, ⟨10.1109/SSIRI.2008.31⟩ |
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Shall we trust WDDL?Future of Trust in Computing, Jun 2008, Berlin, Germany. pp.208-215, ⟨10.1007/978-3-8348-9324-6_22⟩ |
Place-and-route impact on the security of DPL designs in FPGAs2008 IEEE International Workshop on Hardware-Oriented Security and Trust (HOST), Jun 2008, Anaheim, United States. pp.26-32, ⟨10.1109/HST.2008.4559042⟩ |
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Post-layout Security Evaluation Methodology Against Probing AttacksNguyen-Son Vo; Van-Phuc Hoang; Quoc-Tuan Vien. Industrial Networks and Intelligent Systems. 7th EAI International Conference, INISCOM 2021, Hanoi, Vietnam, April 22-23, 2021, Proceedings, 379, Springer International Publishing, pp.465-482, 2021, Lecture Notes of the Institute for Computer Sciences, Social Informatics and Telecommunications Engineering, 978-3-030-77423-3. ⟨10.1007/978-3-030-77424-0_37⟩ |
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Fault Analysis Assisted by SimulationJakub Breier; Xiaolu Hou; Shivam Bhasin. Automated Methods in Cryptographic Fault Analysis, Springer International Publishing, pp.263-277, 2019, 978-3-030-11332-2. ⟨10.1007/978-3-030-11333-9_12⟩ |
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Unrolling Cryptographic Circuits: A Simple Countermeasure Against Side-Channel AttacksJosef Pieprzyk. Topics in Cryptology - CT-RSA 2010. The 10th Cryptographers' Track at the RSA Conference 2010, San Francisco, CA, USA, March 1-5, 2010. Proceedings, 5985, Springer Berlin Heidelberg, pp.195-207, 2010, Lecture Notes in Computer Science, 978-3-642-11924-8. ⟨10.1007/978-3-642-11925-5_14⟩ |
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Overview of Dual Rail with Precharge Logic Styles to Thwart Implementation-Level Attacks on Hardware Cryptoprocessors2009 |
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Successful Attack on an FPGA-based Automatically Placed and Routed WDDL+ Crypto Processor.2008 |
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ElectroMagnetic Radiations of FPGAs: High Spatial Resolution Cartography and Attack of a Cryptographic Module2008 |
Description des nouvelles attaques et de leurs caractéristiques en termes d'efficacité et de modèles de fautes[Contrat] 2KCPV1206, Télécom ParisTech. 2014 |