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Marcello TRAIOLA
63
Documents
Presentation
I obtained my “laurea” degrees (BSc and MSc) in Computer Engineering - cum laude - both from the University of Naples “Federico II” , in Italy, in 2012 and 2016, respectively.
In 2019, I obtained my Ph.D. degree in Computer Engineering from the University of Montpellier , working at the Laboratory of Computer Science, Robotics and Microelectronics of Montpellier (LIRMM) , in France.
In 2013, I was at Fiat Chrysler Automobiles (now part of the group Stellantis ) Information Technology, Excellence and Methods S.p.A. (FCA ITEM), Pomigliano d’arco (Naples, Italy), as a software engineer intern.
From October 2019 to January 2020, I was in the United States for a four-months internship at the semiconductor company MediaTek USA Inc , as an R&D engineer.
From February 2020 to September 2021, I was with the Heterogeneous Systems Design team at the Lyon Institute of Nanotechnology (Institut des Nanotechnologies de Lyon, INL), in France, as a post-doctoral researcher.
Since October 2021, I am with the TARAN research group (ex CAIRN) at the Inria research center at Rennes University , in France, first as a post-doctoral researcher and then as Inria permanent researcher (CRCN), since October 2022
My fields of research concern mainly emerging computing paradigms, with a focus on hardware digital design, testing, and reliability. I am an IEEE member.
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MaxiMals: A Low-cost Hardening Technique for Large Vision TransformersRADECS 2024 - Conference is an annual on RADiation Effects on Components and Systems, RADECS Association, Sep 2024, Maspalomas, Canary Islands, Spain. pp.1-5
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Special Session: Reliability Assessment Recipes for DNN AcceleratorsVTS 2024 - IEEE VLSI Test Symposium, Apr 2024, Tempe AZ USA, United States. pp.131788 - 131828, ⟨10.1109/access.2022.3229767⟩
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Reliability Assessment of Large DNN Models: Trading Off Performance and AccuracyVLSI-SoC 2024 - IFIP/IEEE International Conference on Very Large Scale Integration, Delft University of Technology and University of Abdelmalek Saadi University, Oct 2024, Tanger, Morocco. pp.1-10, ⟨10.5286/ISIS.E.RB2300036)⟩
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Efficient Neural Networks: from SW optimization to specialized HW acceleratorsESWEEK 2024 - Embedded System Week, Sep 2024, Raleigh (NC), United States. pp.1-2
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Cross-Layer Reliability Evaluation and Efficient Hardening of Large Vision Transformers ModelsDesign Automation Conference (DAC), Jun 2024, San Francisco, United States
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Reliability and Security of AI HardwareETS 2024 - 29th IEEE European Test Symposium, May 2024, The Hague, Netherlands. pp.1-10
Conference papers
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Approximate Fault-Tolerant Neural Network SystemsETS 2024 - 29th IEEE European Test Symposium, May 2024, La Haye, Netherlands. pp.1-10, ⟨10.1109/ETS61313.2024.10567290⟩
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Impact of Compiler Optimizations on the Reliability of a RISC-V-based CoreDFT 2024 - 37th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, Oct 2024, Oxfordshire, United Kingdom. pp.1-1
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Combining Fault Simulation and Beam Data for CNN Error Rate Estimation on RISC-V Commercial PlatformsIOLTS 2024 - 30th IEEE International Symposium on On-Line Testing and Robust System Design, INRIA/IRISA Rennes, Jul 2024, Rennes, France. pp.1-8
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Approximate Computing for Test and Test of Approximate ComputingIEEE Workshop on Top Picks in VLSI Test and Reliability, Nov 2024, San Diego, United States. pp.1-2
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harDNNing: a machine-learning-based framework for fault tolerance assessment and protection of DNNsETS 2023 - IEEE European Test Symposium, May 2023, Venise, Italy. pp.1-6
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Input-aware accuracy characterization for approximate circuitsDSN-W 2023 - 53rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops, Jun 2023, Porto, Portugal. pp.179-182, ⟨10.1109/DSN-W58399.2023.00050⟩
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Impact of Transient Faults on Timing Behavior and Mitigation with Near-Zero WCET OverheadECRTS 2023 - 35th Euromicro Conference on Real-Time Systems, Jul 2023, Vienna, Austria. pp.1-22, ⟨10.4230/LIPIcs.ECRTS.2023.15⟩
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Impact of High-Level-Synthesis on Reliability of Neural Network Hardware AcceleratorsNSREC 2023 - IEEE Nuclear & Space Radiation Effects Conference, Jul 2023, Kansas City (US), United States. pp.1-5
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Exploiting assertions mining and fault analysis to guide RTL-level approximationDATE 2023 – 26th IEEE/ACM Design, Automation and Test in Europe, Apr 2023, Antwerp, Belgium. ⟨10.23919/DATE56975.2023.10136949⟩
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Design with low complexity fine-grained Dual Core Lock-Step (DCLS) RISC-V processorsDSN 2023 - 53rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks, Jun 2023, Porto, Portugal. pp.224-229, ⟨10.1109/DSN-S58398.2023.00062⟩
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A machine-learning-guided framework for fault-tolerant DNNsDATE 2023 – 26th IEEE/ACM Design, Automation and Test in Europe, Apr 2023, Antwerp, Belgium. pp.1-2
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Towards Dependable RISC-V Cores for Edge Computing DevicesIOLTS 2023 – IEEE 29th International Symposium on On-Line Testing and Robust System Design, Jul 2023, Crete, Greece. ⟨10.1109/iolts59296.2023.10224862⟩
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Selective Hardening of Critical Neurons in Deep Neural NetworksDDECS 2022 - 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, Apr 2022, Prague, Czech Republic. pp.136-141, ⟨10.1109/DDECS54261.2022.9770168⟩
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Input-Aware Approximate ComputingAQTR 2022 - IEEE International Conference on Automation, Quality and Testing, Robotics, May 2022, Cluj-Napoca, Romania. pp.1-6, ⟨10.1109/AQTR55203.2022.9801944⟩
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A Design Space Exploration Framework for Memristor-Based Crossbar ArchitectureDDECS 2022 - 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, Apr 2022, Prague, Czech Republic. pp.38-43, ⟨10.1109/DDECS54261.2022.9770145⟩
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Assertion-aware approximate computing design exploration on behavioral modelsLATS 2022 - IEEE 23rd Latin American Test Symposium, Sep 2022, Montevideo, Uruguay. pp.1-6, ⟨10.1109/LATS57337.2022.9936945⟩
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Improving the Fault Resilience of Neural Network Applications Through Security MechanismsDSN 2022 - The 52nd Annual IEEE/IFIP International Conference on Dependable Systems and Networks, Jun 2022, Baltimore, United States. ⟨10.1109/DSN-S54099.2022.00017⟩
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Design Space Exploration of Approximation-Based Quadruple Modular Redundancy Circuits2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD), Nov 2021, Munich, Germany. pp.1-9, ⟨10.1109/ICCAD51958.2021.9643561⟩
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Pros and Cons of Fault Injection Approaches for the Reliability Assessment of Deep Neural NetworksLATS 2021 - IEEE 22nd Latin American Test Symposium, Oct 2021, Punta del Este, Uruguay. pp.1-5, ⟨10.1109/LATS53581.2021.9651807⟩
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Efficient Neural Network Approximation via Bayesian Reasoning2021 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), Apr 2021, Vienna, Austria. pp.45-50, ⟨10.1109/DDECS52668.2021.9417057⟩
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Emerging Technologies: Challenges and Opportunities for Logic Synthesis2021 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), Apr 2021, Vienna (virtual), Austria. pp.93-98, ⟨10.1109/DDECS52668.2021.9417062⟩
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Emerging Computing Devices: Challenges and Opportunities for Test and ReliabilityETS 2021 - 26th IEEE European Test Symposium, May 2021, Bruges, Belgium. pp.1-10, ⟨10.1109/ETS50041.2021.9465409⟩
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Reducing Overprovision of Triple Modular Reduncancy Owing to Approximate ComputingIOLTS 2021 - 27th IEEE International Symposium on On-Line Testing and Robust System Design, Jun 2021, Torino, Italy. pp.1-7, ⟨10.1109/IOLTS52814.2021.9486699⟩
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A Novel Test Flow for Approximate Digital CircuitsDATE 2020 - EDAA/IEEE/ACM Design Automation & Test in Europe Conference, PhD Forum, Mar 2020, Grenoble, France
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Design, Verification, Test and In-Field Implications of Approximate Computing SystemsETS 2020 - 25th IEEE European Test Symposium, May 2020, Tallinn, Estonia. pp.1-10, ⟨10.1109/ETS48528.2020.9131557⟩
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Maximizing Yield for Approximate Integrated CircuitsDATE 2020 - 23rd Design, Automation and Test in Europe Conference and Exhibition, Mar 2020, Grenoble, France. pp.810-815, ⟨10.23919/DATE48585.2020.9116341⟩
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Evaluating Data Encryption Effects on the Resilience of an Artificial Neural NetworkDFT 2020 - 33rd IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, Oct 2020, Frascati (on line), Italy. pp.1-4, ⟨10.1109/DFT50435.2020.9250869⟩
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QAMR: an Approximation-Based FullyReliable TMR Alternative for Area Overhead ReductionETS 2020 - 25th IEEE European Test Symposium, May 2020, Tallinn, Estonia. pp.1-6, ⟨10.1109/ETS48528.2020.9131574⟩
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Evaluating the Code Encryption Effects on Memory Fault ResilienceLATS 2020 - 21st IEEE Latin American Test Symposium, Mar 2020, Maceio, Brazil. pp.1-6, ⟨10.1109/LATS49555.2020.9093670⟩
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Testing Approximate Digital Circuits: Challenges and OpportunitiesLATS 2018 - 19th IEEE Latin American Test Symposium, Mar 2018, Sao Paulo, Brazil. pp.1-6, ⟨10.1109/LATW.2018.8349681⟩
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On the Comparison of Different ATPG approaches for Approximate Integrated CircuitsDDECS 2018 - 1st International Symposium on Design and Diagnostics of Electronic Circuits and Systems, Apr 2018, Budapest, Hungary. pp.85-90, ⟨10.1109/DDECS.2018.00022⟩
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lirmm-03032856v1
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Special session: How approximate computing impacts verification, test and reliability36th VLSI Test Symposium (VTS), Apr 2018, San Francisco, CA, United States. ⟨10.1109/VTS.2018.8368628⟩
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Synthesis of Finite State Machines on Memristor CrossbarsDDECS 2018 - 1st International Symposium on Design and Diagnostics of Electronic Circuits and Systems, Apr 2018, Budapest, Hungary. pp.107-112, ⟨10.1109/DDECS.2018.000-3⟩
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Predicting the Impact of Functional Approximation: from Component- to Application-Level24th International Symposium on On-Line Testing And Robust System Design (IOLTS), Jul 2018, Platja d'Aro, Spain. pp.61-64, ⟨10.1109/IOLTS.2018.8474072⟩
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Investigation of Mean-Error Metrics for Testing Approximate Integrated CircuitsDFT 2018 - 31st IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, Oct 2018, Chicago, United States. pp.1-6, ⟨10.1109/DFT.2018.8602939⟩
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Memristive devices: Technology, Design Automation and Computing FrontiersDTIS 2017 - 12th International Conference on Design Technology of Integrated Systems In Nanoscale Era, Apr 2017, Palma de Mallorca, Spain. ⟨10.1109/DTIS.2017.7930178⟩
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Formal Design Space Exploration for memristor-based crossbar architectureDDECS 2017 - 20th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, Apr 2017, Dresden, Germany. pp.145-150, ⟨10.1109/DDECS.2017.7934557⟩
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Towards approximation during test of Integrated CircuitsDDECS 2017 - 20th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, Apr 2017, Dresden, Germany. pp.28-33, ⟨10.1109/DDECS.2017.7934574⟩
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Towards digital circuit approximation by exploiting fault simulationEWDTS: East-West Design & Test Symposium, Sep 2017, Novi Sad, Serbia. ⟨10.1109/EWDTS.2017.8110108⟩
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Can we Approximate the Test of Integrated Circuits?WAPCO: Workshop On Approximate Computing, Jan 2017, Stockholm, Sweden
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XbarGen: A memristor based boolean logic synthesis toolIFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), Sep 2016, Tallinn, Estonia. ⟨10.1109/VLSI-SoC.2016.7753567⟩
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Automatic Approximation of Computer Systems Through Multi-objective OptimizationDesign and Applications of Emerging Computer Systems, Springer Nature Switzerland, pp.383-420, 2024, ⟨10.1007/978-3-031-42478-6_15⟩
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Design, Verification, Test, and In-Field Implications of Approximate Digital Integrated CircuitsApproximate Computing Techniques, Springer International Publishing, pp.349-385, 2022, ⟨10.1007/978-3-030-94705-7_12⟩
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Test and Reliability of Approximate HardwareApproximate Computing, Springer International Publishing, pp.233-266, 2022, ⟨10.1007/978-3-030-98347-5_10⟩
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TEST TECHNIQUES FOR APPROXIMATE DIGITAL CIRCUITSMicro and nanotechnologies/Microelectronics. Université Montpellier, 2019. English. ⟨NNT : 2019MONTS060⟩
Theses
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