Mikaël Briday

Documents

Research domains

Embedded Systems

Publications

	SCHEMATIC: Compile-time checkpoint placement and memory allocation for intermittent systems Hugo Reymond , Jean-Luc Béchennec , Mikaël Briday , Sébastien Faucou , Isabelle Puaut IEEE/ACM International Symposium on Code Generation and Optimization (CGO'24), Mar 2024, Edinburgh, United Kingdom. pp.258-269, ⟨10.1109/CGO57630.2024.10444789⟩ Conference papers hal-04345348v2
	EarlyBird: Energy belongs to those who wake up early Hugo Reymond , Jean-Luc Béchennec , Mikaël Briday , Sébastien Faucou , Isabelle Puaut RTCSA 2024 - 30th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, Aug 2024, Sokcho, South Korea. pp.1-10, ⟨10.1109/RTCSA62462.2024.00011⟩ Conference papers hal-04663862v1
	MORTEM: a new runtime for intermittent computing Antoine Bernabeu , Jean-Luc Béchennec , Mikaël Briday , Sébastien Faucou , Olivier H. Roux Conférence francophone d'informatique en Parallélisme, Architecture et Système (COMPAS), Jul 2023, Annecy, France Conference papers hal-04354069v1
	Securing a RISC-V architecture: A dynamic approach Sébastien Pillement , Maria Mendez Real , Juliette Pottier , Thomas Nieddu , Bertrand Le Gal 2023 Design, Automation and Test in Europe Conference (DATE 2023), Apr 2023, Antwerp, Belgium. ⟨10.23919/DATE56975.2023.10136972⟩ Conference papers hal-03906564v1
	Expressiveness and analysis of Delayable Timed Petri Net Rémi Parrot , Hanifa Boucheneb , Mikaël Briday , Olivier H Roux 16th IFAC Workshop on Discrete Event Systems WODES 2022, IFAC, Sep 2022, Prague, Czech Republic. pp.284-290, ⟨10.1016/j.ifacol.2022.10.355⟩ Conference papers hal-03952599v1
	Energy Efficiency is Not Enough: Towards a Batteryless Internet of Sounds Vincent Lostanlen , Antoine Bernabeu , Jean-Luc Béchennec , Mikaël Briday , Sébastien Faucou Proceedings of the International Workshop on the Internet of Sounds (IWIS), Audio Mostly, Sep 2021, Trento, Italy Conference papers hal-03324622v1
	Réseaux de Petri temporisés pour la conception et vérification de circuits pipelinés Rémi Parrot , Mikaël Briday , Olivier H Roux Modélisation des Systèmes Réactifs (MSR'21), Nov 2021, Paris, France Conference papers hal-03587736v1
	Synthèse de traces temporisées à coût optimal pour l'ordonnancement de systèmes embarqués intermittents Antoine Bernabeu , Jean-Luc Béchennec , Mikaël Briday , Sébastien Faucou , Olivier Henri Roux Modélisation des Systèmes Réactifs (MSR'21), Nov 2021, Paris, France Conference papers hal-03449539v1
	Pipeline Optimization using a Cost Extension of Timed Petri Nets Rémi Parrot , Mikaël Briday , Olivier H Roux 2021 IEEE 28th Symposium on Computer Arithmetic (ARITH), Jun 2021, Lyngby, Denmark. pp.37-44, ⟨10.1109/ARITH51176.2021.00018⟩ Conference papers hal-03464317v1
	Timed Petri Nets with Reset for Pipelined Synchronous Circuit Design Rémi Parrot , Mikaël Briday , Olivier H Roux 42nd International Conference on Application and Theory of Petri Nets and Concurrency, Jun 2021, Paris, France. pp.55-75, ⟨10.1007/978-3-030-76983-3_4⟩ Conference papers hal-03266806v1
	Hardware Runtime Verification of a RTOS Kernel: Evaluation Using Fault Injection Dimitry Solet , Mikaël Briday , Jean-Luc Béchennec , Sébastien Faucou , Sébastien Pillement 14th European Dependable Computing Conference (EDCC), Sep 2018, Iasi, Romania. ⟨10.1109/edcc.2018.00016⟩ Conference papers hal-01874233v1
	HW-based Architecture for Runtime Verification of Embedded Software on SOPC systems Dimitry Solet , Jean-Luc Béchennec , Mikaël Briday , Sébastien Faucou , Sébastien Pillement 2018 NASA/ESA Conference on Adaptive Hardware and Systems (AHS), Aug 2018, Edinburgh, United Kingdom. ⟨10.1109/AHS.2018.8541459⟩ Conference papers hal-01804096v1
	WCET Analysis by Model Checking for a Processor with Dynamic Branch Prediction Armel Mangean , Jean-Luc Béchennec , Mikaël Briday , Sébastien Faucou Verification and Evaluation of Computer and Communication Systems. VECoS 2017, Aug 2017, Montréal, Canada. pp.64--78, ⟨10.1007/978-3-319-66176-6_5⟩ Conference papers hal-01713094v1
	Hardware runtime verification of embedded software in SoPC Dimitry Solet , Jean-Luc Béchennec , Mikaël Briday , Sébastien Faucou , Sébastien Pillement 2016 11th IEEE Symposium on Industrial Embedded Systems (SIES), May 2016, Cracovie, Poland. SIES 2016 paper 16, ⟨10.1109/sies.2016.7509425⟩ Conference papers hal-01307973v1
	BEST: a Binary Executable Slicing Tool Armel Mangean , Jean-Luc Béchennec , Mikaël Briday , Sébastien Faucou 16th International Workshop on Worst-Case Execution Time Analysis (WCET 2016), Jul 2016, Toulouse, France. pp.7:1--7:10, ⟨10.4230/OASIcs.WCET.2016.7⟩ Conference papers hal-01713140v1
	Reactive Embedded Device Driver Synthesis using Logical Timed Models Julien Tanguy , Jean-Luc Béchennec , Mikaël Briday , Olivier-H Roux 4th International Conference on Simulation and Modeling Methodologies, Technologies and Applications (SIMULTECH 2014), Aug 2014, Vienne, Austria. ⟨10.5220/0005040101630169⟩ Conference papers hal-01142411v1
	A compiled Cycle Accurate Simulation for Hardware Architecture Adrien Bullich , Mikaël Briday , Jean-Luc Béchennec , Yvon Trinquet 5th International Conference on Advances in System Simulation - SIMUL 2013, Oct 2013, VENICE, Italy. pp.213-225 Conference papers hal-00943401v1
	Device driver synthesis for embedded systems Julien Tanguy , Jean-Luc Béchennec , Mikaël Briday , Sébastien Dubé , Olivier Henri Roux 18th IEEE International Conference on Emerging Technologies & Factory Automation, Sep 2013, Cagliari, Italy Conference papers hal-00942323v1
	An Architecture Description Language for Embedded Hardware Platforms Guillaume Savaton , Jean-Luc Béchennec , Mikaël Briday , Rola Kassem Workshop on OCL and Textual Modelling, TOOLS 2011, 2011, Zürich, Anguilla Conference papers hal-01179758v1
	Extending HARMLESS Architecture Description Language for Embedded Real-Time Systems Validation Jean-Luc Béchennec , Mikaël Briday , Valère Alibert IEEE International Symposium on Industrial Embedded Systems, Jun 2011, Västerås, Sweden. pp.223 Conference papers hal-00941186v1
	Instruction set simulator generation using Harmless, a new hardware architecture description language Rola Kassem , Mikaël Briday , Jean-Luc Béchennec , Yvon Trinquet , Guillaume Savaton 2nd Int. Conf. on Simulation Tools and Techniques for Communications, Networks ans Systems (Simutools 2009), ICST / ACM SIGSIM, Mar 2009, Roma, Italy Conference papers inria-00538502v1
	Cycle accurate simulator generator using Harmless Rola Kassem , Mikaël Briday , Jean-Luc Béchennec , Yvon Trinquet , Guillaume Savaton Int. Middle Eastern Multiconference on Simulation and Modelling (MESM'09), EUROSIS, Sep 2009, Beirut, Lebanon Conference papers inria-00538508v1
	Simulator Generation Using an Automaton Based Pipeline Model for Timing Analysis. Rola Kassem , Mikaël Briday , Jean-Luc Béchennec , Yvon Trinquet , Guillaume Savaton International Multiconference on Computer Science and Information Technology (IMCSIT), International Workshop on Real Time Software (RTS'08)., Oct 2008, Wisla, Poland. pp.657-664 Conference papers hal-00486839v1
	Trampoline - an open source implementation of the osek/vdx rtos specification Jean-Luc Béchennec , Mikaël Briday , Sébastien Faucou , Yvon Trinquet 11th Int. Conf. on Emerging Technologies and Factory Automation (ETFA'06), IEEE, Sep 2006, Prague, Czech Republic Conference papers inria-00538492v1

	Design and verification of pipelined circuits with Timed Petri Nets Rémi Parrot , Mikaël Briday , Olivier Roux Discrete Event Dynamic Systems, 2023, 33, ⟨10.1007/s10626-022-00371-7⟩ Journal articles hal-03952519v1
	Cost-optimal timed trace synthesis for scheduling of intermittent embedded systems Antoine Bernabeu , Mikaël Briday , Sébastien Faucou , Jean-Luc Béchennec , Olivier H. Roux Discrete Event Dynamic Systems, 2023, 33, ⟨10.1007/s10626-022-00372-6⟩ Journal articles hal-03952467v1
	Harmless, a Hardware Architecture Description Language Dedicated to Real-Time Embedded System Simulation Rola Kassem , Mikaël Briday , Jean-Luc Béchennec , Guillaume Savaton , Yvon Trinquet Journal of Systems Architecture, 2012, 58 (8), pp.318-337. ⟨10.1016/j.sysarc.2012.05.001⟩ Journal articles hal-00768517v1
	Retis: a real-time simulation platform Mikaël Briday , Jean-Luc Béchennec , Yvon Trinquet Journal Européen des Systèmes Automatisés (JESA), 2006, 40 (8), pp.819-846 Journal articles hal-00537625v1

	Memory Allocation in Intermittent Computing Hugo Reymond , Isabelle Puaut , Erven Rohou , Sébastien Faucou , Jean-Luc Béchennec COMPAS'2022, Jul 2022, Amiens, France Conference poster hal-04385204v1
	Support d'exécution pour le calcul intermittent Jean-Luc Béchennec , Antoine Bernabeu , Mikaël Briday , Sébastien Faucou COMPAS 2021, Jul 2021, Lyon, France. Conference poster hal-03446983v1
	Implémentation matérielle d’un dispositif de vérification en ligne sur un SoPC Dimitry Solet , Sébastien Pillement , Mikaël Briday , Jean-Luc Béchennec , Sébastien Faucou Colloque National GDR SoC-SiP, Jun 2016, Nantes, France. , paper ID#68, 2016 Conference poster hal-01324796v1

Mikaël Briday

Research domains

Publications

SCHEMATIC: Compile-time checkpoint placement and memory allocation for intermittent systems

EarlyBird: Energy belongs to those who wake up early

MORTEM: a new runtime for intermittent computing

Securing a RISC-V architecture: A dynamic approach

Expressiveness and analysis of Delayable Timed Petri Net

Energy Efficiency is Not Enough: Towards a Batteryless Internet of Sounds

Réseaux de Petri temporisés pour la conception et vérification de circuits pipelinés

Synthèse de traces temporisées à coût optimal pour l'ordonnancement de systèmes embarqués intermittents

Pipeline Optimization using a Cost Extension of Timed Petri Nets

Timed Petri Nets with Reset for Pipelined Synchronous Circuit Design

Hardware Runtime Verification of a RTOS Kernel: Evaluation Using Fault Injection

HW-based Architecture for Runtime Verification of Embedded Software on SOPC systems

WCET Analysis by Model Checking for a Processor with Dynamic Branch Prediction

Hardware runtime verification of embedded software in SoPC

BEST: a Binary Executable Slicing Tool

Reactive Embedded Device Driver Synthesis using Logical Timed Models

A compiled Cycle Accurate Simulation for Hardware Architecture

Device driver synthesis for embedded systems

An Architecture Description Language for Embedded Hardware Platforms

Extending HARMLESS Architecture Description Language for Embedded Real-Time Systems Validation

Instruction set simulator generation using Harmless, a new hardware architecture description language

Cycle accurate simulator generator using Harmless

Simulator Generation Using an Automaton Based Pipeline Model for Timing Analysis.

Trampoline - an open source implementation of the osek/vdx rtos specification

Design and verification of pipelined circuits with Timed Petri Nets

Cost-optimal timed trace synthesis for scheduling of intermittent embedded systems

Harmless, a Hardware Architecture Description Language Dedicated to Real-Time Embedded System Simulation

Retis: a real-time simulation platform

Memory Allocation in Intermittent Computing

Support d'exécution pour le calcul intermittent

Implémentation matérielle d’un dispositif de vérification en ligne sur un SoPC