Mikaël Briday
Domaines de recherche
Publications
Publications
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Circadia: Checkpointing for Intermittent Computing in AI Driven ApplicationsACACES 2025 - 21st Internationnal Summer School on Advanced Computer Architecture and Compilation for High-performance Embedded Systems, Jul 2025, Salerno, Italy. 2025 |
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Memory Allocation in Intermittent ComputingCOMPAS'2022, Jul 2022, Amiens, France |
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Support d'exécution pour le calcul intermittentCOMPAS 2021, Jul 2021, Lyon, France. |
Implémentation matérielle d’un dispositif de vérification en ligne sur un SoPCColloque National GDR SoC-SiP, Jun 2016, Nantes, France. , paper ID#68, 2016 |
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Circadia: Checkpointing for Intermittent Computing in AI Driven ApplicationsDSD 2025 - 28th Euromicro Conference on Digital System Design, Sep 2025, Salerno, Italy. pp.1-10, ⟨10.1109/DSD67783.2025.00091⟩ |
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EarlyBird: Energy belongs to those who wake up earlyRTCSA 2024 - 30th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, Aug 2024, Sokcho, South Korea. pp.1-10, ⟨10.1109/RTCSA62462.2024.00011⟩ |
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SCHEMATIC: Compile-time checkpoint placement and memory allocation for intermittent systemsIEEE/ACM International Symposium on Code Generation and Optimization (CGO'24), Mar 2024, Edinburgh, United Kingdom. pp.258-269, ⟨10.1109/CGO57630.2024.10444789⟩ |
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Securing a RISC-V architecture: A dynamic approach2023 Design, Automation and Test in Europe Conference (DATE 2023), Apr 2023, Antwerp, Belgium. ⟨10.23919/DATE56975.2023.10136972⟩ |
MORTEM: a new runtime for intermittent computingConférence francophone d'informatique en Parallélisme, Architecture et Système (COMPAS), Jul 2023, Annecy, France |
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Expressiveness and analysis of Delayable Timed Petri Net16th IFAC Workshop on Discrete Event Systems WODES 2022, IFAC, Sep 2022, Prague, Czech Republic. pp.284-290, ⟨10.1016/j.ifacol.2022.10.355⟩ |
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Pipeline Optimization using a Cost Extension of Timed Petri Nets2021 IEEE 28th Symposium on Computer Arithmetic (ARITH), Jun 2021, Lyngby, Denmark. pp.37-44, ⟨10.1109/ARITH51176.2021.00018⟩ |
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Timed Petri Nets with Reset for Pipelined Synchronous Circuit Design42nd International Conference on Application and Theory of Petri Nets and Concurrency, Jun 2021, Paris, France. pp.55-75, ⟨10.1007/978-3-030-76983-3_4⟩ |
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Synthèse de traces temporisées à coût optimal pour l'ordonnancement de systèmes embarqués intermittentsModélisation des Systèmes Réactifs (MSR'21), Nov 2021, Paris, France |
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Energy Efficiency is Not Enough: Towards a Batteryless Internet of SoundsProceedings of the International Workshop on the Internet of Sounds (IWIS), Audio Mostly, Sep 2021, Trento, Italy |
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Réseaux de Petri temporisés pour la conception et vérification de circuits pipelinésModélisation des Systèmes Réactifs (MSR'21), Nov 2021, Paris, France |
Hardware Runtime Verification of a RTOS Kernel: Evaluation Using Fault Injection14th European Dependable Computing Conference (EDCC), Sep 2018, Iasi, Romania. ⟨10.1109/edcc.2018.00016⟩ |
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HW-based Architecture for Runtime Verification of Embedded Software on SOPC systems2018 NASA/ESA Conference on Adaptive Hardware and Systems (AHS), Aug 2018, Edinburgh, United Kingdom. ⟨10.1109/AHS.2018.8541459⟩ |
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WCET Analysis by Model Checking for a Processor with Dynamic Branch PredictionVerification and Evaluation of Computer and Communication Systems. VECoS 2017, Aug 2017, Montréal, Canada. pp.64--78, ⟨10.1007/978-3-319-66176-6_5⟩ |
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BEST: a Binary Executable Slicing Tool16th International Workshop on Worst-Case Execution Time Analysis (WCET 2016), Jul 2016, Toulouse, France. pp.7:1--7:10, ⟨10.4230/OASIcs.WCET.2016.7⟩ |
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Hardware runtime verification of embedded software in SoPC2016 11th IEEE Symposium on Industrial Embedded Systems (SIES), May 2016, Cracovie, Poland. SIES 2016 paper 16, ⟨10.1109/sies.2016.7509425⟩ |
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Reactive Embedded Device Driver Synthesis using Logical Timed Models4th International Conference on Simulation and Modeling Methodologies, Technologies and Applications (SIMULTECH 2014), Aug 2014, Vienne, Austria. ⟨10.5220/0005040101630169⟩ |
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Device driver synthesis for embedded systems18th IEEE International Conference on Emerging Technologies & Factory Automation, Sep 2013, Cagliari, Italy |
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A compiled Cycle Accurate Simulation for Hardware Architecture5th International Conference on Advances in System Simulation - SIMUL 2013, Oct 2013, VENICE, Italy. pp.213-225 |
An Architecture Description Language for Embedded Hardware PlatformsWorkshop on OCL and Textual Modelling, TOOLS 2011, 2011, Zürich, Anguilla |
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Extending HARMLESS Architecture Description Language for Embedded Real-Time Systems ValidationIEEE International Symposium on Industrial Embedded Systems, Jun 2011, Västerås, Sweden. pp.223 |
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Simulator Generation Using an Automaton Based Pipeline Model for Timing Analysis.International Multiconference on Computer Science and Information Technology (IMCSIT), International Workshop on Real Time Software (RTS'08)., Oct 2008, Wisla, Poland. pp.657-664 |
Cycle accurate simulator generator using HarmlessInt. Middle Eastern Multiconference on Simulation and Modelling (MESM'09), EUROSIS, Sep 2009, Beirut, Lebanon |
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Instruction set simulator generation using Harmless, a new hardware architecture description language2nd Int. Conf. on Simulation Tools and Techniques for Communications, Networks ans Systems (Simutools 2009), ICST / ACM SIGSIM, Mar 2009, Roma, Italy |
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Trampoline - an open source implementation of the osek/vdx rtos specification11th Int. Conf. on Emerging Technologies and Factory Automation (ETFA'06), IEEE, Sep 2006, Prague, Czech Republic |
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A Study in Specification and Hardware Runtime Verification of Critical Embedded SoftwareIEEE Transactions on Dependable and Secure Computing, 2024, pp.1-12. ⟨10.1109/tdsc.2024.3484015⟩ |
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Cost-optimal timed trace synthesis for scheduling of intermittent embedded systemsDiscrete Event Dynamic Systems, 2023, 33, ⟨10.1007/s10626-022-00372-6⟩ |
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Design and verification of pipelined circuits with Timed Petri NetsDiscrete Event Dynamic Systems, 2023, 33, ⟨10.1007/s10626-022-00371-7⟩ |
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Harmless, a Hardware Architecture Description Language Dedicated to Real-Time Embedded System SimulationJournal of Systems Architecture, 2012, 58 (8), pp.318-337. ⟨10.1016/j.sysarc.2012.05.001⟩ |
Retis: a real-time simulation platformJournal Européen des Systèmes Automatisés, 2006, 40 (8), pp.819-846 |