
Quentin Meunier
39
Documents
Publications
Publications
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VerifMSI: Practical Verification of Hardware and Software Masking Schemes Implementations20th International Conference on Security and Cryptography, Jul 2023, Rome, Italy. pp.520-527, ⟨10.5220/0012138600003555⟩
Communication dans un congrès
hal-04192584
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Implementations Impact on Iterative Image Processing for Embedded GPUEuropean Signal Processing Conference (EUSIPCO), Aug 2021, Dublin, Ireland
Communication dans un congrès
hal-03330779
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PROSECCO: Formally-proven secure compiled codeC&ESAR 2021 : 28th Computer Electronics Security Application Rendezvous, Nov 2021, Rennes, France. pp.13-25
Communication dans un congrès
cea-03605070
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A 220GOPS 96-Core Processor with 6 Chiplets 3D-Stacked on an Active Interposer Offering 0.6ns/mm Latency, 3Tb/s/mm 2 Inter-Chiplet Interconnects and 156mW/mm 2 @ 82%-Peak-Efficiency DC-DC Converters2020 IEEE International Solid- State Circuits Conference - (ISSCC), Feb 2020, San Francisco, United States. pp.46-48, ⟨10.1109/ISSCC19947.2020.9062927⟩
Communication dans un congrès
hal-02985945
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SELA: a Symbolic Expression Leakage AnalyzerInternational Workshop on Security Proofs for Embedded Systems, Sep 2020, Visioconference, France
Communication dans un congrès
hal-02983213
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Real-time embedded video denoiser prototype9th International Symposium - Optronics in Defense and Security (Optro), Jan 2020, Paris, France
Communication dans un congrès
hal-02469914
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Débruitage temps réel embarqué pour vidéos fortement bruitéesCOMPAS 2019, Jun 2019, Anglet, France
Communication dans un congrès
hal-02268005
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Fault attack vulnerability assessment of binary codeCryptography and Security in Computing Systems (CS2’19), Jan 2019, Valencia, Spain. pp.13-18, ⟨10.1145/3304080.3304083⟩
Communication dans un congrès
hal-02163152
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FastCPA: Efficient Correlation Power Analysis Computation with a Large Number of Traces6th Cryptography and Security in Computing Systems (CS2’19), Jan 2019, Valence, Spain. ⟨10.1145/3304080.3304082⟩
Communication dans un congrès
hal-02172200
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A New Real-Time Embedded Video Denoising AlgorithmDASIP 2019 - The Conference on Design and Architectures for Signal and Image Processing, Oct 2019, Montréal, Canada
Communication dans un congrès
hal-02343597
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A 29 Gops/Watt 3D-Ready 16-Core Computing Fabric with Scalable Cache Coherent Architecture Using Distributed L2 and Adaptive L3 CachesESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC), Sep 2018, Dresden, Germany. pp.318-321, ⟨10.1109/ESSCIRC.2018.8494275⟩
Communication dans un congrès
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Energy and Execution Time Comparison of Optical Flow Algorithms on SIMD and GPU ArchitecturesConference on Design and Architectures for Signal and Image Processing (Dasip 2018), Oct 2018, Porto, Portugal
Communication dans un congrès
hal-01925886
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A new Direct Connected Component Labeling and Analysis Algorithms for GPUs2018 Conference on Design and Architectures for Signal and Image Processing (DASIP), Oct 2018, Porto, Portugal. ⟨10.1109/dasip.2018.8596835⟩
Communication dans un congrès
hal-01923784
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Comparaison de la consommation énergétique et du temps d'exécution d'un algorithme de traitement d'images optimisé sur des architectures SIMD et GPUConférence d’informatique en Parallélisme, Architecture et Système (COMPAS 2018), Jul 2018, Toulouse, France
Communication dans un congrès
hal-01835219
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Modeling a Cache Coherence Protocol with the Guarded Action LanguageWorkshop on Models for Formal Analysis of Real Systems, Apr 2018, Thessaloniki, Greece. ⟨10.4204/EPTCS.268.3⟩
Communication dans un congrès
hal-02172237
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Decoupling Translation Lookaside Buffer Coherence from Cache CoherenceIEEE Computer Society Annual Symposium on VLSI (ISVLSI 2017), Jul 2017, Bochum, Germany. pp.92 - 97, ⟨10.1109/ISVLSI.2017.25⟩
Communication dans un congrès
hal-01585880
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Symbolic Approach for Side-Channel Resistance Analysis of Masked Assembly CodesSecurity Proofs for Embedded Systems, Sep 2017, Taipei, China
Communication dans un congrès
hal-01612463
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Exploiting Large Memory using 32-bit Energy-Efficient Manycore ArchitecturesMCSoC: Many-core Systems-on-Chip, Sep 2016, Lyon, France. pp.61-68, ⟨10.1109/MCSoC.2016.44⟩
Communication dans un congrès
hal-01362760
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Executing secured virtual machines within a manycore architectureIEEE Nordic Circuits and Systems Conference (NORCAS), Oct 2015, Oslo, Norway. ⟨10.1109/NORCHIP.2015.7364380⟩
Communication dans un congrès
hal-01363066
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RWT: Suppressing Write-Through Cost When Coherence is Not Needed2015 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Jul 2015, Montpellier, France. pp.434-439, ⟨10.1109/ISVLSI.2015.35⟩
Communication dans un congrès
hal-01362872
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Mécanisme de synchronisation scalable à plusieurs lecteurs et un écrivainConférence en Parallélisme, Architecture et Systèmes, ComPAS 2014, Apr 2014, Neuchâtel, Suisse
Communication dans un congrès
hal-01219760
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Evaluation de la précision en virgule fixe dans le cas des structures conditionnelles14th Symposium en Architecture (SympA'11), May 2011, Saint Malo, France
Communication dans un congrès
inria-00617720
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Fixed-point Accuracy Evaluation in the Context of Conditional Structures19th European Signal Processing Conference (EUSIPCO), Sep 2011, Barcelona, Spain
Communication dans un congrès
hal-00747610
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LightTM : Une Mémoire Transactionnelle conçue pour les MPSoCsSymposium en Architecture de machines (SympA'13), Sep 2009, Toulouse, France. pp.1-12
Communication dans un congrès
hal-00419309
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Design and Use of Transactional Memory in MPSoCs9th International Seminar on Application Specific Multiprocessor SoC, Aug 2009, Savanah, Georgia, United States
Communication dans un congrès
hal-00560474
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Lightweight Transactional Memory Systems for Large Scale Shared Memory MPSoCsNEWCAS – TAISA'09 Conference, Jun 2009, Toulouse, France. pp.432 - 435
Communication dans un congrès
hal-00419304
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Comparaison de la consommation énergétique et du temps d'exécution d'un algorithme de traitement d'images optimisé sur des architectures SIMD et GPUGdR SOC2, Jun 2018, Paris, France
Poster de conférence
hal-01835240
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Étude de deux solutions pour le support matériel de la programmation parallèle dans les multiprocesseurs intégrés : vol de travail et mémoires transactionnellesAutre [cs.OH]. Institut National Polytechnique de Grenoble - INPG, 2010. Français. ⟨NNT : ⟩
Thèse
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