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Sophie Dupuis
Maîtresse de Conférences,
LIRMM (Université de Montpellier/CNRS) Département Microélectronique,
IUT de Montpellier Département GEII
8
Documents
Affiliations actuelles
- 1100642
Identifiants chercheurs
- sophie-dupuis
- 0000-0002-4876-2982
- Google Scholar : https://scholar.google.fr/citations?user=BIC4uX8AAAAJ
Présentation
Je suis maîtresse de Conférences au LIRMM (Montpellier, France) depuis 2011.
J'ai obtenu un DEA en Architecture des Systèmes Intégrés et Microélectronique puis une thèse de doctorat en microélectronique (intitulée Optimisation automatique des chemins de données arithmétiques par l’utilisation des systèmes de numérations redondants) à l'Université Pierre et Marie Curie (Paris, France) en 2004 et 2009 respectivement.
Mes intérêts de recherche actuels incluent plusieurs facettes de la conception de circuits numériques, en mettant l'accent sur la confiance matérielle.
Je suis responsable des études 2ème et 3ème année du BUT GEII, en formation initiale et enseigne principalement l'électronique numérique et la programmation/algorithmique.
I have been aa associate professor at LIRMM (Montpellier, France) since 2011.
I obtained a Master in Integrated Systems Architecture and Microelectronics, and then a PhD in microelectronics (entitled: Automatic optimization of arithmetic data paths through the use of redundant arithmetic) at Pierre and Marie Curie University (Paris, France) in 2004 and 2009 respectively.
My current research interests include several facets of digital circuit design, with an emphasis on hardware trust.
I am responsible for 2nd and 3rd year studies at BUT GEII, in initial training and mainly teach digital electronics and programming/algorithmic.
Publications
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- 8
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Duplication-based Concurrent Detection of Hardware Trojans in Integrated CircuitsTRUDEVICE, Nov 2016, Barcelona, Spain
Communication dans un congrès
lirmm-01385551v1
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Hardware Trust through Layout Filling: a Hardware Trojan Prevention TechniqueISVLSI: International Symposium on Very Large Scale Integration, Jul 2016, Pittsburgh, United States. pp.254-259, ⟨10.1109/ISVLSI.2016.22⟩
Communication dans un congrès
lirmm-01346529v1
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Using Outliers to Detect Stealthy Hardware Trojan Triggering?IVSW: International Verification and Security Workshop, Jul 2016, Sant Feliu de Guixols, France
Communication dans un congrès
lirmm-01347119v1
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On the limitations of logic testing for detecting Hardware Trojans HorsesDTIS: Design and Technology of Integrated Systems in Nanoscale Era, Apr 2015, Naples, Italy. ⟨10.1109/DTIS.2015.7127362⟩
Communication dans un congrès
lirmm-01257837v1
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New Testing Procedure for Finding Insertion Sites of Stealthy Hardware TrojansDATE 2015 - 18th Design, Automation and Test in Europe Conference and Exhibition, Mar 2015, Grenoble, France. pp.776-781, ⟨10.7873/DATE.2015.1102⟩
Communication dans un congrès
lirmm-01141619v1
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Hardware Trojan Prevention using Layout-Level Design ApproachECCTD: European Conference on Circuit Theory and Design, Aug 2015, Trondheim, Norway. ⟨10.1109/ECCTD.2015.7300093⟩
Communication dans un congrès
lirmm-01234072v1
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A Novel Hardware Logic Encryption Technique for thwarting Illegal Overproduction and Hardware TrojansIOLTS: International On-Line Testing Symposium, Jul 2014, Platja d'Aro, Girona, Spain. pp.49-54, ⟨10.1109/IOLTS.2014.6873671⟩
Communication dans un congrès
lirmm-01025275v1
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Detection and Prevention of Hardware Trojan through Logic TestingTRUDEVICE, Nov 2016, Barcelona, Spain. , 4th Workshop on Trustworthy Manufacturing and Utilization of Secure Devices, Manufacturing test of secure devices / Reverse engineering countermeasures / Other topics, pp.#33, 2016, Posters IV
Poster de conférence
lirmm-01430007v1
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