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Vincent Beroulle
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Présentation
Vincent Beroulle received an Engineer Degree from the National Polytechnical Institute of Grenoble (INPG) in 1996, and a Master's Degree and a Ph.D. in Microelectronics from the University of Montpellier II, respectively in 1999 and 2002. He is currently a Professor at the Grenoble Institute of Technology. He is head of the LCIS laboratory. His main interest concerns the security and safety of complex integrated circuits and systems. In particular, his work deals with fault modeling and fault injection with emulation platforms with a specific focus on IoT and RFID technologies.
Publications
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Cross-layer analysis of clock glitch fault injection while fetching variable-length instructionsJournal of Cryptographic Engineering, 2024, ⟨10.1007/s13389-024-00352-6⟩
Article dans une revue
hal-04557324v1
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Cross-Layer Inference Methodology for Microarchitecture-aware Fault ModelsMicroelectronics Reliability, 2022, 139, ⟨10.1016/j.microrel.2022.114841⟩
Article dans une revue
hal-03848691v1
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Microarchitectural Insights into Unexplained Behaviors under Clock Glitch Fault Injection22nd Smart Card Research and Advanced Application Conference (CARDIS 2023), Nov 2023, Amsterdam, Netherlands. pp.1-20
Communication dans un congrès
hal-04273995v1
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Microarchitecture-aware Fault Models: Experimental Evidence and Cross-Layer Inference MethodologyInternational Conference on Design & Technology of Integrated System in Nanoscale Era (DTIS 2021), Jun 2021, Apulia (virtual), Italy
Communication dans un congrès
hal-03272932v1
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