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Vincent Beroulle

5
Documents

Présentation

Vincent Beroulle received an Engineer Degree from the National Polytechnical Institute of Grenoble (INPG) in 1996, and a Master's Degree and a Ph.D. in Microelectronics from the University of Montpellier II, respectively in 1999 and 2002. He is currently a Professor at the Grenoble Institute of Technology. He is head of the LCIS laboratory. His main interest concerns the security and safety of complex integrated circuits and systems. In particular, his work deals with fault modeling and fault injection with emulation platforms with a specific focus on IoT and RFID technologies.

Publications

david-hely
"paolo-maistri"
"giorgio-di-natale"
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Modeling Thermal Effects For Biasing PUFs

Aghiles Douadi , Ioana Vatajelu , Paolo Maistri , David Hély , Vincent Beroulle
29th IEEE European Test Symposium (ETS 2024), May 2024, The Hague, Netherlands
Communication dans un congrès hal-04532564v1
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The case of using CMOS FD-SOI rather than CMOS bulk to harden ICs against laser attacks

Jean-Max Dutertre , Vincent Beroulle , Philippe Candelier , Louis-Barthelemy Faber , Marie-Lise Flottes
IOLTS: International On-Line Testing Symposium, Jul 2018, Platja d’Aro, Spain. pp.214-219, ⟨10.1109/IOLTS.2018.8474230⟩
Communication dans un congrès emse-01856000v1
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Laser fault injection at the CMOS 28 nm technology node: an analysis of the fault model

Jean-Max Dutertre , Vincent Beroulle , Philippe Candelier , Stephan de Castro , Louis-Barthelemy Faber
FDTC: Fault Diagnosis and Tolerance in Cryptography, Sep 2018, Amsterdam, Netherlands. pp.1-6, ⟨10.1109/FDTC.2018.00009⟩
Communication dans un congrès emse-01856008v1
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Laser-Induced Fault Effects in Security-Dedicated Circuits

Vincent Beroulle , Philippe Candelier , Stephan de Castro , Giorgio Di Natale , Jean-Max Dutertre
VLSI-SoC: Very Large Scale Integration and System-on-Chip, Oct 2014, Playa del Carmen, Mexico. pp.220-240, ⟨10.1007/978-3-319-25279-7_12⟩
Communication dans un congrès hal-01383737v1