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Vincent Beroulle

18
Documents

Présentation

Vincent Beroulle received an Engineer Degree from the National Polytechnical Institute of Grenoble (INPG) in 1996, and a Master's Degree and a Ph.D. in Microelectronics from the University of Montpellier II, respectively in 1999 and 2002. He is currently a Professor at the Grenoble Institute of Technology. He is head of the LCIS laboratory. His main interest concerns the security and safety of complex integrated circuits and systems. In particular, his work deals with fault modeling and fault injection with emulation platforms with a specific focus on IoT and RFID technologies.

Publications

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Cross-layer Approach to Assess FMEA on Critical Systems and Evaluate High-Level Model Realism

Julie Roux , Katell Morin-Allory , Vincent Beroulle , Régis Leveugle , Gilles Genévrier
29th IFIP/IEEE International Conference on very Large Scale Integration, VLSI-SoC 2021, Oct 2021, Singapour, Singapore
Communication dans un congrès hal-03353865v1

Cross Layer Fault Simulations for Analyzing the Robustness of RTL Designs in Airborne Systems

Julie Roux , Vincent Beroulle , Katell Morin-Allory , Régis Leveugle , Lilian Bossuet
23rd International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), Apr 2020, Novi Sad, Serbia. pp.1-4, ⟨10.1109/DDECS50862.2020.9095559⟩
Communication dans un congrès hal-02937868v1

High Level Fault Injection Method for Evaluating Critical System Parameter Ranges

Julie Roux , Vincent Beroulle , Katell Morin-Allory , Régis Leveugle , Lilian Bossuet
2020 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS), Nov 2020, Glasgow, United Kingdom. pp.1-4, ⟨10.1109/ICECS49266.2020.9294821⟩
Communication dans un congrès hal-03136621v1
Image document

Laser fault injection at the CMOS 28 nm technology node: an analysis of the fault model

Jean-Max Dutertre , Vincent Beroulle , Philippe Candelier , Stephan de Castro , Louis-Barthelemy Faber
FDTC: Fault Diagnosis and Tolerance in Cryptography, Sep 2018, Amsterdam, Netherlands. pp.1-6, ⟨10.1109/FDTC.2018.00009⟩
Communication dans un congrès emse-01856008v1
Image document

The case of using CMOS FD-SOI rather than CMOS bulk to harden ICs against laser attacks

Jean-Max Dutertre , Vincent Beroulle , Philippe Candelier , Louis-Barthelemy Faber , Marie-Lise Flottes
IOLTS: International On-Line Testing Symposium, Jul 2018, Platja d’Aro, Spain. pp.214-219, ⟨10.1109/IOLTS.2018.8474230⟩
Communication dans un congrès emse-01856000v1

On the development of a new countermeasure on a laser attack RTL fault model

C. Ananiadis , A. Papadimitriou , D. Hély , V. Beroulle , Paolo Maistri
Design, Automation and Test in Europe Conference (DATE'16), Mar 2016, Dresden, Germany
Communication dans un congrès hal-01414728v1

On Fault Injections for Early Security Evaluation vs. Laser-based Attacks

Régis Leveugle , A. Chahed , Paolo Maistri , A. Papadimitriou , D. Hély
1st IEEE International Verification and Security Workshop, Jul 2016, St Feliu de Guixols, Spain. pp.33-38
Communication dans un congrès hal-01444970v1

Validation of RTL laser fault injection model with respect to layout information

A. Papadimitriou , M. Tampas , D. Hély , V. Beroulle , Paolo Maistri
IEEE International Symposium on Hardware Oriented Security and Trust (HOST'15), May 2015, McLean, VA, United States. pp.78-81
Communication dans un congrès hal-01393414v1

Validation of RTL laser fault injection model with respect to layout information

Athanasios Papadimitriou , Marios Tampas , David Hély , Vincent Beroulle , Paolo Maistri
Hardware Oriented Security and Trust (HOST 2016), May 2015, Washington,, United States. ⟨10.1109/HST.2015.7140241⟩
Communication dans un congrès hal-01392792v1

Analysis of laser-induced errors: RTL fault model versus layout locality characteristics

A. Papadimitriou , D. Hély , V. Beroulle , Paolo Maistri , Régis Leveugle
Third Workshop on Trustworthy Manufacturing and Utilization of Secure Devices (TRUDEVICE'15), Mar 2015, Grenoble, France
Communication dans un congrès hal-01393406v1

FPGA emulation of laser attacks against secure deep submicron integrated circuits

P. Papavramidou , D. Hély , V. Beroulle , Paolo Maistri , Régis Leveugle
Second Workshop on Trustworthy Manufacturing and Utilization of Secure Devices (TRUDEVICE'14), May 2014, Paderborn, Germany
Communication dans un congrès hal-01132405v1

On error models for RTL security evaluations

Pierre Vanhauwaert , Paolo Maistri , Régis Leveugle , Athanasios Papadimitriou , David Hely
9th Conference on Design and Technology of Integrated Systems in Nanoscale Era (DTIS) 2014, May 2014, Santorini, Greece. pp.1-6
Communication dans un congrès hal-01010314v1
Image document

Laser-Induced Fault Effects in Security-Dedicated Circuits

Vincent Beroulle , Philippe Candelier , Stephan de Castro , Giorgio Di Natale , Jean-Max Dutertre
VLSI-SoC: Very Large Scale Integration and System-on-Chip, Oct 2014, Playa del Carmen, Mexico. pp.220-240, ⟨10.1007/978-3-319-25279-7_12⟩
Communication dans un congrès hal-01383737v1

A multiple fault injection methodology based on cone partitioning towards RTL modeling of laser attacks

Athanasios Papadimitriou , David Hely , Vincent Beroulle , Paolo Maistri , Régis Leveugle
Design, Automation and Test in Europe Conference and Exhibition (DATE), 2014, Mar 2014, Dresden, Germany. pp.1-4, ⟨10.7873/DATE2014.219⟩
Communication dans un congrès hal-00981848v1

FPGA emulation of laser attacks against secure deep submicron integrated circuits

A. Papadimitriou , D. Hély , V. Beroulle , Paolo Maistri , Régis Leveugle
7ème Colloque du GdR SoC-SiP, Jun 2013, Lyon, France
Communication dans un congrès hal-01400108v1