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Vincent Beroulle
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Documents
Présentation
Vincent Beroulle received an Engineer Degree from the National Polytechnical Institute of Grenoble (INPG) in 1996, and a Master's Degree and a Ph.D. in Microelectronics from the University of Montpellier II, respectively in 1999 and 2002. He is currently a Professor at the Grenoble Institute of Technology. He is head of the LCIS laboratory. His main interest concerns the security and safety of complex integrated circuits and systems. In particular, his work deals with fault modeling and fault injection with emulation platforms with a specific focus on IoT and RFID technologies.
Publications
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Design-for-Test Approach of an Asynchronous Network-on-Chip Architecture and its Associated Test Pattern Generation and ApplicationIET Computers & Digital Techniques, 2009, 3 (5), pp.487-500. ⟨10.1049/iet-cdt.2008.0072⟩
Article dans une revue
hal-01105280v1
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High-Speed Design-for-Test Architecture for Asynchronous NoC-based Systems-on-ChipIEEE Transactions on Computers, 2008, 10, pp.12
Article dans une revue
hal-01105282v1
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A Design-for-Test Implementation of an Asynchronous Network-on-Chip Architecture and its Associated Test Pattern Generation and ApplicationThe 2nd ACM/IEEE International Symposium on Networks-on-Chip, Apr 2008, Newcastle, United Kingdom. pp. 149-158
Communication dans un congrès
hal-00331239v1
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Implementation of a Design-for-Test Architecture for Asynchronous Networks-on-ChipThe 1st ACM/IEEE International Symposium on Networks-on-Chip (NOCS 2007), May 2007, Princeton, New Jersey, United States. pp.100
Communication dans un congrès
hal-00187291v1
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Design-for-Test of Asynchronous Networks-on-ChipIEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, Apr 2006, Prague, Czech Republic. pp. 163-167
Communication dans un congrès
hal-00218149v1
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Conception en vue de Test pour l'Architecture d'un Réseau sur Puce Asynchrone2006
Autre publication scientifique
hal-00381555v1
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