- 2
- 2
VB
Vincent Beroulle
4
Documents
Présentation
Vincent Beroulle received an Engineer Degree from the National Polytechnical Institute of Grenoble (INPG) in 1996, and a Master's Degree and a Ph.D. in Microelectronics from the University of Montpellier II, respectively in 1999 and 2002. He is currently a Professor at the Grenoble Institute of Technology. He is head of the LCIS laboratory. His main interest concerns the security and safety of complex integrated circuits and systems. In particular, his work deals with fault modeling and fault injection with emulation platforms with a specific focus on IoT and RFID technologies.
Publications
- 2
- 1
- 1
- 1
- 1
- 1
- 1
- 1
- 1
- 1
- 4
- 3
- 1
Functional Verification of RTL Designs driven by Mutation Testing metrics10th Euromicro Conference on Digital System Design Architectures, Methods and Tools, 2007. DSD 2007., Aug 2007, Lubeck, Germany. pp.222-227, ⟨10.1109/DSD.2007.4341472⟩
Communication dans un congrès
hal-00254470v1
|
|
How to Improve a set of design validation data by using mutation-based test2006 IEEE Design and Diagnostics of Electronic Circuits and systems, Apr 2006, Prague, Czech Republic. pp.75-76
Communication dans un congrès
hal-00254378v1
|
|
IP Validation using Genetic Algorithms guided by Mutation TestingConference on Design of Circuit and Integrated Systems, Nov 2006, Barcelone, Spain. pp.CD
Communication dans un congrès
hal-00254467v1
|
Amélioration des Jeux de Test pour la Validation de Conception2006
Autre publication scientifique
hal-00381553v1
|