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Vincent Beroulle
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Documents
Présentation
Vincent Beroulle received an Engineer Degree from the National Polytechnical Institute of Grenoble (INPG) in 1996, and a Master's Degree and a Ph.D. in Microelectronics from the University of Montpellier II, respectively in 1999 and 2002. He is currently a Professor at the Grenoble Institute of Technology. He is head of the LCIS laboratory. His main interest concerns the security and safety of complex integrated circuits and systems. In particular, his work deals with fault modeling and fault injection with emulation platforms with a specific focus on IoT and RFID technologies.
Publications
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Cross-layer analysis of software fault models and countermeasures against hardware fault attacks in a RISC-V processorMicroprocessors and Microsystems: Embedded Hardware Design , 2019, 71, pp.102862. ⟨10.1016/j.micpro.2019.102862⟩
Article dans une revue
hal-02426107v1
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Analyzing Software Security Against Complex Fault Models with Frama-C Value Analysis2019 Workshop on Fault Diagnosis and Tolerance in Cryptography (FDTC), Aug 2019, Atlanta, United States. pp.33-40, ⟨10.1109/FDTC.2019.00013⟩
Communication dans un congrès
hal-02426133v1
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Fault Injection on Hidden Registers in a RISC-V Rocket Processor and Software Countermeasures2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), Mar 2019, Florence, Italy. pp.252-255, ⟨10.23919/DATE.2019.8715158⟩
Communication dans un congrès
hal-02426113v1
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On the Importance of Analysing Microarchitecture for Accurate Software Fault Models2018 21st Euromicro Conference on Digital System Design (DSD), Aug 2018, Prague, France. ⟨10.1109/DSD.2018.00097⟩
Communication dans un congrès
hal-01899800v1
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