
Arnaud Virazel
35%
Libre accès
343
Documents
Affiliation actuelle
- Test and dEpendability of microelectronic integrated SysTems (LIRMM | TEST)
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Publications
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Accelerating Cell-Aware Model Generation for Sequential Cells using Graph TheoryDATE 2025 - 28th Design, Automation and Test in Europe Conference and Exhibition, Mar 2025, Lyon, France. In press
Communication dans un congrès
lirmm-04955115
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A Fast and Efficient Graph-Based methodology for Cell-Aware Model GenerationITC 2024 - IEEE International Test Conference, Nov 2024, San Diego, United States. pp.270-279, ⟨10.1109/ITC51657.2024.00047⟩
Communication dans un congrès
lirmm-04738192
v1
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Approximate Computing for Test and Test of Approximate ComputingIEEE Workshop on Top Picks in VLSI Test and Reliability, Nov 2024, San Diego, United States. pp.1-2
Communication dans un congrès
lirmm-04738424
v1
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Producing a Bidirectional ATPG Compliant Verilog-HDL Memory Model of SRAMDTTIS 2024 - IEEE International Conference on Design, Test & Technology of Integrated Systems, Oct 2024, Aix-en-Provence, France. pp.1-6, ⟨10.1109/DTTIS62212.2024.10780141⟩
Communication dans un congrès
lirmm-04738159
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Producing a Bidirectional ATPG Compliant Verilog-HDL Memory Model of SRAM Memory18e Colloque National du GDR SoC², Jun 2024, Toulouse, France
Communication dans un congrès
lirmm-04739569
v1
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Design for Advanced Test and Safety for Image and Photonic SensorsTTTC’s E. J. McCluskey Best Doctoral Thesis Award Contest at ETS’24 Semifinal, May 2024, The Hague, Netherlands
Communication dans un congrès
lirmm-04739546
v1
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A Structural Testing Approach for SRAM Address Decoders using Cell-Aware MethodologyDFT 2024 - 37th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, Oct 2024, Harwell, United Kingdom. pp.1-4, ⟨10.1109/DFT63277.2024.10753545⟩
Communication dans un congrès
lirmm-04738361
v1
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A Graph-Based Methodology for Speeding up Cell-Aware Model GenerationIOLTS 2024 - 30th IEEE International Symposium on On-Line Testing and Robust System Design, Jul 2024, Rennes, France. pp.1-6, ⟨10.1109/IOLTS60994.2024.10616062⟩
Communication dans un congrès
lirmm-04738312
v1
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A Structural Testing Approach for SRAMs using Cell-Aware MethodologySouth European Test Seminar, Mar 2024, Claviere, Italy
Communication dans un congrès
lirmm-04739520
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A Novel March Test Algorithm for Testing 8T SRAM-based IMC ArchitecturesDATE 2024 - 27th Design, Automation & Test in Europe Conference & Exhibition, Mar 2024, Valence, Spain. pp.1-6, ⟨10.23919/DATE58400.2024.10546583⟩
Communication dans un congrès
hal-04658584
v1
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Comparaison des Approches de Lockstep pour la Tolérance aux Fautes des FPGAs Utilisés en Milieu Radiatif18e Colloque National du GDR SoC², Jun 2024, Toulouse, France
Communication dans un congrès
lirmm-04739624
v1
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Method and Techniques to Speed-Up Cell-Aware Model GenerationSouth European Test Seminar, Mar 2024, Claviere, Italy
Communication dans un congrès
lirmm-04739532
v1
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Analysis of Resistive-Open Defects on a Foundry 8T SRAM-based IMC Architecture17e Colloque National du GDR SoC², Jun 2023, Lyon, France
Communication dans un congrès
lirmm-04565688
v1
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Intra-cell Resistive-Open Defect Analysis on a Foundry 8T SRAM-based IMC ArchitectureETS 2023 - 28th IEEE European Test Symposium, May 2023, Venise, Italy. pp.1-4, ⟨10.1109/ETS56758.2023.10174107⟩
Communication dans un congrès
hal-04164663
v1
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Learning-Based Characterization Models for Quality Assurance of Emerging Memory TechnologiesETS 2023 - 28th IEEE European Test Symposium, May 2023, Venezia, Italy. pp.1-2, ⟨10.1109/ETS56758.2023.10174202⟩
Communication dans un congrès
hal-04164855
v1
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On Using Cell-Aware Methodology for SRAM Bit Cell TestingETS 2023 - 28th IEEE European Test Symposium, May 2023, Venezia, Italy. pp.1-4, ⟨10.1109/ETS56758.2023.10174118⟩
Communication dans un congrès
hal-04164704
v1
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Predictor BIST: An "All-in-One" Optical Test Solution for CMOS Image SensorsITC 2023 - IEEE International Test Conference, Oct 2023, Anaheim, United States. pp.310-319, ⟨10.1109/ITC51656.2023.00048⟩
Communication dans un congrès
lirmm-04240449
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Analysis of Read Port Short Defects in an 8T SRAM-based IMC Architecture16e Colloque National du GDR SoC², Jun 2022, Strasbourg, France
Communication dans un congrès
lirmm-03990078
v1
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A Generic Fast and Low Cost BIST Solution for CMOS Image SensorsETS 2022 - 27th IEEE European Test Symposium, May 2022, Barcelona, Spain. pp.1-2, ⟨10.1109/ETS54262.2022.9810458⟩
Communication dans un congrès
lirmm-03770756
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A Lightweight, Plug-and-Play and Autonomous JTAG Authentication IP for Secure Device TestingETS 2022 - 27th IEEE European Test Symposium, May 2022, Barcelona, Spain. pp.1-4, ⟨10.1109/ETS54262.2022.9810364⟩
Communication dans un congrès
lirmm-03739783
v1
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A Comprehensive Learning-Based Flow for Cell-Aware Model GenerationITC 2022 - IEEE International Test Conference, Sep 2022, Anaheim, United States. pp.484-488, ⟨10.1109/ITC50671.2022.00057⟩
Communication dans un congrès
lirmm-03770147
v1
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Configuring a Universal BIST Solution for CMOS Image Sensors16e Colloque National du GDR SoC², Jun 2022, Strasbourg, France
Communication dans un congrès
lirmm-03988569
v1
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Effective techniques for automatically improving the transition delay fault coverage of Self-Test LibrariesETS 2022 - 27th IEEE European Test Symposium, May 2022, Barcelona, Spain. pp.1-2, ⟨10.1109/ETS54262.2022.9810392⟩
Communication dans un congrès
lirmm-03739788
v1
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On Using Cell-Aware Models for Representing SRAM Architecture16e Colloque National du GDR SoC², Jun 2022, Strasbourg, France
Communication dans un congrès
lirmm-03987914
v1
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Reducing Overprovision of Triple Modular Reduncancy Owing to Approximate ComputingIOLTS 2021 - 27th IEEE International Symposium on On-Line Testing and Robust System Design, Jun 2021, Torino, Italy. pp.1-7, ⟨10.1109/IOLTS52814.2021.9486699⟩
Communication dans un congrès
lirmm-03380025
v1
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Preliminary Defect Analysis of 8T SRAM Cells Used for In-Memory Computing15e Colloque National du GDR SoC², Jun 2021, Rennes, France
Communication dans un congrès
lirmm-03994467
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Self-Test Libraries Analysis for Pipelined Processors Transition Fault Coverage ImprovementPESW 2021 - 9th Prague Embedded Systems Workshop, Jul 2021, Horoměřice, Czech Republic
Communication dans un congrès
lirmm-03988459
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Preliminary Defect Analysis of 8T SRAM Cells for In-Memory Computing ArchitecturesDTIS 2021 - 16th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, Jun 2021, Montpellier, France. ⟨10.1109/DTIS53253.2021.9505101⟩
Communication dans un congrès
lirmm-03377433
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A Fast and Low Cost Embedded Test Solution for CMOS Image SensorsITC 2021 - IEEE International Test Conference, Oct 2021, Online, United States. pp.1-9, ⟨10.1109/ITC50571.2021.00007⟩
Communication dans un congrès
lirmm-03377562
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Emerging Computing Devices: Challenges and Opportunities for Test and ReliabilityETS 2021 - 26th IEEE European Test Symposium, May 2021, Bruges, Belgium. pp.1-10, ⟨10.1109/ETS50041.2021.9465409⟩
Communication dans un congrès
lirmm-03379074
v1
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A Novel BIST Engine for CMOS Image Sensors15e Colloque National du GDR SoC², Jun 2021, Rennes, France
Communication dans un congrès
lirmm-03987828
v1
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Cell-Aware Diagnosis of Customer Returns Using Bayesian InferenceISQED 2021 - 22nd International Symposium on Quality Electronic Design, Apr 2021, Santa Clara (virtual), United States. pp.48-53, ⟨10.1109/ISQED51717.2021.9424337⟩
Communication dans un congrès
hal-03266815
v1
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A Learning-Based Methodology for Accelerating Cell-Aware Model GenerationDATE 2021 - 24th Design, Automation and Test in Europe Conference and Exhibition, Feb 2021, Grenoble, France. pp.1580-1585, ⟨10.23919/DATE51398.2021.9474227⟩
Communication dans un congrès
lirmm-03377383
v1
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Accelerating Cell-Aware Model Generation Through Machine Learning15e Colloque National du GDR SoC², Jun 2021, Rennes, France
Communication dans un congrès
lirmm-03987805
v1
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A Learning-Based Cell-Aware Diagnosis Flow for Industrial Customer ReturnsITC 2020 - IEEE International Test Conference, Nov 2020, Washington DC, United States. pp.1-10, ⟨10.1109/ITC44778.2020.9325246⟩
Communication dans un congrès
lirmm-03034264
v1
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A Plug and Play Digital ABIST Controller for Analog Sensors in Secure DevicesETS 2021 - 26th IEEE European Test Symposium, May 2021, Bruges, Belgium. pp.1-4, ⟨10.1109/ETS50041.2021.9465480⟩
Communication dans un congrès
lirmm-03305266
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Self-Test Libraries Analysis for Pipelined Processors Transition Fault Coverage ImprovementIOLTS 2021 - 27th IEEE International Symposium on On-Line Testing and Robust System Design, Jun 2021, Torino, Italy. pp.1-4, ⟨10.1109/IOLTS52814.2021.9486711⟩
Communication dans un congrès
lirmm-03380201
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A CMOS OxRAM-Based Neuron Circuit Hardened with Enclosed Layout Transistors for Aerospace ApplicationsIOLTS 2020 - 26th IEEE International Symposium on On-Line Testing and Robust System Design, Jul 2020, Napoli, Italy. pp.1-6, ⟨10.1109/IOLTS50870.2020.9159709⟩
Communication dans un congrès
lirmm-03035780
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Maximizing Yield for Approximate Integrated CircuitsDATE 2020 - 23rd Design, Automation and Test in Europe Conference and Exhibition, Mar 2020, Grenoble, France. pp.810-815, ⟨10.23919/DATE48585.2020.9116341⟩
Communication dans un congrès
lirmm-03036002
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QAMR: an Approximation-Based FullyReliable TMR Alternative for Area Overhead ReductionETS 2020 - 25th IEEE European Test Symposium, May 2020, Tallinn, Estonia. pp.1-6, ⟨10.1109/ETS48528.2020.9131574⟩
Communication dans un congrès
lirmm-03035640
v1
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A Novel Test Flow for Approximate Digital CircuitsDATE 2020 - EDAA/IEEE/ACM Design Automation & Test in Europe Conference, PhD Forum, Mar 2020, Grenoble, France
Communication dans un congrès
lirmm-03993654
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Design, Verification, Test and In-Field Implications of Approximate Computing SystemsETS 2020 - 25th IEEE European Test Symposium, May 2020, Tallinn, Estonia. pp.1-10, ⟨10.1109/ETS48528.2020.9131557⟩
Communication dans un congrès
lirmm-03035724
v1
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Learning-Based Cell-Aware Defect Diagnosis of Customer ReturnsETS 2020 - 25th IEEE European Test Symposium, May 2020, Tallinn, Estonia. pp.1-2, ⟨10.1109/ETS48528.2020.9131601⟩
Communication dans un congrès
lirmm-03035669
v1
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Development and Application of Embedded Test Instruments to Digital, Analog/RFs and Secure ICsIOLTS 2020 - 26th IEEE International Symposium on On-Line Testing and Robust System Design, Jul 2020, Napoli, Italy. pp.1-4, ⟨10.1109/IOLTS50870.2020.9159723⟩
Communication dans un congrès
lirmm-02993384
v1
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Investigation of Mean-Error Metrics for Testing Approximate Integrated CircuitsDFT 2018 - 31st IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, Oct 2018, Chicago, United States. pp.1-6, ⟨10.1109/DFT.2018.8602939⟩
Communication dans un congrès
lirmm-02099895
v1
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Cell-Aware Diagnosis of Automotive Customer Returns Based on Supervised LearningART 2019 - 4th IEEE Automotive Reliability and Test Workshop, Nov 2019, Washington, United States
Communication dans un congrès
lirmm-02395653
v1
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A Capacitor-Less CMOS Neuron Circuit for Neuromemristive NetworksNEWCAS 2019 - 17th IEEE International Conference on Electronics Circuits and Systems, Jun 2019, Munich, Germany. ⟨10.1109/NEWCAS44328.2019.8961278⟩
Communication dans un congrès
lirmm-02395325
v1
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Towards Improvement of Mission Mode Failure Diagnosis for System-on-ChipIOLTS 2019 - 25th IEEE International Symposium on On-Line Testing and Robust System Design, Jul 2019, Rhodes, Greece. pp.21-26, ⟨10.1109/IOLTS.2019.8854388⟩
Communication dans un congrès
lirmm-02395493
v1
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An Effective Intra-Cell Diagnosis Flow for Industrial SRAMsITC 2018 - IEEE International Test Conference, Oct 2018, Phoenix, United States. pp.1-8, ⟨10.1109/TEST.2018.8624799⟩
Communication dans un congrès
lirmm-02099874
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On the Comparison of Different ATPG approaches for Approximate Integrated CircuitsDDECS 2018 - 1st International Symposium on Design and Diagnostics of Electronic Circuits and Systems, Apr 2018, Budapest, Hungary. pp.85-90, ⟨10.1109/DDECS.2018.00022⟩
Communication dans un congrès
lirmm-03032856
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Is aproximate computing suitable for selective hardening of arithmetic circuits?DTIS 2018 - 13th International Conference on Design and Technology of Integrated Systems in Nanoscale Era, Apr 2018, Taormina, Italy. pp.1-6, ⟨10.1109/DTIS.2018.8368559⟩
Communication dans un congrès
lirmm-03130537
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Testing Approximate Digital Circuits: Challenges and OpportunitiesLATS 2018 - 19th IEEE Latin American Test Symposium, Mar 2018, Sao Paulo, Brazil. pp.1-6, ⟨10.1109/LATW.2018.8349681⟩
Communication dans un congrès
lirmm-03033024
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Can we Approximate the Test of Integrated Circuits?WAPCO: Workshop On Approximate Computing, Jan 2017, Stockholm, Sweden
Communication dans un congrès
lirmm-02004418
v1
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Approximate computing: Design & test for integrated circuitsLATS 2017 - 18th IEEE Latin American Test Symposium, Mar 2017, Bogota, Colombia. ⟨10.1109/LATW.2017.7906737⟩
Communication dans un congrès
lirmm-01718600
v1
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Towards digital circuit approximation by exploiting fault simulationEWDTS: East-West Design & Test Symposium, Sep 2017, Novi Sad, Serbia. ⟨10.1109/EWDTS.2017.8110108⟩
Communication dans un congrès
lirmm-01718583
v1
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Towards approximation during test of Integrated CircuitsDDECS 2017 - 20th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, Apr 2017, Dresden, Germany. pp.28-33, ⟨10.1109/DDECS.2017.7934574⟩
Communication dans un congrès
lirmm-01718580
v1
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An effective fault-injection framework for memory reliability enhancement perspectivesDTIS: Design and Technology of Integrated Systems in Nanoscale Era, Apr 2017, Palma de Mallorca, Spain. ⟨10.1109/DTIS.2017.7930172⟩
Communication dans un congrès
lirmm-01718579
v1
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An Advanced Diagnosis Flow for SRAMsISTFA 2017 - 43rd International Symposium for Testing and Failure Analysis, Nov 2017, Pasadena, United States. pp.538-543, ⟨10.31399/asm.cp.istfa2017p0538⟩
Communication dans un congrès
lirmm-01718596
v1
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Improving the Functional Test Delay Fault Coverage: A Microprocessor Case StudyISVLSI: International Symposium on Very Large Scale Integration, Jul 2016, Pittsburgh, PA, United States. pp.731-736, ⟨10.1109/ISVLSI.2016.42⟩
Communication dans un congrès
lirmm-01446917
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An effective BIST architecture for power-gating mechanisms in low-power SRAMsISQED 2016 - 17th International Symposium on Quality Electronic Design, Mar 2016, Santa Clara, CA, United States. pp.185-191, ⟨10.1109/ISQED.2016.7479198⟩
Communication dans un congrès
lirmm-01457424
v1
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A Case Study on the Approximate Test of Integrated CircuitsAC: Approximate Computing, Oct 2016, Pittsburgh, PA, United States
Communication dans un congrès
lirmm-01718609
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Test of Low Power Circuits: Issues and Industrial PracticesICECS: International Conference on Electronics, Circuits and Systems, Dec 2016, Monte Carlo, Monaco
Communication dans un congrès
lirmm-01433330
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A Low-Cost Reliability vs. Cost Trade-Off Methodology to Selectively Harden Logic CircuitsETS: European Test Symposium, May 2016, Amsterdam, Netherlands. ⟨10.1109/ETS.2016.7519296⟩
Communication dans un congrès
hal-01444734
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A Hybrid Power Estimation Technique to improve IP power models qualityVLSI-SoC: Very Large Scale Integration and System-on-Chip, Sep 2016, Tallin, Estonia. ⟨10.1109/VLSI-SoC.2016.7753582⟩
Communication dans un congrès
lirmm-01689544
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An effective approach for functional test programs compactionDDECS: Design and Diagnostics of Electronic Circuits and Systems, Apr 2016, Kosice, Slovakia. ⟨10.1109/DDECS.2016.7482466⟩
Communication dans un congrès
lirmm-01457396
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Auto-adaptive ultra-low power ICDTIS: Design and Technology of Integrated Systems in Nanoscale Era, Apr 2016, Istanbaul, Turkey. ⟨10.1109/DTIS.2016.7483886⟩
Communication dans un congrès
lirmm-01457361
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A hybrid power modeling approach to enhance high-level power modelsDDECS: Design and Diagnostics of Electronic Circuits and Systems, Apr 2016, Kosice, Slovakia. ⟨10.1109/DDECS.2016.7482453⟩
Communication dans un congrès
lirmm-01446854
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Analysis of Setup & Hold Margins Inside Silicon for Advanced Technology NodesISQED 2016 - 17th International Symposium on Quality Electronic Design, Mar 2016, Santa Clara, CA, United States. pp.295-300, ⟨10.1109/ISQED.2016.7479217⟩
Communication dans un congrès
lirmm-01433314
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An efficient hybrid power modeling approach for accurate gate-level power estimationICM: International Conference on Microelectronics, Dec 2015, Casablanca, Morocco. pp.17-20, ⟨10.1109/ICM.2015.7437976⟩
Communication dans un congrès
lirmm-01354745
v1
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Design space exploration and optimization of a Hybrid Fault-Tolerant ArchitectureIOLTS: International On-Line Testing Symposium, Jul 2015, Halkidiki, Greece. pp.89-94, ⟨10.1109/IOLTS.2015.7229838⟩
Communication dans un congrès
lirmm-01272735
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Scan-chain intra-cell defects gradingDTIS: Design and Technology of Integrated Systems in Nanoscale Era, Apr 2015, Naples, Italy. ⟨10.1109/DTIS.2015.7127349⟩
Communication dans un congrès
lirmm-01272696
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Design and performance parameters of an ultra-low voltage, single supply 32bit processor implemented in 28nm FDSOI technologyISQED 2015 - 16th International Symposium on Quality Electronic Design, Apr 2015, Santa Clara, United States. pp.366-370, ⟨10.1109/ISQED.2015.7085453⟩
Communication dans un congrès
lirmm-01272913
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An effective hybrid fault-tolerant architecture for pipelined coresETS: European Test Symposium, May 2015, Cluj-Napoca, Romania. ⟨10.1109/ETS.2015.7138733⟩
Communication dans un congrès
lirmm-01272730
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An effective ATPG flow for Gate Delay FaultsDTIS: Design and Technology of Integrated Systems in Nanoscale Era, Apr 2015, Naples, Italy. ⟨10.1109/DTIS.2015.7127350⟩
Communication dans un congrès
lirmm-01272719
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An Experimental Comparative Study of Fault-Tolerant ArchitecturesVALID: Advances in System Testing and Validation Lifecycle, Nov 2015, Barcelone, Spain. pp.1-6
Communication dans un congrès
lirmm-01354754
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Exploring the impact of functional test programs re-used for power-aware testingDATE 2015 - 18th Design, Automation and Test in Europe Conference and Exhibition, Mar 2015, Grenoble, France. pp.1277-1280, ⟨10.7873/DATE.2015.1031⟩
Communication dans un congrès
lirmm-01272937
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Design-for-Diagnosis Architecture for Power SwitchesDDECS: Design and Diagnostics of Electronic Circuits and Systems, Apr 2015, Belgrade, Serbia. pp.43-48, ⟨10.1109/DDECS.2015.18⟩
Communication dans un congrès
lirmm-01272684
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An ATPG Flow to Generate Crosstalk-Aware Path Delay PatternISVLSI: International Symposium on Very Large Scale Integration, Jul 2015, Montpellier, France. pp.515-520, ⟨10.1109/ISVLSI.2015.99⟩
Communication dans un congrès
lirmm-01272933
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A Comprehensive Evaluation of Functional Programs for Power-Aware TestNATW: North Atlantic Test Workshop, May 2014, Johnson City, NY, United States. pp.69-72, ⟨10.1109/NATW.2014.23⟩
Communication dans un congrès
lirmm-01248597
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TSV aware timing analysis and diagnosis in paths with multiple TSVsVTS: VLSI Test Symposium, Apr 2014, Napa, CA, United States. ⟨10.1109/VTS.2014.6818772⟩
Communication dans un congrès
lirmm-01248594
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Timing-aware ATPG for critical paths with multiple TSVsDDECS: Design and Diagnostics of Electronic Circuits and Systems, Apr 2014, Warsaw, Poland. pp.116-121, ⟨10.1109/DDECS.2014.6868774⟩
Communication dans un congrès
lirmm-01248600
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A Delay Probability Metric for Input Pattern Ranking Under Process Variation and Supply NoiseISVLSI: International Symposium on Very Large Scale Integration, Jul 2014, Tampa, FL, United States. pp.226-231, ⟨10.1109/ISVLSI.2014.42⟩
Communication dans un congrès
lirmm-01248592
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Test and diagnosis of power switchesDDECS: Design and Diagnostics of Electronic Circuits and Systems, Apr 2014, Warsaw, Poland. pp.213-218, ⟨10.1109/DDECS.2014.6868792⟩
Communication dans un congrès
lirmm-01248590
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Path delay test in the presence of multi-aggressor crosstalk, power supply noise and ground bounceDDECS: Design and Diagnostics of Electronic Circuits and Systems, Apr 2014, Warsaw, Poland. pp.207-212, ⟨10.1109/DDECS.2014.6868791⟩
Communication dans un congrès
lirmm-01248599
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Power supply noise-aware workload assignments for homogeneous 3D MPSoCs with thermal considerationASP-DAC: Asia and South Pacific Design Automation Conference, Jan 2014, Singapore, Singapore. pp.544-549, ⟨10.1109/ASPDAC.2014.6742948⟩
Communication dans un congrès
lirmm-01248596
v1
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iBoX — Jitter based Power Supply Noise sensorETS: European Test Symposium, May 2014, Paderborn, United States. ⟨10.1109/ETS.2014.6847830⟩
Communication dans un congrès
lirmm-01248601
v1
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Real-Time Testing of 90nm COTS SRAMs at Concordia Station in AntarcticaNSREC: Nuclear and Space Radiation Effects Conference, Jul 2014, Paris, France
Communication dans un congrès
lirmm-01237709
v1
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Efficient Dynamic Test Methods for COTS SRAMs Under Heavy Ion IrradiationNSREC: Nuclear and Space Radiation Effects Conference, Jul 2014, Paris, France
Communication dans un congrès
lirmm-01237660
v1
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Protecting combinational logic in pipelined microprocessor cores against transient and permanent faultsDDECS: Design and Diagnostics of Electronic Circuits and Systems, Apr 2014, Warsaw, Poland. pp.223-225, ⟨10.1109/DDECS.2014.6868794⟩
Communication dans un congrès
lirmm-01248598
v1
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On the Generation of Diagnostic Test Set for Intra-cell DefectsATS: Asian Test Symposium, Nov 2014, Hangzhou, China. pp.312-317, ⟨10.1109/ATS.2014.57⟩
Communication dans un congrès
lirmm-01272539
v1
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Adaptive Source Bias for Improved Resistive-Open Defect Coverage during SRAM TestingATS: Asian Test Symposium, Nov 2013, Jiaosi Township, Taiwan. pp.109-114, ⟨10.1109/ATS.2013.30⟩
Communication dans un congrès
lirmm-01248609
v1
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SRAM Soft Error Rate Evaluation Under Atmospheric Neutron Radiation and PVT variationsIOLTS: International On-Line Testing Symposium, Jul 2013, Chania, Crete, Greece. pp.145-150, ⟨10.1109/IOLTS.2013.6604066⟩
Communication dans un congrès
lirmm-00818955
v1
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On the correlation between Static Noise Margin and Soft Error Rate evaluated for a 40nm SRAM cellDFT: Defect and Fault Tolerance in VLSI and Nanotechnology Systems, Oct 2013, New York, United States. pp.143-148, ⟨10.1109/DFT.2013.6653597⟩
Communication dans un congrès
lirmm-01238413
v1
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A novel method to mitigate TSV electromigration for 3D ICsISVLSI: IEEE Computer Society Annual Symposium on VLSI, Aug 2013, Natal, Brazil. pp.121-126, ⟨10.1109/ISVLSI.2013.6654633⟩
Communication dans un congrès
lirmm-01248617
v1
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Test Solution for Data Retention Faults in Low-Power SRAMsDATE 2013 - 16th Design, Automation and Test in Europe Conference, Mar 2013, Grenoble, France. pp.442-447, ⟨10.7873/DATE.2013.099⟩
Communication dans un congrès
lirmm-00805140
v1
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On the Reuse of Read and Write Assist Circuits to Improve Test Efficiency in Low-Power SRAMsITC: International Test conference, Sep 2013, Anaheim, CA, United States. pp.1-10, ⟨10.1109/TEST.2013.6651927⟩
Communication dans un congrès
lirmm-00818977
v1
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Performance Characterization of TAS-MRAM Architectures in Presence of Capacitive DefectsVALID: Advances in System Testing and Validation Lifecycle, Oct 2013, Venice, Italy. pp.39-44
Communication dans un congrès
lirmm-01433308
v1
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Analyzing resistive-open defects in SRAM core-cell under the effect of process variabilityETS: European Test Symposium, May 2013, Avignon, France. ⟨10.1109/ETS.2013.6569373⟩
Communication dans un congrès
lirmm-01921630
v1
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Characterization of an SRAM Based Particle Detector For Mixed-Field Radiation EnvironmentsIWASI: International Workshop on Advances in Sensors and Interfaces, Jun 2013, Bari, Italy. pp.75-80, ⟨10.1109/IWASI.2013.6576070⟩
Communication dans un congrès
lirmm-00839046
v1
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Temperature Impact on the Neutron SER of a Commercial 90nm SRAMNSREC: Nuclear and Space Radiation Effects Conference, Jul 2013, San Francisco, Ca, United States. pp.1-4
Communication dans un congrès
lirmm-00805291
v1
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Fast and Accurate Electro-Thermal Analysis of Three-Dimensional Power Delivery NetworksEuroSimE: Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems, Apr 2013, Wroclaw, Poland. pp.1-4, ⟨10.1109/EuroSimE.2013.6529956⟩
Communication dans un congrès
lirmm-00839043
v1
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Effect-Cause Intra-Cell Diagnosis at Transistor LevelISQED 2013 - 14th International Symposium on Quality Electronic Design, Mar 2013, Santa Clara, CA, United States. pp.460-467, ⟨10.1109/ISQED.2013.6523652⟩
Communication dans un congrès
lirmm-00817224
v1
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Multiple-Cell-Upsets on a commercial 90nm SRAM in Dynamic ModeRADECS: Radiation and Its Effects on Components and Systems, Sep 2013, Oxford, United Kingdom. pp.1-4, ⟨10.1109/RADECS.2013.6937429⟩
Communication dans un congrès
lirmm-00839062
v1
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Mitigate TSV Electromigration for 3D ICs - From the Architecture PerspectiveInternational Symposium on VLSI, Natale, Brazil. pp.6
Communication dans un congrès
lirmm-00839052
v1
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Evaluating An SEU Monitor For Mixed-Field Radiation EnvironmentsiWoRID: International Workshop on Radiation Imaging Detectors, SOLEIL Synchrotron, Jun 2013, Paris, France
Communication dans un congrès
lirmm-01238433
v1
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Improving Defect Localization Accuracy by means of Effect-Cause Intra-Cell Diagnosis at Transistor LevelSDD: Silicon Debug and Diagnosis, Sep 2013, Anaheim, CA, United States
Communication dans un congrès
lirmm-00806872
v1
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SEU Monitoring in Mixed-Field Radiation Environments of Particle AcceleratorsRADECS: Radiation and Its Effects on Components and Systems, Sep 2013, Oxford, United Kingdom. pp.1-4, ⟨10.1109/RADECS.2013.6937419⟩
Communication dans un congrès
lirmm-00839085
v1
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Worst-Case Power Supply Noise and Temperature Distribution Analysis for 3D PDNs with Multiple Clock DomainsNEWCAS: New Circuits and Systems, Jun 2013, Paris, France. ⟨10.1109/NEWCAS.2013.6573628⟩
Communication dans un congrès
lirmm-00839042
v1
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Analyzing the effect of concurrent variability in the core cells and sense amplifiers on SRAM read access failuresDTIS: Design and Technology of Integrated Systems in Nanoscale Era, Mar 2013, Abu Dhabi, United Arab Emirates. pp.39-44, ⟨10.1109/DTIS.2013.6527775⟩
Communication dans un congrès
lirmm-01248603
v1
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A Built-in Scheme for Testing and Repairing Voltage Regulators of Low-Power SRAMsVTS: VLSI Test Symposium, Apr 2013, Berkeley, CA, United States. pp.1-6, ⟨10.1109/VTS.2013.6548894⟩
Communication dans un congrès
lirmm-00805366
v1
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Computing Detection Probability of Delay Defects in Signal Line TSVsETS: European Test Symposium, May 2013, Avignon, France. ⟨10.1109/ETS.2013.6569349⟩
Communication dans un congrès
lirmm-00839044
v1
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Electro-Thermal Analysis of 3D Power Delivery NetworksDAC: Design Automation Conference, 2012, San Francisco, United States
Communication dans un congrès
lirmm-00806836
v1
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Dynamic Mode Test of a Commercial 4Mb Toggle MRAM under Neutron RadiationRADECS: European Conference on Radiation and Its Effects on Components and Systems, Sep 2012, Biarritz, France. pp.1-4
Communication dans un congrès
lirmm-00805165
v1
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Radiation Induced Effects on Electronic Systems and ICsSETS: South European Test Seminar, Mar 2012, Sauze d'Oulx, Italy
Communication dans un congrès
lirmm-00807055
v1
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Fault Localization Improvement through an Intra-Cell Diagnosis ApproachISTFA 2012 - 38th International Symposium for Testing and Failure Analysis, Nov 2012, Phoenix, AZ, United States. pp.509-519
Communication dans un congrès
lirmm-00806863
v1
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Defect Localization Through an Effect-Cause based Intra-Cell DiagnosisColloque GDR SoC-SiP, 2012, Paris, France
Communication dans un congrès
lirmm-00806841
v1
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Impact of Resistive-Open Defects on the Heat Current of TAS-MRAM ArchitecturesDATE 2012 - 15th Design, Automation and Test in Europe Conference and Exhibition, Mar 2012, Dresden, Germany. pp.532-537, ⟨10.1109/DATE.2012.6176526⟩
Communication dans un congrès
lirmm-00689024
v1
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SRAM testing under Neutron Radiation for the evaluation of different algorithms stress15ème Journées Nationales du Réseau Doctoral en Microélectronique, Jun 2012, Marseille, France
Communication dans un congrès
lirmm-00807054
v1
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Power Supply Noise Sensor Based on Timing Uncertainty MeasurementsATS: Asian Test Symposium, Nov 2012, Niigata, Japan. pp.161-166, ⟨10.1109/ATS.2012.46⟩
Communication dans un congrès
lirmm-00806890
v1
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Low-power SRAMs Power Mode Control Logic: Failure Analysis and Test SolutionsITC'2012: International Test Conference, Nov 2012, Anaheim, CA, United States. pp.1-10, ⟨10.1109/TEST.2012.6401578⟩
Communication dans un congrès
lirmm-00805143
v1
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A Novel Framework for Evaluating the SRAM Core-Cell Sensitivity to NeutronsRADECS: European Conference on Radiation and Its Effects on Components and Systems, Sep 2012, Biarritz, France. pp.1-4
Communication dans un congrès
lirmm-00805163
v1
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On Using Address Scrambling for Defect Tolerance in SRAMsInternational test Conference, Sep 2011, Anaheim, CA, United States. pp.1-8, ⟨10.1109/TEST.2011.6139149⟩
Communication dans un congrès
lirmm-00805334
v1
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Resistive-Open Defects Affecting Bit-Line Selection in TAS-MRAM ArchitecturesJNRDM: Journées Nationales du Réseau Doctoral en Microélectronique, 2012, Paris, France
Communication dans un congrès
lirmm-00806827
v1
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Resistive-Open Defect Analysis for Through-Silicon-ViasDCIS 2012 - 27th Conference on Design of Circuits and Integrated Systems, Nov 2012, Avignon, France
Communication dans un congrès
lirmm-00806803
v1
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Dynamic Mode Testing of SRAMS under Neutron RadiationSixième colloque du GDR SOC-SIP du CNRS, Jun 2012, Paris, France
Communication dans un congrès
lirmm-00807053
v1
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Defect Analysis in Power Mode Control Logic of Low-Power SRAMsETS: European Test Symposium, May 2012, Annecy, France. ⟨10.1109/ETS.2012.6233033⟩
Communication dans un congrès
lirmm-00805374
v1
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Impact of Resistive-Bridge Defects in TAS-MRAM ArchitecturesATS: Asian Test Symposium, Nov 2012, Niigata, Japan. pp.125-130, ⟨10.1109/ATS.2012.37⟩
Communication dans un congrès
lirmm-00806809
v1
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A Pseudo-Dynamic Comparator for Error Detection in Fault Tolerant ArchitecturesVTS: VLSI Test Symposium, Apr 2012, Hawaii, United States. pp.50-55, ⟨10.1109/VTS.2012.6231079⟩
Communication dans un congrès
lirmm-00806778
v1
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Advanced Test Methods for SRAMsVTS: VLSI Test Symposium, Apr 2012, Hyatt Maui, HI, United States. pp.300-301, ⟨10.1109/VTS.2012.6231070⟩
Communication dans un congrès
lirmm-00805049
v1
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Evaluation of Test Algorithms Stress Effect on SRAMs under Neutron RadiationIOLTS: International On-Line Testing Symposium, Jun 2012, Sitges, Spain. pp.212-222, ⟨10.1109/IOLTS.2012.6313853⟩
Communication dans un congrès
lirmm-00805373
v1
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Adaptive Voltage Scaling via Effective On-Chip Timing Uncertainty MeasurementsColloque GDR SoC-SiP, 2012, Paris, France
Communication dans un congrès
lirmm-00806859
v1
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Impacts of Resistive-Open Defects in the Word-Line Selection of TAS-MRAMsColloque GDR SoC-SiP, 2012, Paris, France
Communication dans un congrès
lirmm-00806842
v1
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Through-Silicon-Via Resistive-Open Defect AnalysisETS: European Test Symposium, May 2012, Annecy, France. ⟨10.1109/ETS.2012.6233037⟩
Communication dans un congrès
lirmm-00806848
v1
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Why and How Controlling Power Consumption During Test: A SurveyATS: Asian Test Symposium, Nov 2012, Niigata, Japan. pp. 221-226, ⟨10.1109/ATS.2012.30⟩
Communication dans un congrès
lirmm-00818984
v1
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Complete Framework for the Estimation of the SRAM Core-Cell Resilience to RadiationRADECS: Radiation and its Effects on Components and Systems, Sep 2012, Biarritz, France
Communication dans un congrès
hal-01935785
v1
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Optimized March Test Flow for Detecting Memory Faults in SRAM Devices Under Bit Line CouplingGDR SOC-SIP'11 : Colloque GDR SoC-SiP, Lyon, France
Communication dans un congrès
lirmm-00679522
v1
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A DfT Solution for Oxide Thickness Varitions in ATMEL eFlash TechnologyDTIS: Design and Technology of Integrated Systems in Nanoscale Era, 2011, Athènes, Greece
Communication dans un congrès
lirmm-00647750
v1
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Power Reduction Through X-filling of Transition Fault Test Vectors for LOS TestingDTIS: Design and Technology of Integrated Systems in Nanoscale Era, 2011, Athènes, Greece. ⟨10.1109/DTIS.2011.5941434⟩
Communication dans un congrès
lirmm-00647760
v1
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Variability Analysis of an SRAM Test ChipETS: European Test Symposium, May 2011, Trondheim, Norway
Communication dans un congrès
lirmm-00651791
v1
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On using a SPICE-like TSTAC™ eFlash model for design and testDDECS: Design and Diagnostics of Electronic Circuits ans Systems, Apr 2011, Cottbus, Germany. pp.359-370, ⟨10.1109/DDECS.2011.5783111⟩
Communication dans un congrès
lirmm-00592203
v1
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A Hybrid Fault Tolerant Architecture for Robustness Improvement of Digital CircuitsGDR SOC-SIP'11 : Colloque GDR SoC-SiP, Lyon, France
Communication dans un congrès
lirmm-00679513
v1
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Error Resilient Infrastructure for Data Transfer in a Distributed Neutron DetectorDFT 2011 - International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, Oct 2011, Vancouver, Canada. pp.294-301, ⟨10.1109/DFT.2011.41⟩
Communication dans un congrès
lirmm-00651226
v1
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Failure Analysis and Test Solutions for Low-Power SRAMsATS: Asian Test Symposium, Nov 2011, New Delhi, India. pp.459-460, ⟨10.1109/ATS.2011.97⟩
Communication dans un congrès
lirmm-00805123
v1
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Mapping Test Power to Functional Power through Smart X-Filling for LOS SchemeLPonTR'11: IEEE International Workshop on the Impact of Low Power on Test and Reliability, Trondheim, Norway
Communication dans un congrès
lirmm-00651905
v1
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A Hybrid Fault Tolerant Architecture for Robustness Improvement of Digital CircuitsATS 2011 - 20th IEEE Asian Test Symposium, Nov 2011, New Delhi, India. pp.136-141, ⟨10.1109/ATS.2011.89⟩
Communication dans un congrès
lirmm-00651238
v1
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Effective Launch-to-Capture Power Reduction for LOS Scheme with Adjacent-Probability-Based X-FillingATS: Asian Test Symposium, 2011, New Delhi, India. pp.21-23
Communication dans un congrès
lirmm-00651247
v1
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Test and Reliability of Magnetic Random Access MemoriesGDR SOC-SIP'11: Colloque GDR SoC-SiP, Lyon, France
Communication dans un congrès
lirmm-00679516
v1
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A Functional Power Evaluation Flow for Defining Test Power Limits during At-Speed Delay TestingETS 2011 - 16th IEEE European Test Symposium, May 2011, Trondheim, Norway. pp.153-158, ⟨10.1109/ETS.2011.21⟩
Communication dans un congrès
lirmm-00647822
v1
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On Using Address Scrambling to Implement Defect Tolerance in SRAMsITC'2011: International Test Conference, Sep 2011, Anaheim, CA, United States. pp.N/A
Communication dans un congrès
lirmm-00647773
v1
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Power Supply Noise and Ground Bounce Aware Pattern Generation for Delay TestingNEWCAS: International New Circuits and Systems Conference, Jun 2011, Bordeaux, France. pp.73-76, ⟨10.1109/NEWCAS.2011.5981222⟩
Communication dans un congrès
lirmm-00647815
v1
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Power-Aware Test Pattern Generation for At-Speed LOS TestingATS: Asian Test Symposium, Nov 2011, New Delhi, India. pp.506-510
Communication dans un congrès
lirmm-00651917
v1
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Impact of Technology Scaling on Defects and Parameter Deviations in Embedded SRAMsNVM'11: Leading-Edge Embedded NVM Workshop, Gardane, France
Communication dans un congrès
lirmm-00679494
v1
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A Study of Path Delay Variations in the Presence of Uncorrelated Power and Ground Supply NoiseDDECS: Design and Diagnostics of Electronic Circuits and Systems, Apr 2011, Cottbus, Germany. pp.189-194, ⟨10.1109/DDECS.2011.5783078⟩
Communication dans un congrès
lirmm-00592000
v1
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Optimized March Test Flow for Detecting Memory Faults in SRAM Devices Under Bit Line CouplingDDECS'11: 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits ans Systems, Netherlands. pp.353-358
Communication dans un congrès
lirmm-00592182
v1
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Simultaneous Power and Thermal Integrity Analysis for 3D Integrated SystemsLPonTR'11: IEEE International Workshop on the Impact of Low Power on Test and Reliability, Trondheim, Norway
Communication dans un congrès
lirmm-00651802
v1
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Robust Structure for Data Collection and Transfer in a Distributed SRAM Based Neutron Test BenchWorkshop on Dependability Issues in Deep-Submicron Technologies, Trondheim, Norway
Communication dans un congrès
lirmm-00651796
v1
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Robustness Improvement of Digital Circuits A New Hybrid Fault Tolerant ArchitectureJNRDM'11: Journées Nationales du Réseau Doctoral de Microélectronique, Paris, France
Communication dans un congrès
lirmm-00679509
v1
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Analysis of Resistive-Open Defects in TAS-MRAM ArrayITC: International Test Conference, Sep 2011, Anaheim, CA, United States
Communication dans un congrès
lirmm-00679524
v1
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Analysis of Resistive-Bridging Defects in SRAM Core-Cells: a Comparative Study from 90nm down to 40nm Technology NodesETS: European Test Symposium, May 2010, Prague, Czech Republic. pp.132-137
Communication dans un congrès
lirmm-00493236
v1
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A Two-Layer SPICE Model of the ATMEL TSTAC eFlash Memory Technology for Defect Injection and Faulty Behavior PredictionETS: European Test Symposium, May 2010, Prague, Czech Republic. pp.81-86
Communication dans un congrès
lirmm-00493204
v1
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Tolérance aux fautes et rendement de fabricationGDR SOC-SIP'10 : Colloque GDR SoC-SiP, Cergy, France
Communication dans un congrès
lirmm-00553995
v1
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Detecting NBTI Induced Failures in SRAM Core-CellsVTS'10: VLSI Test Symposium, Santa Cruz, CA, United States. pp.75-80
Communication dans un congrès
lirmm-00553612
v1
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Test Relaxation and X-filling to Reduce Peak Power During At-Speed LOS TestingGDR SOC-SIP'10 : Colloque GDR SoC-SiP, Cergy, France
Communication dans un congrès
lirmm-00553989
v1
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Setting Test Conditions for Improving SRAM ReliabilityETS: European Test Symposium, May 2010, Prague, Czech Republic. pp.257-262
Communication dans un congrès
lirmm-00492741
v1
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Impact of Resistive-Bridging Defects in SRAM Core-CellDELTA'10: International Symposium on Electronic Design, Test & Applications, Ho Chi Minh, Vietnam. pp.265-270
Communication dans un congrès
lirmm-00553592
v1
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Power Reduction Through X-filling of Transition Fault Test Vectors for LOS TestingLPonTR:
Impact of Low-Power design on Test and Reliability, May 2010, Prague, Czech Republic
Communication dans un congrès
lirmm-00553930
v1
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A Memory Fault Simulator for Radiation-Induced Effects in SRAMsATS: Asian Test Symposium, 2010, Shanghai, China. pp.100-105
Communication dans un congrès
lirmm-00545102
v1
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Analysis and Fault Modeling of Actual Resistive Defects in Flash MemoriesJNRDM'10 : Journées Nationales du Réseau Doctoral de Microélectronique, Montpellier, France
Communication dans un congrès
lirmm-00553935
v1
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Analyse et modélisation des défauts résistifs affectant les mémoires FlashGDR SOC-SIP'10 : Colloque GDR SoC-SiP, Cergy, France
Communication dans un congrès
lirmm-00553947
v1
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Analysis of Power Consumption and Transition Fault Coverage for LOS and LOC Testing SchemesDDECS'10: 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, Apr 2010, Vienna, Austria. pp.376-381
Communication dans un congrès
lirmm-00475734
v1
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Setting Test Conditions for Detecting Faults Induced by Random Dopant Fluctuation in SRAM Core-CellsVARI: Workshop on CMOS Variability, 2010, Montpellier, France
Communication dans un congrès
lirmm-00553626
v1
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A Comprehensive System-on-Chip Logic DiagnosisATS: Asian Test Symposium, 2010, Shanghai, China. pp.237-242
Communication dans un congrès
lirmm-00545131
v1
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A Statistical Simulation Method for Reliability Analysis of SRAM Core-CellsDAC: Design Automation Conference, Jun 2010, Anaheim, United States. pp.853-856
Communication dans un congrès
lirmm-00553619
v1
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Delay Fault Diagnosis in Sequential CircuitsATS: Asian Test Symposium, Nov 2009, Taichung, Taiwan. pp.355-360
Communication dans un congrès
lirmm-00406968
v1
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A Fault-Simulation-Based Approach for Logic DiagnosisDTIS: Design and Technology of Integrated Systems in Nanoscale Era, Apr 2009, Cairo, Egypt. pp.216-221
Communication dans un congrès
lirmm-00371377
v1
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Comprehensive Bridging Fault Diagnosis based on the SLAT ParadigmDDECS'09: 12th IEEE Symposium on Design and Diagnostics of Electronic Systems, pp.264-269
Communication dans un congrès
lirmm-00371198
v1
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Yes, we Can Improve SoC YieldPRIME 2009 - Ph.D. Research in Microelectronics and Electronics, Jul 2009, Cork, Ireland. pp.272-275, ⟨10.1109/RME.2009.5201370⟩
Communication dans un congrès
lirmm-00433763
v1
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A New Design-for-Test Technique for SRAM Core-Cell Stability FaultsDATE: Design, Automation and Test in Europe, Apr 2009, Nice, France. pp.1344-1348, ⟨10.1109/DATE.2009.5090873⟩
Communication dans un congrès
lirmm-00371374
v1
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Trade-off Between Power Dissipation and Delay Fault Coverage For LOS and LOC Testing SchemesImpact of Low-Power Design on Test and Reliability, Spain
Communication dans un congrès
lirmm-00435005
v1
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Using TMR Architectures for SoC Yield ImprovementVALID'09: The First International Conference on Advances in System Testing and Validation Lifecycle, 2009, Porto, Portugal. pp.155-160
Communication dans un congrès
lirmm-00406967
v1
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A Case Study on Logic Diagnosis for System-on-ChipISQED 2009 - 10th International Symposium on Quality Electronic Design, Mar 2009, San Jose, CA, United States. pp.253-260, ⟨10.1109/ISQED.2009.4810303⟩
Communication dans un congrès
lirmm-00370646
v1
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Using TMR Architectures for Yield ImprovementDFT'08: 23rd IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, Oct 2008, pp.007-015
Communication dans un congrès
lirmm-00326901
v1
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Improved Diagnosis Resolution without Physical InformationDELTA'08: International Symposium on Electronic Design, Test & Applications, Jan 2008, pp.210-215
Communication dans un congrès
lirmm-00260961
v1
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A History-Based Technique for Faults Diagnosis in SRAMsColloque GDR SoC-SiP, France
Communication dans un congrès
lirmm-00341821
v1
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A Signature-based Approach for Diagnosis of Dynamic Faults in SRAMsDTIS: Design and Technology of Integrated Systems in Nanoscale Era, Mar 2008, Tunis, Tunisia. pp.001-006, ⟨10.1109/DTIS.2008.4540243⟩
Communication dans un congrès
lirmm-00324143
v1
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Impact of Technology Scaling on Defects and Parameter Deviations in Embedded SRAMsVLSI Test Symposium, Apr 2008, San Diego, California, United States. pp.336
Communication dans un congrès
lirmm-00324151
v1
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Tolérer Plus pour Fabriquer PlusColloque GDR SoC-SiP, 2008, Paris, France
Communication dans un congrès
lirmm-00341812
v1
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An SRAM Design-for-Diagnosis Solution Based on Write Driver Voltage SensingVTS'08: VLSI Test Symposium, May 2008, San Diego, CA, USA, pp.89-94
Communication dans un congrès
lirmm-00281558
v1
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A Design-for-Diagnosis Technique for SRAM Write DriversDATE: Design, Automation and Test in Europe, Mar 2008, Munich, Germany. pp.1480-1485, ⟨10.1109/DATE.2008.4484883⟩
Communication dans un congrès
lirmm-00341796
v1
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Yield Improvement, Fault-Tolerance to the Rescue?IOLTS: International On-Line Testing Symposium, Jul 2008, Rhodes, Greece. pp.165-170, ⟨10.1109/IOLTS.2008.10⟩
Communication dans un congrès
lirmm-00303400
v1
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Améliorer le rendement grâce aux structures tolérantes aux fautesJournées des Doctorants de l'Ecole Doctorale I2S, France
Communication dans un congrès
lirmm-00341806
v1
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Utilisation de structures tolérantes aux fautes pour augmenter le rendementJNRDM 2008 - 11e Journées Nationales du Réseau Doctoral de Microélectronique, May 2008, Bordeaux, France
Communication dans un congrès
lirmm-00341811
v1
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A History-Based Diagnosis Technique for Static and Dynamic Faults in SRAMsITC'2008: International Test Conference, Oct 2008, Santa Clara, CA, United States. pp.1-10, ⟨10.1109/TEST.2008.4700555⟩
Communication dans un congrès
lirmm-00341798
v1
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Resistive-Open Defect Influences in SRAM I/O CircuitryColloque du GDR SoC-SiP, Jun 2007, Paris, France
Communication dans un congrès
lirmm-00194282
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Test des Mémoires Flash Embarquées : Analyse de la perturbation entre cellules FloTOx voisines durant une phase de programmationJournées Nationales du Réseau Doctoral de Microélectronique, France
Communication dans un congrès
lirmm-00194274
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Embedded Flash TestingColloque du GDR SoC-SiP, Jun 2007, Paris, France
Communication dans un congrès
lirmm-00194277
v1
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Electrical Simulation Model of the 2T-FLOTOX Core-Cell for Defect Injection and Faulty Behavior Prediction in eFlash MemoriesETS: European Test Symposium, May 2007, Freiburg, Germany. pp.77-82, ⟨10.1109/ETS.2007.20⟩
Communication dans un congrès
lirmm-00158543
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Méthode de diagnostic unifiée pour circuits intégrés numériquesColloque du GDR SoC-SiP, Jun 2007, Paris, France
Communication dans un congrès
lirmm-00194285
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A Mixed Approach for Unified Logic DiagnosisDDECS'07: IEEE Design and Diagnostics of Electronic Circuits and Systems, Apr 2007, Krakow, Poland, pp.239-242
Communication dans un congrès
lirmm-00161643
v1
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Un-Restored Destructive Write Faults due to Resistive-Open Defects in the Write Driver of SRAMsVTS 2007 - 25th IEEE VLSI Test Symposium, May 2007, Berkeley, CA, United States. pp.361-366, ⟨10.1109/VTS.2007.84⟩
Communication dans un congrès
lirmm-00155979
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A Concurrent Approach for Testing Address Decoder Faults in eFlash MemoriesITC'07: International Test Conference, paper 3.2
Communication dans un congrès
lirmm-00194260
v1
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Influence of Threshold Voltage Deviations on 90nm SRAM Core-Cell BehaviorATS 2007 - 16th IEEE Asian Test Symposium, Oct 2007, Beijing, China. pp.501-504, ⟨10.1109/ATS.2007.121⟩
Communication dans un congrès
lirmm-00179276
v1
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Dynamic Two-Cell Incorrect Read Fault due to Resistive-Open Defects in the Sense Amplifiers of SRAMsETS: European Test Symposium, May 2007, Freiburg, Germany. pp.97-104, ⟨10.1109/ETS.2007.19⟩
Communication dans un congrès
lirmm-00158116
v1
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Slow Write Driver Faults in 65nm SRAM Technology: Analysis and March Test SolutionDATE: Design, Automation and Test in Europe, Apr 2007, Nice, France. pp.528-533, ⟨10.1109/DATE.2007.364647⟩
Communication dans un congrès
lirmm-00187037
v1
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DERRIC: A Tool for Unified Logic DiagnosisETS: European Test Symposium, May 2007, Freiburg, Germany. pp.13-18, ⟨10.1109/ETS.2007.16⟩
Communication dans un congrès
lirmm-00155993
v1
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Retention and Reliability Problems in Embedded Flash Memories: Analysis and Test of Defective 2T-FLOTOX Tunnel WindowVTS'07: 25th IEEE VLSI Test Symposium, May 2007, Berkeley, CA (USA), pp.47-52
Communication dans un congrès
lirmm-00151034
v1
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Fast Bridging Fault Diagnosis using Logic InformationATS: Asian Test Symposium, Oct 2007, Beijing, China. pp.33-38
Communication dans un congrès
lirmm-00179259
v1
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Test et testabilité de structures numériques tolérantes aux fautesColloque du GDR SoC-SiP, Jun 2007, Paris, France
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v1
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Structural-Based Power-Aware Assignment of Don't Cares for Peak Power Reduction during Scan TestingVLSI-SOC'06: 14th IFIP WG 10.5 International Conference on Very Large Scale Integration and System-on-Chip, Oct 2006, Nice (France), pp.403-408
Communication dans un congrès
lirmm-00108141
v1
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Méthode unifiée de diagnostic ciblant l'ensemble des modèles de fautesJNRDM: Journées Nationales du Réseau Doctoral de Microélectronique, May 2006, Rennes, France
Communication dans un congrès
lirmm-00136841
v1
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Diagnostic Multi-Modèles des Circuits LogiquesMAJECSTIC'06: Manifestation des Jeunes Chercheurs STIC, Nov 2006, Lorient, France
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v1
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Unified Diagnostic Method Targeting Several Fault ModelsVLSI-SOC'06: 14th IFIP WG 10.5 International Conference on Very Large Scale Integration and System-on-Chip, Oct 2006, Nice, pp.53-55
Communication dans un congrès
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Unified Framework for Logic DiagnosisEWDTW: East-West Design & Test Workshop, Sep 2006, Sochi, Russia. pp.47-52
Communication dans un congrès
lirmm-00096211
v1
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March Pre: an Efficient Test for Resistive-Open Defects in the SRAM Pre-charge CircuitDDECS'06: Design and Diagnostics of Electronic Circuits and Systems, Apr 2006, Prague, République Tchèque, pp.256-261
Communication dans un congrès
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Power-Aware Test Data Compression for Embedded IP CoreATS 2006 - 15th IEEE Asian Test Symposium, Nov 2006, Fukuoka, Japan. pp.5-10, ⟨10.1109/ATS.2006.66⟩
Communication dans un congrès
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Technique Structurelle d'Affectation des Bits Non Spécifiés en Vue d'une Réduction de la Puissance de Pic Pendant le Test SérieJNRDM: Journées Nationales du Réseau Doctoral de Microélectronique, May 2006, Rennes, France
Communication dans un congrès
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Embedded Flash Testing: Overview and PerspectivesDTIS: Design and Technology of Integrated Systems in Nanoscale Era, Sep 2006, Tunis, Tunisia. pp.210-215
Communication dans un congrès
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Low Power TestingWRTLT'06: 7th Workshop on RTL and High Level Testing, Nov 2006, Fukuoka, pp.4
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Minimizing Peak Power Consumption during Scan Testing: Structural Technique for Don't Care Bits AssignmentPRIME'06: Conference on Ph.D. Research in Microelectronics and Electronics, Jun 2006, Otranto, Italy, pp.65-68
Communication dans un congrès
lirmm-00137614
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An Overview of Failure Mechanisms in Embedded Flash MemoriesVTS'06: VLSI Test Symposium, Apr 2006, Berkeley, CA, United States. pp.108-113
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lirmm-00102761
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Minimizing Peak Power Consumption during Scan Testing: Test Pattern Modification with X Filling HeuristicsDTIS: Design and Technology of Integrated Systems in Nanoscale Era, Sep 2006, Tunis, Tunisia. pp.359-364
Communication dans un congrès
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Efficient Test of Dynamic Read Destructive Faults in SRAM MemoriesLATW: Latin American Test Workshop, Mar 2005, Salvador, Bahia, Brazil. pp.40-45
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v1
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Resistive-Open Defect Influence in SRAM Pre-Charge Circuits: Analysis and CharacterizationETS: European Test Symposium, May 2005, Tallinn, Estonia. pp.116-121, ⟨10.1109/ETS.2005.33⟩
Communication dans un congrès
lirmm-00106010
v1
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Resistive-Open Defect Injection in SRAM Core-Cell: Analysis and Comparison Between 0.13 um and 90 nm TechnologiesDAC: Design Automation Conference, Jun 2005, Anaheim, CA, United States. pp.857-862
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Peak Power Consumption During Scan Testing: Issue, Analysis and Heuristic SolutionDDECS'05: IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, Apr 2005, Sopron, Hungary. pp.151-159
Communication dans un congrès
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Data Retention Fault in SRAM Memories: Analysis and Detection ProceduresVTS 2005 - 23rd IEEE VLSI Test Symposium, May 2005, Palm Springs, CA, United States. pp.183-188, ⟨10.1109/VTS.2005.37⟩
Communication dans un congrès
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Analyse et Réduction de la Puissance de Pic durant le Test SérieJNRDM 2005 - 8e Journées Nationales du Réseau Doctoral de Microélectronique, May 2005, Paris, France
Communication dans un congrès
lirmm-00106528
v1
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Controlling Peak Power Consumption During Scan Testing: Power-Aware DfT and Test Set PerspectivesPATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 2005, Leuven, Belgium. pp.540-549, ⟨10.1007/11556930_55⟩
Communication dans un congrès
istex
lirmm-00106111
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Power-Aware Scan Testing for Peak Power ReductionVLSI-SOC'05: IFIP International Conference on Very Large Scale Integration, Oct 2005, Perth, Australia. pp.441-446
Communication dans un congrès
lirmm-00106112
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Resistive-Open Defect Injection in SRAM Core-Cell: Analysis and Comparison between 0.13μm and 90nm TechnologiesDAC: Design Automation Conference, May 2005, Anaheim, CA, United States. pp.857-862, ⟨10.1145/1065579.1065804⟩
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lirmm-00106558
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Incidence des Défauts Résistifs dans les Circuits de Précharge des Mémoires SRAMJNRDM 2005 - 8e Journées Nationales du Réseau Doctoral de Microélectronique, May 2005, Paris, France
Communication dans un congrès
lirmm-00106529
v1
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March Tests Improvements for Address Decoder Open and Resistive Open Fault DetectionLATW: Latin American Test Workshop, Mar 2004, Cartagena, Colombia. pp.31-36
Communication dans un congrès
lirmm-00108642
v1
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Resistive-Open Defects in Embedded-SRAM Core Cells: Analysis and March Test SolutionATS: Asian Test Symposium, Nov 2004, Kenting, Taiwan. pp.266-271
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lirmm-00108800
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Dynamic Read Destructive Faults in Embedded-SRAMs: Analysis and March Test SolutionETS: European Test Symposium, May 2004, Ajaccio, Corsica, France. pp.140-145
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lirmm-00108795
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March iC-: An Improved Version of March C- for ADOFs DetectionVTS: VLSI Test Symposium, Apr 2004, Napa Valley, CA, United States. pp.129-134, ⟨10.1109/VTEST.2004.1299236⟩
Communication dans un congrès
lirmm-00108772
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Design of Routing-Constrained Low Power Scan ChainsDATE: Design, Automation and Test in Europe, Feb 2004, Paris, France. pp.62-67, ⟨10.1109/DATE.2004.1268828⟩
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lirmm-00108836
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Test March pour la Détection des Fautes Dynamiques dans les Décodeurs de Mémoires SRAMJNRDM'04 : 7ièmes Journées Nationales du Réseau Doctoral de Microélectronique, May 2004, Marseille, France. pp.495-497
Communication dans un congrès
lirmm-00108644
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Design of Routing-Constrained Low Power Scan ChainsDELTA: Electronic Design, Test and Applications, Jan 2004, Perth, Australia. pp.287-292, ⟨10.1109/DELTA.2004.10009⟩
Communication dans un congrès
lirmm-00108833
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Comparison of open and resistive-open defect test conditions in SRAM address decodersATS: Asian Test Symposium, Nov 2003, Xian, China. pp.250-255, ⟨10.1109/ATS.2003.1250818⟩
Communication dans un congrès
lirmm-01238821
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Defect-Oriented Dynamic Fault Models for Embedded-SRAMsETW: European Test Workshop, May 2003, Maastricht, Netherlands. pp.23-28
Communication dans un congrès
lirmm-00269526
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On Using Efficient Test Sequences for BISTVTS: VLSI Test Symposium, 2002, Monterey, CA, United States. pp.145-150
Communication dans un congrès
lirmm-00268499
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Test Intégré de Circuits Digitaux : Comparaison de deux types de Séquences de TestJournées des Doctorants, École Doctorale I2S, 2001, Montpellier, France. pp.158-160
Communication dans un congrès
lirmm-00345806
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On Hardware Generation of Random Single Input Change TestETW: European Test Workshop, May 2001, Saltsjöbaden, Sweden. pp.117-123
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lirmm-00345801
v1
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Test Intégré de Circuits Digitaux : Etude Comparative de l'Efficacité de deux types de Séquences de TestJNRDM: Journées Nationales du Réseau Doctoral de Microélectronique, LIRMM; CEM2, May 2000, Montpellier, France. pp.86-87
Communication dans un congrès
lirmm-00345804
v1
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Comparison between Random and Pseudo-Random Generation for BIST of Delay, Stuck-at and Bridging FaultsIOLTW: International On-Line Testing Workshop, Jul 2000, Palma de Mallorca, Spain. pp.121-161, ⟨10.1109/OLT.2000.856623⟩
Communication dans un congrès
lirmm-00345800
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Delay Fault Testing: Choosing Between Random SIC and Random MIC Test SequencesETW: European Test Workshop, May 2000, Cascais, Portugal. pp.09-14, ⟨10.1109/ETW.2000.873772⟩
Communication dans un congrès
lirmm-00345799
v1
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Analyse des capacités de test de générateurs intégrés produisant des vecteurs adjacentsColloque CAO de Circuits Intégrés et Systèmes, France. pp.88-91
Communication dans un congrès
lirmm-00345803
v1
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A BIST Structure to Test Delay Faults in a Scan EnvironmentATS: Asian Test Symposium, Dec 1998, Singapore, Singapore. pp.435-439
Communication dans un congrès
lirmm-00345798
v1
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Sécurité et intégrité dans un Contexte Embarqué15e Colloque National du GDR SoC², Jun 2021, Rennes, France
Poster de conférence
lirmm-03361957
v1
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An Advanced Diagnosis Flow for SRAMs11e Colloque National du GDR SoC/SiP, Jun 2017, Bordeaux, France. 2017
Poster de conférence
lirmm-01718611
v1
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Fault-Effect Propagation Based Intra-cell Scan Chain DiagnosisColloque GDR SoC-SiP, Jun 2013, Lyon, France. 2013
Poster de conférence
lirmm-00839113
v1
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Performance Evaluation of Capacitive defects on TAS-MRAMsColloque GDR SoC-SiP, 2013, Lyon, France. 2013
Poster de conférence
lirmm-00839093
v1
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Investigating Multiple-Cell-Upsets on a 90mn SRAMColloque GDR SoC-SiP, 2013, Lyon, France. 2013
Poster de conférence
lirmm-00839108
v1
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Coupling-Based Resistive-Open Defects in TAS-MRAM ArchitecturesETS: European Test Symposium, May 2012, Annecy, France. Test Symposium (ETS), 2012 17th IEEE European, 2012, ⟨10.1109/ETS.2012.6233034⟩
Poster de conférence
lirmm-00806793
v1
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Resistive Open Defect Analysis for Through-Silicon-ViasETS: European Test Symposium, May 2012, Annecy, France. 17th IEEE European Test Symposium, pp.183, 2012
Poster de conférence
lirmm-00806795
v1
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Parity Prediction Synthesis for Nano-Electronic Gate DesignsITC'2010: International Test Conference, Nov 2010, Austin, Texas, United States. pp.N/A, 2010
Poster de conférence
lirmm-00537938
v1
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Is Test Power Reduction Through X-Filling Good Enough?ITC'2010: International Test Conference, Nov 2010, Austin, Texas, United States. 2010
Poster de conférence
lirmm-00537926
v1
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SoC Yield Improvement for Future Nanoscale TechnologiesETS 2009 - 14th IEEE European Test Symposium | PhD Forum, May 2009, Sevilla, Spain. 2009
Poster de conférence
lirmm-00433798
v1
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Analysis of Resistive-Bridging Defects in SRAM Core-Cell: Impact within the Core-Cell and in the Memory ArrayETS: European Test Symposium, May 2009, Sevilla, Spain. 14th IEEE European Test Symposium, 2009
Poster de conférence
lirmm-00433796
v1
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A Logic Diagnosis Approach for Sequential CircuitsETS 2009 - 14th IEEE European Test Symposium, May 2009, Sevilla, Spain. , 2009, Ph. D. Forum
Poster de conférence
lirmm-00433792
v1
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NAND Flash Testing: A Preliminary Study on Actual DefectsITC: International Test Conference, Nov 2009, Austin, TX, United States. 2009, ⟨10.1109/TEST.2009.5355898⟩
Poster de conférence
lirmm-00433765
v1
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SRAM Core-cell Quality MetricsGDR SOC SIP, France. 2009
Poster de conférence
lirmm-00434962
v1
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Trade-off Between Power Dissipation and Delay Fault Coverage for LOS and LOC Testing SchemesGDR SOC SIP, France. 2009
Poster de conférence
lirmm-00434959
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Test des Mémoires FLASH NANDColloque GDR SoC-SiP, France. 2009
Poster de conférence
lirmm-00433770
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SoC Yield Improvement: Redundant Architectures to the RescueITC'2008: International Test Conference, Oct 2008, Santa Clara, CA, United States. IEEE, pp.7, 2008
Poster de conférence
lirmm-00341799
v1
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Failure Mechanisms due to Process Variations in Nanoscale SRAM Core-CellsETS: European Test Symposium, May 2006, Southampton, United Kingdom. 11th IEEE European Test Symposium, 2006
Poster de conférence
lirmm-00134787
v1
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Structural Power-Aware Assignment of Xs for Peak Power Reduction during Scan TestingETS: European Test Symposium, May 2006, Southampton, United Kingdom. 11th IEEE European Test Symposium, 2006
Poster de conférence
lirmm-00134781
v1
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Advanced Test Methods for SRAMs - Effective Solutions for Dynamic Fault Detection in Nanoscaled TechnologiesSpringer, 171 p., 2009, 978-1-4419-0937-4
Ouvrages
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Machine Learning Support for Cell-aware DiagnosisMachine Learning Support for Fault Diagnosis of System-on-Chip, Springer, pp.173-204, 2023, ISBN 978-3-031-19638-6 ISBN 978-3-031-19639-3 (eBook). ⟨10.1007/978-3-031-19639-3_6⟩
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Defect Diagnosis Techniques for Silicon Customer ReturnsFrontiers of Quality Electronic Design (QED), Springer International Publishing, pp.641-676, 2023, 978-3-031-16344-9. ⟨10.1007/978-3-031-16344-9_17⟩
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Cell-Aware Model Generation Using Machine LearningFrontiers of Quality Electronic Design (QED), Springer International Publishing, pp.227-257, 2023, 978-3-031-16344-9. ⟨10.1007/978-3-031-16344-9_6⟩
Chapitre d'ouvrage
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Test and Reliability of Approximate HardwareApproximate Computing, Springer International Publishing, pp.233-266, 2022, ⟨10.1007/978-3-030-98347-5_10⟩
Chapitre d'ouvrage
hal-03888016
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Design, Verification, Test, and In-Field Implications of Approximate Digital Integrated CircuitsApproximate Computing Techniques, Springer International Publishing, pp.349-385, 2022, ⟨10.1007/978-3-030-94705-7_12⟩
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Electromigration Alleviation Techniques for 3D Integrated CircuitsChao Wang. High Performance Computing for Big Data: Methodologies and Applications, CRC Press, pp.37-58, 2017, 9781498783996
Chapitre d'ouvrage
lirmm-01800220
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Scan Cell Reordering for Peak Power Reduction during Scan Test CyclesVLSI-Soc: From Systems to Silicon, pp.267-281, 2007, 978-0-387-73661-7
Chapitre d'ouvrage
lirmm-00194261
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Random Adjacent Sequences: An Efficient Solution for Logic BISTSOC Design Methodologies, 90, Kluwer, pp.413-424, 2002, IFIP — The International Federation for Information Processing, 978-1-4757-6530-4. ⟨10.1007/978-0-387-35597-9_35⟩
Chapitre d'ouvrage
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An Advanced Diagnosis Flow using CustomSim for SRAMs2017
Autre publication scientifique
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Contribution au test et à la fiabilité des systèmes sur puceMicro et nanotechnologies/Microélectronique. Université Montpellier 2, 2014
HDR
tel-01420363
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