HASSAN AZIZA
Présentation
Publications
Publications
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Analysis of Conductance Variability in RRAM for Accurate Neuromorphic Computing25th IEEE Latin-American Test Symposium, Apr 2024, Maceio, Brazil |
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Circuit-level evaluation of a new zero-cost transistor in a embedded non-volatile memory CMOS technology2021 16th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS), Jun 2021, Montpellier, France. pp.1-5, ⟨10.1109/DTIS53253.2021.9505137⟩ |
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Investigation of Single Event Effects in a Resistive RAM memory array by SPICE level simulation2021 IEEE 22nd Latin American Test Symposium (LATS), Oct 2021, Punta del Este, Uruguay. ⟨10.1109/LATS53581.2021.9651871⟩ |
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Intermittent Undefined State Fault in RRAMs2021 IEEE European Test Symposium (ETS), May 2021, Bruges, France. pp.1-6, ⟨10.1109/ETS50041.2021.9465401⟩ |
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Benchmarking and optimization of trench-based multi-gate transistors in a 40 nm non-volatile memory technology2021 16th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS), Jun 2021, Montpellier, France. pp.1-4, ⟨10.1109/DTIS53253.2021.9505093⟩ |
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Design Considerations Towards Zero-Variability Resistive RAMs in HRS State2021 IEEE 22nd Latin American Test Symposium (LATS), Oct 2021, Punta del Este, France. pp.1-5, ⟨10.1109/LATS53581.2021.9651758⟩ |
Tutorial: Silicon Systems for Wireless LAN2021 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), Apr 2021, Vienna, Austria. pp.157-158, ⟨10.1109/DDECS52668.2021.9417056⟩ |
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A CMOS OxRAM-Based Neuron Circuit Hardened with Enclosed Layout Transistors for Aerospace ApplicationsIOLTS 2020 - 26th IEEE International Symposium on On-Line Testing and Robust System Design, Jul 2020, Napoli, Italy. pp.1-6, ⟨10.1109/IOLTS50870.2020.9159709⟩ |
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A Lightweight Reconfigurable RRAM-based PUF for Highly Secure Applications2020 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), Oct 2020, Frascati, Italy. ⟨10.1109/DFT50435.2020.9250829⟩ |
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Resistive RAM SET and RESET Switching Voltage Evaluation as an Entropy Source for Random Number Generation2020 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), Oct 2020, Frascati, Italy. pp.1-4, ⟨10.1109/DFT50435.2020.9250726⟩ |
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Design of a Novel Hybrid CMOS Non-Volatile SRAM Memory in 130nm RRAM TechnologyDesign, Technology, and Test of Integrated Circuits and Systems, Apr 2020, virtual, Morocco. ⟨10.1109/DTIS48698.2020.9081153⟩ |
A Capacitor-Less CMOS Neuron Circuit for Neuromemristive NetworksNEWCAS 2019 - 17th IEEE International Conference on Electronics Circuits and Systems, Jun 2019, Munich, Germany. ⟨10.1109/NEWCAS44328.2019.8961278⟩ |
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An Augmented OxRAM Synapse for Spiking Neural Network (SNN) Circuits2019 14th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS), Apr 2019, Mykonos, France. ⟨10.1109/DTIS.2019.8735057⟩ |
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Device-Aware Test: A New Test Approach Towards DPPB Level2019 IEEE International Test Conference (ITC), Nov 2019, Washington, United States. pp.1-10, ⟨10.1109/ITC44170.2019.9000134⟩ |
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True random number generation exploiting SET voltage variability in resistive RAM memory arrays2019 19th Non-Volatile Memory Technology Symposium (NVMTS), Oct 2019, Durham, France. pp.1-5, ⟨10.1109/NVMTS47818.2019.9043369⟩ |
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A configurable operational amplifier based on oxide resistive RAMs2018 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS), Apr 2018, Taormina, France. pp.1-2, ⟨10.1109/DTIS.2018.8368572⟩ |
Using short-term fourier transform for particle detection and recognition in a CMOS oscillator-based chain2018 IEEE 19th Latin-American Test Symposium (LATS), Mar 2018, Sao Paulo, France. pp.1-5, ⟨10.1109/LATW.2018.8349684⟩ |
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Memristor models optimization for large-scale 1T1R memory arrays2018 International Conference on IC Design & Technology (ICICDT), Jun 2018, Otranto, France. pp.109-112, ⟨10.1109/ICICDT.2018.8399768⟩ |
High voltage recycling scheme to improve power consumption of regulated charge pumps2017 27th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS), Sep 2017, Thessaloniki, Greece. ⟨10.1109/PATMOS.2017.8106995⟩ |
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An Ultra-Low Power and High Speed Single Ended Sense Amplifier for Non-Volatile Memories2017 New Generation of CAS (NGCAS), Sep 2017, Genova, Italy. ⟨10.1109/NGCAS.2017.33⟩ |
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ReRAM ON/OFF resistance ratio degradation due to line resistance combined with device variability in 28nm FDSOI technology2017 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS), Apr 2017, Athens, Greece. ⟨10.1109/ULIS.2017.7962594⟩ |
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Oxide-based RRAM Models for Circuit Designers: A Comparative Analysis2017 12TH IEEE INTERNATIONAL CONFERENCE ON DESIGN & TECHNOLOGY OF INTEGRATED SYSTEMS IN NANOSCALE ERA (DTIS 2017), 2017, Unknown, Unknown Region |
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Power efficiency optimization of charge pumps in embedded low voltage NOR flash memory2017 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC), Oct 2017, Linkoping, Sweden. ⟨10.1109/NORCHIP.2017.8124949⟩ |
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Resistive RAM Variability Monitoring using a Ring Oscillator based Test Chip27th European Symposium on Reliability of Electron Devices, Failure Physics and Analysis (ESREF 2016), Sep 2016, Halle, Germany |
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Multilevel Operation in Oxide Based Resistive RAM with SET voltage modulation2016 11TH IEEE INTERNATIONAL CONFERENCE ON DESIGN & TECHNOLOGY OF INTEGRATED SYSTEMS IN NANOSCALE ERA (DTIS), Apr 2016, Istanbul, Turkey. pp.1-5, ⟨10.1109/DTIS.2016.7483892⟩ |
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Ultra Low Power Charge Pump with Multi-Step Charging and Charge Sharing2016 IEEE 8TH INTERNATIONAL MEMORY WORKSHOP (IMW), 2016, Unknown, Unknown Region |
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Impact of Resistive Paths on NVM Array Reliability: Application to Flash & ReRAM Memories27th European Symposium on Reliability of Electron Devices, Failure Physics and Analysis (ESREF 2016), Sep 2016, Halle, Germany |
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Comparison of a readout chain dedicated to the signal conditioning of a particle detector and an innovative chain based on a VCO concept15. European Conference on Radiation and Its Effects on Components and Systems (Radecs), Sep 2015, Moscou, Russia |
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Low cost built-in-tuning of on-chip passive filters for low-if double quadrature rf receiver2015 16th Latin-American Test Symposium (LATS), Mar 2015, Puerto Vallarta, France. ⟨10.1109/LATW.2015.7102501⟩ |
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Improvement of a detection chain based on a VCO concept for microelectronic reliability under natural radiative environment16. Latin-American Test Symposium (LATS)), Mar 2015, Puerto Vallarta, Mexico |
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Development of a CMOS oscillator chain for particle detection based on SOI technology2015 4th International Conference on Advancements in Nuclear Instrumentation Measurement Methods and their Applications (ANIMMA), Apr 2015, Lisbon, France. pp.1-5 |
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Improvement of a VCO concept for low energy particule detection and recognition15th Latin American Test Workshop (LATW), IEEE., Mar 2014, Fortaleza, Brazil |
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Oxide based resistive RAM: ON/OFF resistance analysis versus circuit variability2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), Oct 2014, Amsterdam, Netherlands. ⟨10.1109/DFT.2014.6962107⟩ |
SPICE level analysis of Single Event Effects in an OxRRAM cell2013 14th Latin American Test Workshop - LATW, Apr 2013, Cordoba, France. ⟨10.1109/LATW.2013.6562684⟩ |
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Single-ended sense amplifier robustness evaluation for OxRRAM technology2013 IEEE Design and Test Symposium (IDT), Dec 2013, Marrakesh, Morocco. ⟨10.1109/IDT.2013.6727097⟩ |
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Built-in tuning of the local oscillator for open loop modulation of low cost, low power RF transceiver2013 14th Latin American Test Workshop - LATW, Apr 2013, Cordoba, Argentina. ⟨10.1109/LATW.2013.6562686⟩ |
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Analytical study of complementary memristive synchronous logic gates2013 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH), Jul 2013, Brooklyn, United States. ⟨10.1109/NanoArch.2013.6623047⟩ |
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A Built-In Self-Test Structure (BIST) for Resistive RAMs Characterization: Application to Bipolar OxRRAMsInternational Semiconductor Device Research Symposium, Dec 2013, Bethesda, United States |
On the investigation of built-in tuning of RF receivers using on-chip polyphase filters2013 IEEE 31st VLSI Test Symposium (VTS), Apr 2013, Berkeley, United States. ⟨10.1109/VTS.2013.6548932⟩ |
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Analytical study of complementary memristive synchronous logic gates2013 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH), Jul 2013, Brooklyn, France. ⟨10.1109/NanoArch.2013.6623047⟩ |
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Synchronous Full-Adder based on Complementary Resistive Switching Memory Cells11th International New Circuits and Systems Conference (NEWCAS), Jun 2013, Paris, France. ⟨10.1109/NEWCAS.2013.6573578⟩ |
Built-in tuning of RFIC Passive Polyphase Filter by process and thermal monitoring2012 13th Latin American Test Workshop - LATW, Apr 2012, Quito, France. pp.1-5 |
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SITARe: A simulation tool for analysis and diagnosis of radiation effects2012 13th Latin American Test Workshop - LATW, Apr 2012, Quito, France. pp.1-5 |
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Built-in Tunning of RFIC Passive Polyphase Filter by Process and Thermal MonitoringIEEE Latin-American Test Workshop LATW, Apr 2012, Quito, Ecuador |
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Crossbar architecture based on 2R complementary resistive switching memory cell2012 IEEE/ACM International Symposium on Nanoscale Architectures , Jul 2012, Amsterdam, Netherlands. ⟨10.1145/2765491.2765508⟩ |
Investigation of a CMOS oscillator concept for particle detection and diagnosis2012 13th Latin American Test Workshop - LATW, Apr 2012, Quito, France. pp.1-5 |
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Analysis of SEU parameters for the study of SRAM cells reliability under radiation2011 12th Latin American Test Workshop - LATW, Mar 2011, Beach of Porto de Galinhas, France. pp.1-5 |
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Contribution to SER prediction: A new metric based on RC transient simulations2011 12th European Conference on Radiation and Its Effects on Components and Systems (RADECS), Sep 2011, Sevilla, France. pp.103-108 |
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Using design of experiment to diagnose analog blocks geometrical defects: Application to current reference circuitsTechnology of Integrated Systems in Nanoscale Era (DTIS), Apr 2011, Athens, France. pp.1-5 |
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Impact of SEU configurations on a SRAM cell response at circuit level2011 12th Latin American Test Workshop - LATW, Mar 2011, Beach of Porto de Galinhas, France. pp.1-5 |
Embedded Memory TestSilicon Systems for Wireless LAN, World Scientific, pp.387-404, 2020, ⟨10.1142/9789811210723_0015⟩ |
Resistive random memory architecture with high integration density and control method thereofFrance, Patent n° : WO2021191362A1. 2021 |
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French Tech LAB Grant Proposal: The SMILE Startup Project (Pôles Universitaires d’Innovation - PUI)2024 |
Système multi-capteurs offrant une auto-calibration dynamique pour l’analyse des émissions de GES en temps réel2023 |
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Monitoring urban chemistry at the street corner: the SMILE startup project2022 |
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METHODOLOGIE DE DIAGNOSTIC ET TECHNIQUES DE TEST POUR LES MEMOIRES NON VOLATILES DE TYPE EEPROMMicro et nanotechnologies/Microélectronique. Aix-Marseille Université (AMU), 2004. Français. ⟨NNT : ⟩ |
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METHODOLOGIES DE TEST DEIEES AUX MEMOIRES EMBARQUEESMicro et nanotechnologies/Microélectronique. Aix Marseille Université (AMU), 2012 |