Bertrand Le Gal
Maître de conférences à l'ENSEIRB-MATMECA et chercheur au laboratoire IMS (UMR CNRS 5218)
144
Documents
Publications
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Implantation d'un détecteur de préambules vobulés par satellite en orbite basseGretsi 2023 - XXIXème Colloque Francophone de Traitement du Signal et des Images, Aug 2023, Grenoble, France. pp.1-4
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Efficient LoRa-like Transmitter Stacks for SDR ApplicationsIEEE International Conference on Electronics, Circuits and Systems (ICECS), Oct 2022, Glasgow, United Kingdom. pp.1-4, ⟨10.1109/ICECS202256217.2022.9971030⟩
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High-throughput FFT architectures using HLS tools2022 29th IEEE International Conference on Electronics, Circuits and Systems (ICECS), Oct 2022, Glasgow, United Kingdom. pp.1-4, ⟨10.1109/ICECS202256217.2022.9970886⟩
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Conception d’architectures de FFT pour FPGA à base de modèles comportementauxConférence francophone d'informatique en Parallélisme, Architecture et Système (COMPAS 2022), Jul 2022, Amiens, France
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Architecture matérielle programmable optimisée pour les systèmes de communications numériquesConférence francophone d'informatique en Parallélisme, Architecture et Système, Jul 2021, Lyon, France
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Generation of efficient self-adaptive hardware polar decoders using high-level synthesisIEEE International Workshop on Signal Processing Systems (SIPS), Oct 2019, Nanjing, China
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High data rate and flexible hardware QC-LDPC decoder for satellite optical communications2018 IEEE 10th International Symposium on Turbo Codes & Iterative Information Processing (ISTC), Dec 2018, Hong Kong, China. pp.1-5
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From multicore LDPC decoder implementations to FPGA decoder architectures: a case study2018 25th IEEE International Conference on Electronics, Circuits and Systems (ICECS), Dec 2018, Bordeaux, France. pp.89-92
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A scalable and efficient digital signal processing system for real time biological spike detection2018 25th IEEE International Conference on Electronics, Circuits and Systems (ICECS), Dec 2018, Bordeaux, France. pp.697-700
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Hardware design of Euclidean Projection modules for ADMM LDPC decoding2018 25th IEEE International Conference on Electronics, Circuits and Systems (ICECS), Dec 2018, Bordeaux, France. pp.73-76
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Implementation aspects of a pipeline ADMM-based LP decoding of LDPC convolutional codesIEEE Wireless Communications and Networking Conference (WCNC), Apr 2018, Barcelona, France. pp.1-6
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Fast Design of Reliable, Flexible and High-Speed AWGN architectures with High Level Synthesis2018 25th IEEE International Conference on Electronics, Circuits and Systems (ICECS), Dec 2018, Bordeaux, France. pp.661-664
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Model-based Design of Efficient LDPC Decoder Architectures2018 IEEE 10th International Symposium on Turbo Codes & Iterative Information Processing (ISTC), Dec 2018, Hong Kong, China. pp.1-5
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Real-Time Analysis of Living Biological Cell Activity2018 Conference on Design and Architectures for Signal and Image Processing (DASIP), Oct 2018, Porto, Portugal. pp.62-63
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ADMM hardware decoder for regular LDPC codes using a NISC-based architectureIEEE Wireless Communications and Networking Conference (WCNC), Apr 2018, Barcelona, France. pp.1-6
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Low-latency software LDPC decoders for x86 multi-core devices2017 IEEE International Workshop on Signal Processing Systems (SiPS), Oct 2017, Lorient, France. ⟨10.1109/SiPS.2017.8110001⟩
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Fast Simulation and Prototyping with AFF3CTThe 20th International Workshop on Signal Processing Systems (SiPS 2017), Oct 2017, Lorient, France. ⟨10.13140/RG.2.2.10295.42409/1⟩
Communication dans un congrès
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A survey on decoding schedules of LDPC convolutional codes and associated hardware architectures2017 IEEE Symposium on Computers and Communications (ISCC), Jul 2017, Heraklion, France. ⟨10.1109/ISCC.2017.8024640⟩
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An LP-based algorithm for decoding terminated LDPC convolutional codes2017 International Conference on Internet of Things, Embedded Systems and Communications (IINTEC), Oct 2017, Gafsa, France. pp.95-100
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Low complexity ADMM-LP based decoding strategy for LDPC convolutional codes25th International Conference on Software, Telecommunications and Computer Networks (SoftCOM), Sep 2017, Split, Croatia. ⟨10.23919/SOFTCOM.2017.8115500⟩
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Reduced complexity ADMM-based schedules for LP decoding of LDPC convolutional codes2017 IEEE International Workshop on Signal Processing Systems (SiPS), Oct 2017, Lorient, France. ⟨10.1109/SiPS.2017.8110012⟩
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Successive cancellation decoder for very long polar codes2017 IEEE International Workshop on Signal Processing Systems (SiPS), Oct 2017, Lorient, France. ⟨10.1109/SiPS.2017.8110022⟩
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Comparison of different schedulings for the ADMM based LDPC decoding2016 9th International Symposium on Turbo Codes and Iterative Information Processing (ISTC), Sep 2016, Brest, France. ⟨10.1109/ISTC.2016.7593075⟩
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Lowering the error floor of double-binary turbo codes: The flip and check algorithm2016 9th International Symposium on Turbo Codes and Iterative Information Processing (ISTC), Sep 2016, Brest, France. ⟨10.1109/ISTC.2016.7593096⟩
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Energy Consumption Analysis of Software Polar Decoders on Low Power ProcessorsThe 24nd European Signal Processing Conference (EUSIPCO 2016), Aug 2016, Budapest, Hungary. ⟨10.1109/EUSIPCO.2016.7760327⟩
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A scalable 3-phase polar decoder2016 IEEE International Symposium on Circuits and Systems (ISCAS), May 2016, Montréal, France. ⟨10.1109/ISCAS.2016.7527259⟩
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Multicore implementation of LDPC decoders based on ADMM algorithm2016 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), Mar 2016, Shanghai, China. ⟨10.1109/ICASSP.2016.7471820⟩
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Beyond Gbps Turbo Decoder on Multi-Core CPUsThe 10th International Symposium on Turbo Codes and Iterative Information Processing (ISTC 2016), Sep 2016, Brest, France. ⟨10.1109/ISTC.2016.7593092⟩
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Hardware complexity reduction of LDPC-CC decoders based on message-passing approaches2016 17th International Conference on Sciences and Techniques of Automatic Control and Computer Engineering (STA), Dec 2016, Sousse, France. ⟨10.1109/STA.2016.7952003⟩
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QBox: an industrial solution for virtual platform simulation using QEMU and SystemC TLM-2.08th European Congress on Embedded Real Time Software and Systems (ERTS 2016), Jan 2016, TOULOUSE, France
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Evaluation of the hardware complexity of the ADMM approach for LDPC decoding2016 IEEE Wireless Communications and Networking Conference (WCNC), Apr 2016, Doha, France. ⟨10.1109/WCNC.2016.7565042⟩
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Hardware architecture for lowering the error floor of LTE turbo codes2016 Conference on Design and Architectures for Signal and Image Processing (DASIP), Oct 2016, Rennes, France. ⟨10.1109/DASIP.2016.7853805⟩
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Analysis of ADMM-LP algorithm for LDPC decoding, a first step to hardware implementation2015 IEEE International Conference on Electronics, Circuits, and Systems (ICECS), Dec 2015, Cairo, Egypt. ⟨10.1109/ICECS.2015.7440322⟩
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An Efficient, Portable and Generic Library for Successive Cancellation Decoding of Polar CodesThe 28th International Workshop on Languages and Compilers for Parallel Computing (LCPC 2015), Sep 2015, Raleigh, United States. ⟨10.1007/978-3-319-29778-1_19⟩
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Study and Analysis of a New Implementation of a Mixed-Signal Cartesian Feedback for a Low Power Zero-IF WCDMA TransmitterNEWCAS, Jun 2013, PARIS, France. pp.1-4
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Improving the Performance of Message Parsers for Embedded SystemsSymposium on Applied Computing 2013, Mar 2013, Coimbra, Portugal. pp.1505
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Improving architecture efficiency of SoftCore processorsEmbedded Real Time Software and Systems (ERTS2012), Feb 2012, Toulouse, France
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New digital predistortion design based on mixed-signal cartesian feedback training for 3G homodyne transmitterInternational New Circuits and Systems Conference (NEWCAS), Jun 2012, Montréal, Canada. pp.93-96, ⟨10.1109/NEWCAS.2012.6328964⟩
Communication dans un congrès
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Cartesian Feedback with digital enhancement applied to fully integrated CMOS RF transmitterIMS2012 International Microwave Symposium, Workshop WSD: RF & mmW PAs: Linearization and Power Challenges, Jun 2012, Montreal, Canada
Communication dans un congrès
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Spatial downsizing impact in the transrating tradeoff for content/context awareness in media networkInternational Conference on Telecommunications and Multimedia (TEMU), Jul 2012, Chania, Greece. pp.158-162, ⟨10.1109/TEMU.2012.6294709⟩
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A generic video adaptation FPGA implementation towards content- and context-awareness in future networksConference on Design and Architectures for Signal and Image Processing (DASIP), Oct 2012, Karlsruhe, Germany. pp.1-7
Communication dans un congrès
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A Generic Video Adaptation Framework Towards Content - and Context - Awareness in Future NetworksEUSIPCO 2012, Aug 2012, Bucharest, Romania. pp.2218 - 2222
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Design of a Mixed-Signal Cartesian Feedback Loop for a Low Power Zero-IF WCDMA Transmitter3rd IEEE Circuits and Systems Society Latin American Symposium on Circuits and Systems (LASCAS2012), Feb 2012, Mexico. pp.4
Communication dans un congrès
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Mixed Cartesian Feedback for Zero-IF WCDMA TransmitterLASCAS 2011, Feb 2011, Bogota, Colombia. pp.1, ⟨10.1109/LASCAS.2011.5750300⟩
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A system aproach for reducing power consumption of multimedia devices with a low QoE impact2011 18th IEEE International Conference on Electronics, Circuits and Systems (ICECS), Dec 2011, Beirut, Lebanon. pp.5-8, ⟨10.1109/ICECS.2011.6122200⟩
Communication dans un congrès
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Implémentation matérielle du filtre anti-bloc pour la norme H.264/AVCGRETSI: Conférence francophone de la communauté du traitement du signal et des images, Sep 2011, Bordeaux, France
Communication dans un congrès
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Performance analysis and evaluation of Xenomai with H.264/AVC decoderICM: International Conference on Microelectronics, Dec 2011, Hammamet, Tunisia. pp 1-6
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A Reconfigurable Multi-core cryptoprocessor for Multi-channel Communication SystemsIPDPS - 25th IEEE International Parallel & Distributed Processing Symposium, May 2011, Anchorage, United States. pp.199-206
Communication dans un congrès
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Automatic HLS based Low-Cost IP Watermarking9th IEEE International NEWCAS conference 2011, Jun 2011, Bordeaux, France. pp.490-493
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An LCF-ADC Model Using Co-simulation Technique2011 International Workshop on ADC Modelling, Testing and Data Converter Analysis and Design and IEEE 2011 ADC Forum, Jun 2011, Orvieto, Italy. pp.104-108
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Assertion support in high-level synthesis design flowForum on Specification and Design Languages, Sep 2011, Oldenburg, Germany. pp.1-8
Communication dans un congrès
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Evaluation des performances de Xenomai avec un décodeur H.264/AVCColloque national du GDR SOC-SIP, Jun 2011, Lyon, France. pp 1-2
Communication dans un congrès
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Implémentation matérielle du filtre anti-bloc pour la norme H.264/AVCConférence francophone de la communauté du traitement du signal et des images, Sep 2011, France. pp 1-4
Communication dans un congrès
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Design and implementation of a multi-core crypto-processor for software defined radiosSymposium on Applied Reconfigurable Computing, Mar 2011, Belfast, United Kingdom. pp.29-40, ⟨10.1007/978-3-642-19475-7_5⟩
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Using Digital Signal Processor Singularities to Minimize ROM Based Controller Area8th IEEE International NEWCAS Conference, Jun 2010, Montréal, Canada. pp.29-32
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Reducing and Smoothing Power consumption of ROM-based Controller Implementations23rd Symposium on Integrated Circuits and Sytems Design, SBCCI 2010, Sep 2010, Sao Paulo, Brazil. pp.8-13
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Area Optimization Of ROM-Based Controllers Dedicated To Digital Signal Processing Applications18th EURASIP European Conference on Signal Processing 2010, EUSIPCO 2010, Aug 2010, Aalborg, Denmark. pp.547-551
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A Low-Area Filter Bank Design Methodology for On-Chip ADC TestingIEEE International Conference on Electronics, Circuits and Systems, ICECS 2010, Dec 2010, Athens, Greece. pp.724-727
Communication dans un congrès
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Efficient phase noise modeling of a PLL-based frequency synthesizer4th International Symposium on Communications, Control and Signal Processing (ISCCSP), 2010, Cyprus. pp.1-4, ⟨10.1109/ISCCSP.2010.5463478⟩
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Génération de moniteurs matériels dans un processus de synthèse de haut-niveauJNRDM 2010, Jun 2010, Montpelleir, France. pp.1-4
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Gestion des Assertions Comportementales dans un Flot de Synthèse de Haut-NiveauGDR SocSiP, Jun 2010, Paris, France
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A Multi-Core AES Cryptoprocessor for Multi-Channel SDRMilitary Communication and Information Systems Conference, MCC 2010, Sep 2010, Wroclaw, Poland. pp.1-7
Communication dans un congrès
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Behavioral Assertion Support in HLS Design Flow.System, Software, SoC and Silicon Debug Conference, SD4 2010, Sep 2010, Southampton, United Kingdom. pp.1
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A Reconfigurable Crypto Sub System for the Sotware Communication ArchitectureIEEE Military Communications Conference, MILCOM 2009, Oct 2009, Boston, United States. pp.1-7
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High-Level Synthesis for the Design of FPGA-based Signal Processing SystemsIEEE International Symposium on Systems, Architectures, Modeling, and Simulation Conference (SAMOS'09), Jul 2009, Samos, Greece. pp.000
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Experiments on Designing Low Power Decimation Filter for Multistandard Receiver on heterogeneous targets17th EURASIP European Conference on Signal Processing, Aug 2009, Glasgow, United Kingdom. pp.000
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Automated Multimode System Design for High Performance DSP Applications17th EURASIP European Conference on Signal Processing, Aug 2009, United Kingdom. pp.000
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Introduction à la synthèse de haut niveau (HLS)Ecole thématique d'Architectures des systèmes matériels enfouis et méthodes de conception associées, Apr 2009, Lannion, France
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Low Power Decimation and Channel Selection Filter for Multistandard ReceiverIEEE Wireless Communications and Wireless Networking Conference (WCNC'09), 2009, Budapest, Hungary. pp.000
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CrypatArchi Web Site : A collaborative Web Site for Teachnig Hardware SecurityInternational CrypatArchi Workshop, Sep 2008, Trégastel, France
Communication dans un congrès
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Optimized Decimation Filter Architecture for 5th Order Σ∆ Converter in GSM/ UMTS/ Wi-max Radio ReceiverIEEE International conference on Signals, Circuits & Systems (SCS'08), Dec 2008, Hammamet, Tunisia. pp.000
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Site internet collaborative pour l'enseignement de la sécurité matérielle7ème Colloque sur l'Enseignement des Technologies et des Sciences de l'Information et des Systèmes (CESTIS 2008), Oct 2008, Bruxelles, Belgique
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A New Orthogonal Online Digital Calibration for Time-Interleaved Analog-to-Digital ConvertersISCAS'2008, May 2008, Seattle, United States. pp.576-579
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Orthogonal correction implementation for time interleaved analog-to-digital converters: realtime application16th EURASIP European Conference on Signal Processing (EUSIPCO'08), Aug 2008, Lausanne, Switzerland. pp.000
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Low power implementation of decimation filter for multistandard receiverIEEE Design and Technology of Integrated Systems (DTIS'08), Mar 2008, Tozeur, Tunisia. pp.00
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Unité de gestion des modes d'un IP multimodeJournées nationales du réseau doctoral en microélectronique (JNRDM 2008), May 2008, Bordeaux, France
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Optimized Decimation Structure for Complex Bandpass ΣΔ Modulator in Wideband ReceiverIMEKO Workshop on ADC and DAC Modelling and Testing, Sep 2008, Florence, Italy. pp.000
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Travaux pratiques de gestion de périphériques d'une carte FPGA Xilinx Starter-Kit Spartan3-E à l'aide de picoprocesseur (picoBlaze)7ème Colloque sur l'Enseignement des Technologies et des Sciences de l'Information et des Systèmes (CESTIS 2008), Oct 2008, Bruxelles, Belgique
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Mathematical Functions Based Watermarking for IPPIEEE International Conference on Electronics, Circuits and Systems (ICECS'07), Dec 2007, Marrakech, Morocco. pp.00
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A Multi-Rate Filter for Broadband Radiotelescopes15th IMEKO-TC4 International Symposium, Sep 2007, Iasi, Romania. pp.55-60
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Intellectual Property Protection using WatermakingColloque national du GDR SOC-SIP, Jun 2007, Paris, France
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A Decimation Filter for a Very Large Band Signal in RadioastronomyPRIME'2007, Jul 2007, Bordeaux, France. pp.PRIME 2007 15.3
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HLS Design Flow for Multimode IP Generation Under Multiple ConstraintsIEEE International Conference on Electronics, Circuits and Systems, Dec 2007, Marrakech, Morocco. pp.000
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Les convertisseurs analogique numérique entrelacés dans le temps: théorie et nouvelles tendances des méthodes de correction d'erreursJNRDM'2007, May 2007, Lille, France. pp.1-4
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Multimode architecture designDesign and Architectures for Signal and Image Processing Workshop (DASIP'07), Dec 2007, Grenoble, France. pp.00
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New Adaptive Calibration Method for Time Interleaved Analog to Digital ConvertersNEWCAS'2007, Aug 2007, Ottawa, Canada. pp.932-935
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Bit-Width Optimizations for High-level Synthesis of Digital Signal Processing SystemsDesign of Circuits and Integrated Systems (DCIS'06), Nov 2006, Barcelona, Spain. pp.000
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Bit-Width Optimizations for High-level Synthesis of Digital Signal Processing Systems2006, pp.180
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IP Generation Targeting Multiple Bit-Width StandardsIEEE International Conference on Electronics, Circuits and Systems (ICECS'06), Dec 2006, Nice, France. pp.000
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Bit-Width Aware High-level Synthesis for Digital Signal Processing Systems2006, pp.175-178
Communication dans un congrès
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Pipelined memory controllers for DSP real time applications handling unpredictable data accessesthe European Signal Processing Conference (EUSIPCO'05), Sep 2005, Antalya, Turkey. pp.000
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Dynamic Memory Access Management and Address Computation for Dataflow Applications2005, pp.152-157
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Pipelined memory controllers for DSP applications handling unpredictable data acesses2005, pp.268 - 269
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Séquenceur mémoire pour applications multimédia temps réel gérant les séquences d'accès indéterministes2005, pp.183-186
Communication dans un congrès
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Dynamic memory access management and address computation for dataflow applicationsthe IFIP International Conference on Very Large Scale Integration (VLSI-SOC'05), Oct 2005, Perth, Australia. pp.152-157
Communication dans un congrès
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C- BASED RAPID PROTOTYPING FOR DIGITAL SIGNAL PROCESSINGEUSIPCO, 2005, Turkey. pp.1-4
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Bounded budgeted parallel architecture versus control dominated architecture for hazard data-signal processors synthesisthe SPIE Conference, Microtechnologies for the New Millennium (SPIE'05), May 2005, Sevilla, Spain. pp.100-111
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High Level Synthesis Assisted Rapid Prototyping for Digital Signal ProcessingIEEE International Conference on Microelectronics, Dec 2004, Tunis, Tunisia. pp.000
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Reed-solomon behavioral virtual component for communication systemsIEEE International Symposium on Circuits and Systems (ISCAS'04), May 2004, Vancouver, Canada. pp.000
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Electronic System Level to Hw/Sw Design Flow2004, pp.1-6
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Real-Time QCSP Communication System PrototypingPoster de conférence hal-03880799v1 |
Architecture programmable pour les systèmes de communications numériquesGDR SoC2, Jun 2021, Rennes, France
Poster de conférence
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AFF3CT : Un environnement de simulation pour le codage de canalLe 12ème Colloque du GDR SoC/SiP, Jun 2017, Bordeaux, France. , ⟨10.13140/RG.2.2.13492.91520⟩
Poster de conférence
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Cartesian Feedback with Digital Enhancement for CMOS RF TransmitterLinearization and Efficiency Enhancement Techniques for Silicon Power Amplifiers, 2014, ⟨10.1016/B978-0-12-418678-1.00002-7⟩
Chapitre d'ouvrage
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Contribution à la prise en compte des contraintes des applications TDSI dans la synthèse de haut niveauMicro et nanotechnologies/Microélectronique. Université de Bretagne Sud, 2005. Français. ⟨NNT : ⟩
Thèse
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Adéquation Algorithme Architecture - Approches matérielles et logicielles pour les applications de communications numériquesArchitectures Matérielles [cs.AR]. Université de Bordeaux, 2023
HDR
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