Brice Colombier
- Laboratoire Hubert Curien (LabHC)
Publications
Publications
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Implementing SPHINCS+ on Embedded Systems: Ensuring Performance in Resource-Constrained EnvironmentsEuropean Congress of Embedded Real Time Systems, Société de l’Électricité, de l’Électronique et des Technologies de l’Information et de la Communications; Association Aéronautique et Astronautique de France, Feb 2026, Toulouse, France. ⟨10.82331/ERTS.2026.31⟩ |
Low-Latency (i)FFT RTL Implementation for the FALCON Post-Quantum Signature AlgorithmInternational Workshops on Cryptographic Architectures Embedded in Logic Devices - CyrptArchi, Jun 2025, Autrans, France |
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Low-Latency FFT/iFFT RTL Implementation for the FALCON Post-Quantum Signature AlgorithmAnnual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM), May 2025, Fayetteville, Arkansas, United States |
Masking Falcon Gaussian SamplerInternational Workshops on Cryptographic Architectures Embedded in Logic Devices - CyrptArchi, Jun 2025, Autrans, France |
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Side-Channel Extraction of Dataflow AI Accelerator Hardware Parameters2025 IEEE 31st International Symposium on On-Line Testing and Robust System Design (IOLTS), Jul 2025, Ischia, Italy. pp.1-7, ⟨10.1109/IOLTS65288.2025.11117043⟩ |
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Message-recovery Horizontal Correlation Attack on Classic McElieceConference on Constructive Approaches for Security Analysis and Design of Embedded Systems (CASCADE 2025), Apr 2025, Saint-Étienne, France |
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TrustSoC: Light and Efficient Heterogeneous SoC Architecture, Secure-by-design2023 Asian Hardware Oriented Security and Trust Symposium (AsianHOST), Dec 2023, Tianjin, China. pp.1-6, ⟨10.1109/AsianHOST59942.2023.10409311⟩ |
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Punctured Syndrome Decoding ProblemCOSADE 2023 - Constructive side-channel analysis and secure design, Apr 2023, Munich (Allemagne), Germany. pp.170-192, ⟨10.1007/978-3-031-29497-6_9⟩ |
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A Side-Channel Attack against Classic McEliece when loading the Goppa Polynomial.Progress in Cryptology - AFRICACRYPT, Jul 2023, Sousse, Tunisia, Tunisia. pp.105-125, ⟨10.1007/978-3-031-37679-5_5⟩ |
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Key-Recovery by Side-Channel Information on the Matrix-Vector Product in Code-Based Cryptosystems25th International Conference on Information Security and Cryptology (ICISC 2022), Nov 2022, Séoul, South Korea. pp.219-234, ⟨10.1007/978-3-031-29371-9_11⟩ |
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Microarchitectural Insights into Unexplained Behaviors under Clock Glitch Fault Injection22nd Smart Card Research and Advanced Application Conference (CARDIS 2023), Nov 2023, Amsterdam, Netherlands. pp.1-20 |
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Multi-spot Laser Fault Injection Setup: New Possibilities for Fault Injection Attacks20th Smart Card Research and Advanced Application Conference - CARDIS 2021, Nov 2021, Lübeck, Germany. pp.151-166, ⟨10.1007/978-3-030-97348-3_9⟩ |
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Integer Syndrome Decoding in the Presence of NoiseIEEE Information Theory Workshop (ITW 2022), IEEE, Nov 2022, Mumbai, India. pp.482-487, ⟨10.1109/ITW54588.2022.9965806⟩ |
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Variable-Length Instruction Set: Feature or Bug?25th Euromicro Conference on Digital System Design (DSD 2022), Aug 2022, Maspalomas, Spain |
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Online Performance Evaluation of Deep Learning Networks for Profiled Side-Channel AnalysisInternational Workshop on Constructive Side-Channel Analysis and Secure Design (COSADE), Apr 2020, Lugano ( virtual ), Switzerland. pp.200-218, ⟨10.1007/978-3-030-68773-1_10⟩ |
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Message-Recovery Laser Fault Injection Attack on the Classic McEliece CryptosystemAdvances in Cryptology - EUROCRYPT, Oct 2021, Zagreb, Croatia. pp.438-467, ⟨10.1007/978-3-030-77886-6_15⟩ |
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Microarchitecture-aware Fault Models: Experimental Evidence and Cross-Layer Inference MethodologyInternational Conference on Design & Technology of Integrated System in Nanoscale Era (DTIS 2021), Jun 2021, Apulia (virtual), Italy |
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Single-bit Laser Fault Model in NOR Flash Memories2020 Workshop on Fault Detection and Tolerance in Cryptography (FDTC), Sep 2020, Milan, Italy. pp.41-48, ⟨10.1109/FDTC51366.2020.00013⟩ |
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Backtracking Search for Optimal Parameters of a PLL-based True Random Number Generator2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), Mar 2020, Grenoble, France. pp.1-6, ⟨10.23919/DATE48585.2020.9116307⟩ |
Apprentissage profond pour les attaques par analyse de canaux auxiliaires des implémentations de fonctions cryptographiquesEcole d’hiver Francophone sur les Technologies de Conception des Systèmes embarqués Hétérogènes, FETCH, Feb 2020, Montréal, Canada |
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Improved Deep-Learning Side-Channel Attacks using Normalization layersWorkshop on Randomness and Arithmetics for Cryptography on Hardware (WRAC’H), Apr 2019, Roscoff, France |
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Transient Effect Ring Oscillators Leak TooIEEE Computer Society Annual Symposium on VLSI (ISVLSI 2019), Jul 2019, Miami, FL, United States. ⟨10.1109/ISVLSI.2019.00016⟩ |
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Laser-induced Single-bit Faults in Flash Memory: Instructions Corruption on a 32-bit Microcontroller2019 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), May 2019, McLean, United States. pp.1-10, ⟨10.1109/HST.2019.8741030⟩ |
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Complete activation scheme for FPGA-oriented IP cores design protection27th International Conference on Field-Programmable Logic and Applications, Sep 2017, Ghent, Belgium |
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Centrality Indicators for Efficient and Scalable Logic MaskingIEEE Computer Society Annual Symposium on VLSI (ISVLSI 2017), IEEE, Jul 2017, Bochum, Germany. pp.98-103, ⟨10.1109/ISVLSI.2017.26⟩ |
A comprehensive hardware/software infrastructure for IP cores design protectionIEEE International Conference on Field-Programmable Technology, ICFPT 2017, Dec 2017, Melbourne, Australia |
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Centrality Indicators for Efficient and Scalable Logic MaskingIn International CryptArchi Workshop 2017, Jun 2017, Smolenice, Slovakia |
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Complete activation scheme for IP design protectionIEEE International Symposium on Hardware Oriented Security and Trust (HOST), May 2017, MCLEAN, VIRGINIA, United States |
Key Reconciliation Protocols: an Alternative for Lightweight Authentication of Integrated CircuitsInternational CryptArchi Workshop , Jun 2016, La Grande-Motte, France |
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Key Reconcilication Protocol Application to Error Correction in Silicon PUF ResponsesWorkshop on Trustworthy Manufacturing and Utilization of Secure Devices, TRUDEVICE 2016 (Workshop of Date 2016), Mar 2016, Dresden, Germany |
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Reversible Denial-of-Service by Locking Gates Insertion for IP Cores Design Protection{IEEE} Computer Society Annual Symposium on VLSI, CNRS-LIRMM, France, Jul 2015, Montpellier, France |
Functional Locking Modules for Design Protection of Intellectual Property CoresWorkshop on Trustworthy Manufacturing and Utilization of Secure Devices, TRUDEVICE 2015 (Workshop of Date 2015), Mar 2015, Grenoble, France |
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Functional Locking Modules for Design Protection of Intellectual Property CoresIEEE 23rd Annual International Symposium on Field-Programmable Custom Computing Machines, May 2015, vancouver, Canada. pp.233, ⟨10.1109/FCCM.2015.17⟩ |
Reversible Denial-of-Service by Locking Gates Insertion for IP Cores Design ProtectionInternational CryptArchi Workshop 2015, Jun 2015, Leuven, Belgium |
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Polynomial structures in code-based cryptographyIndocrypt 2013, Dec 2013, India. pp.286-296 |
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Countermeasures and Advanced AttacksEmmanuel Prouff; Guénaël Renault; Matthieu Rivain; Colin O'Flynn. Embedded Cryptography 1, 1, Wiley; ISTE, 2025, 9781789452136. ⟨10.1002/9781394351879.ch7⟩ |
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Turning Electronic Circuits Features into On-Chip LocksLilian Bossuet; Lionel Torres. Foundations of Hardware IP Protection, Springer International Publishing, pp.15-36, 2017, 978-3-319-50378-3. ⟨10.1007/978-3-319-50380-6_2⟩ |
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Logic Modification-Based IP Protection Methods: An Overview and a ProposalBossuet, Lilian, Torres, Lionel. Foundations of Hardware IP Protection, 2, Springer, pp.30-64, 2017, 978-3-319-50378-3 |
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Methods for protecting intellectual property of IP cores designersMicro and nanotechnologies/Microelectronics. Université de Lyon, 2017. English. ⟨NNT : 2017LYSES038⟩ |