
Caroline HERNANDEZ
75
Documents
Publications
Publications
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« Coatings » : de l’infiniment petit à l’infiniment grandMatière Condensée [cond-mat]. Grenoble INP, 2014
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tel-05024841
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PROCEDE ET DISPOSITIF DE TRAITEMENT D'UNE SURFACEFrance, N° de brevet: FR2935617 (A1), EP 2328718 (A1), US2011/0215075 (A1), WO 2010026242 (A1). 2010, https://worldwide.espacenet.com/publicationDetails/biblio?CC=FR&DB=fr.espacenet.com&FT=D&KC=A1&NR=2935617A1&date=20100312&locale=fr_EP
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hal-05024869
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Imager system comprising an integrated optical filter arranged between an imager and a transparent plateFrance, N° de brevet: FR2904144 (A1), EP 1881532 (A2), US7851826, US11779171, US2008/0023739 (A1), US2011/0045625 (A1). 2008, https://worldwide.espacenet.com/publicationDetails/biblio?CC=FR&DB=fr.espacenet.com&FT=D&KC=A1&NR=2904144A1&date=20080125&locale=fr_EP
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hal-05024890
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Method of fabricating lenses, in particular for CMOS imaging devicesFrance, Patent n° : FR2901614 (A1), EP1860466 (A1), US7919022 (B2). 2007, https://worldwide.espacenet.com/publicationDetails/biblio?CC=FR&DB=fr.espacenet.com&FT=D&KC=A1&NR=2901614A1&date=20071130&locale=fr_EP
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hal-05024908
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METHOD FOR PROCESSING A SCRATCHED SURFACE, PARTICULARLY A GLASS PLATE OF A SEMICONDUCTOR WAFERFrance, Patent n° : FR2901638 (A1), EP1860700 (A2), US2007/0290244 (A1). 2007, https://worldwide.espacenet.com/publicationDetails/biblio?CC=FR&DB=fr.espacenet.com&FT=D&KC=A1&NR=2901638A1&date=20071130&locale=fr_EP
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hal-05024898
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SEMICONDUCTOR WAFER THINNINGFrance, Patent n° : FR2878076 (A1), EP1815509 (A2), US2007/0218649 (A1), WO/2006/054024. 2006, https://worldwide.espacenet.com/publicationDetails/biblio?CC=FR&DB=fr.espacenet.com&FT=D&KC=A1&NR=2878076A1&date=20060519&locale=fr_EP
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hal-05024914
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Process for nitriding the gate oxide layer of a semiconductor device and device obtainedFrance, Patent n° : US6372581 (B1),EP0976148 (B1), FR2775120 (A1), WO/1999/043023. 2002, https://worldwide.espacenet.com/publicationDetails/biblio?CC=US&DB=EPODOC&FT=D&KC=B1&NR=6372581B1&adjacent=true&date=20020416&locale=en_EP
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hal-05025129
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MOSFET transistor with short channel effect compensated by the gate materialFrance, Patent n° : FR2795868 (A1), US6528399 (B1). 2001, https://worldwide.espacenet.com/publicationDetails/biblio?CC=FR&DB=fr.espacenet.com&FT=D&KC=A1&NR=2795868A1&date=20010105&locale=fr_EP
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hal-05024943
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Method for making a device comprising layers of planes of quantum dotsFrance, Patent n° : FR2797093 (A1), US6690027 (B1), EP1198840 (A1), WO/2001/008225. 2001, https://worldwide.espacenet.com/publicationDetails/biblio?CC=FR&DB=fr.espacenet.com&FT=D&KC=A1&NR=2797093A1&date=20010202&locale=fr_EP
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hal-05024924
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Process for restricting interdiffusion in a semiconductor device with composite Si/SiGe gateFrance, Patent n° : US6255149 (B1), FR2775119 (A1), EP0976149 (B1), WO/1999/043024. 2001, https://worldwide.espacenet.com/publicationDetails/biblio?CC=US&NR=6255149&KC=&FT=E&locale=en_EP
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hal-05025123
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Process for obtaining a layer of single-crystal germanium or silicon on a substrate of single-crystal silicon or germanium, respectively, and multilayer products obtainedFrance, Patent n° : US6117750 (A) et FR2773177(A1), US6429098 (B1), EP0930382 (B1). 2000, https://worldwide.espacenet.com/publicationDetails/biblio?CC=FR&DB=fr.espacenet.com&FT=D&KC=A1&NR=2773177A1&date=19990702&locale=fr_EP
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hal-05025110
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METHOD FOR TREATING, BY NITRIDING, A SILICON SUBSTRATE FOR FORMING A THIN INSULATING LAYERFrance, Patent n° : FR2783530 (A1), EP1115895 (B1), WO/2000/017412, US6551698 (B1). 2000, https://worldwide.espacenet.com/publicationDetails/biblio?CC=FR&DB=fr.espacenet.com&FT=D&KC=A1&NR=2783530A1&date=20000324&locale=fr_EP
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hal-05025106
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Process for obtaining a layer of single-crystal germanium on a substrate of single-crystal silicon, and products obtainedFrance, Patent n° : FR2783254 (A1), EP1115920 (B1), US6537370 (B1), WO/2000/015885. 2000, https://worldwide.espacenet.com/publicationDetails/biblio?CC=FR&DB=fr.espacenet.com&FT=D&KC=A1&NR=2783254A1&date=20000317&locale=fr_EP
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hal-05025109
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Process for fabrication of a planar heterostructureFrance, Patent n° : FR2791810 (A1), US6399502 (B1), EP1772905 (A1), EP1041639 (B1). 2000, https://worldwide.espacenet.com/publicationDetails/biblio?CC=FR&DB=fr.espacenet.com&FT=D&KC=A1&NR=2791810A1&date=20001006&locale=fr_EP
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hal-05024946
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Process for nitriding the gate oxide layer of a semiconductor device and device obtainedFrance, Patent n° : FR2775120 (A1), JP2002510437 (A), WO9943023 (A1), EP0976148 (A1), EP0976148 (B1), DE69934362 (T2). 1998
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hal-05025140
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