Gilles Sassatelli
Présentation
Publications
Publications
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Low-Rank Equilibrium Propagation: An Online Incremental Learning Architecture for Analog-Based Hardware AcceleratorsMOCAST 2025 - 14th International Conference on Modern Circuits and Systems Technologies, Jun 2025, Dresden, Germany. ⟨10.1109/MOCAST65744.2025.11083959⟩ |
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Run-time Energy-Efficiency Optimization for AI and HPC WorkloadsSC Workshops 2025 - Workshops of the International Conference for High Performance Computing, Networking, Storage and Analysis, Nov 2025, St Louis, MO, United States. pp.1970-1979, ⟨10.1145/3731599.3767560⟩ |
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Designing Compatible Analog Circuits for Equilibrium Propagation: Implementations Using The Adjoint Method and Reciprocity PrinciplesISVLSI 2025 - IEEE Computer Society Annual Symposium on VLSI, Jul 2025, Kalamata, Greece. pp.1-6, ⟨10.1109/ISVLSI65124.2025.11130216⟩ |
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Energy-efficient Hardware Reuse for Sustainable Data CentresEco-ES 2023 - Workshop on Eco-design and circular economy of Electronic Systems@DATE 2023, Apr 2023, Antwerp, Belgium |
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Towards Sustainable Low Carbon Emission Mini Data CentresComPAS 2023 - Conférence francophone d'informatique en Parallélisme, Architecture et Système, Jul 2023, Annecy, France |
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Energy-Based Analog Neural Network FrameworkSOCC 2022 - 35th IEEE International System on Chip Conference, IEEE, Sep 2022, Belfast, United Kingdom. pp.1-6, ⟨10.1109/SOCC56010.2022.9908086⟩ |
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A Generative AI for Heterogeneous Network-on-Chip Design Space PruningDATE 2022 - 25th Design, Automation and Test in Europe Conference and Exhibition, Mar 2022, Antwerp, Belgium. pp.1135-1138, ⟨10.23919/DATE54114.2022.9774721⟩ |
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Modeling and Analysis for Energy-Driven Computing using Statistical Model-CheckingDATE 2021 - 24th Design, Automation and Test in Europe Conference and Exhibition, Feb 2021, Grenoble (Virtual), France. pp.980-985, ⟨10.23919/DATE51398.2021.9474224⟩ |
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Highly-Adaptive Mixed-Precision MAC Unit for Smart and Low-Power Edge ComputingNEWCAS 2021 - 19th IEEE International New Circuits and Systems Conference, Jun 2021, Toulon (virtual), France. pp.1-4, ⟨10.1109/NEWCAS50681.2021.9462745⟩ |
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GANNoC: A Framework for Automatic Generation of NoC Topologies using Generative Adversarial NetworksRAPIDO 2021 - 13th Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools, Jan 2021, Budapest, Hungary. pp.51-58, ⟨10.1145/3444950.3447283⟩ |
L’impact énergétique des flux de données numériquesColloque Energie du CNRS, Cellule énergie du CNRS, Dec 2021, Paris, France |
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A Flexible Power Crossbar-based Architecture for Software-Defined Power DomainsEPE’20 ECCE Europe, Sep 2020, Lyon (virtual), France |
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Online Learning for Dynamic Control of OpenMP WorkloadsMOCAST 2020 - 9th International Conference on Modern Circuits and Systems Technologies, Sep 2020, Bremen, Germany. ⟨10.1109/MOCAST49295.2020.9200292⟩ |
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Évaluation de deux architectures matérielles dédiées à l'inférence basée sur des réseaux de neurones convolutifsComPAS 2020 - Conférence francophone d'informatique en Parallélisme, Architecture et Système, Jun 2020, Lyon, France |
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Versatile Software Framework for the Monitoring and Control of Distributed Computing SystemsEDiS 2020 - 2nd International Conference on Embedded & Distributed Systems, Apr 2020, Oran, Algeria. pp.117-122, ⟨10.1109/EDiS49545.2020.9296483⟩ |
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Energy-Efficient Machine Learning on FPGA for Edge Devices: a Case StudyComPAS 2020 - Conférence francophone d'informatique en Parallélisme, Architecture et Système, Jun 2020, Lyon, France |
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Exploration of Energy-Proportional Distributed Systems13e Colloque National du GDR SoC², Jun 2019, Montpellier, France |
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Automatic Energy-Efficiency Monitoring of OpenMP WorkloadsReCoSoC 2019 - 14th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, Jul 2019, York, United Kingdom. pp.43-50, ⟨10.1109/ReCoSoC48741.2019.9034988⟩ |
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Performance and Energy Assessment of Last-Level Cache Replacement PoliciesEDiS: Embedded and Distributed Systems, Dec 2017, Oran, Algeria. ⟨10.1109/EDIS.2017.8284032⟩ |
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Improving the Performance of STT-MRAM LLC through Enhanced Cache Replacement PolicyARCS: Architecture of Computing Systems, Apr 2018, Braunschweig, Germany. pp.168-180, ⟨10.1007/978-3-319-77610-1_13⟩ |
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Using multifunctional standardized stack as universal spintronic technology for IoTDATE 2018 - 21st Design, Automation and Test in Europe Conference and Exhibition, Mar 2018, Dresden, Germany. pp.931-936, ⟨10.23919/DATE.2018.8342143⟩ |
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Evaluation of Heterogeneous Multicore Cluster Architectures Designed for Mobile ComputingReCoSoC: Reconfigurable Communication-centric Systems-on-Chip, Jul 2018, Lille, France. ⟨10.1109/ReCoSoC.2018.8449376⟩ |
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Distributed and Dynamic Shared-Buffer Router for High-Performance InterconnectNOCS 2017 - 11th IEEE/ACM International Symposium on Networks-on-Chip, Oct 2017, Seoul, South Korea. pp.1-8, ⟨10.1145/3130218.3130223⟩ |
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Efficient Programming for Multicore Processor Heterogeneity: OpenMP versus OmpSsOpenSuCo, Jun 2017, Frankfurt, Germany |
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ElasticSimMATE: a Fast and Accurate gem5 Trace-Driven Simulator for Multicore SystemsReCoSoC: Reconfigurable Communication-centric Systems-on-Chip, Jul 2017, Madrid, Spain. ⟨10.1109/ReCoSoC.2017.8016146⟩ |
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Embedded systems to high performance computing using STT-MRAMDATE 2017 - 20th Design, Automation and Test in Europe Conference and Exhibition, Mar 2017, Lausanne, Switzerland. pp.536-541, ⟨10.23919/DATE.2017.7927046⟩ |
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MAGPIE: System-level Evaluation of Manycore Systems with Emerging Memory TechnologiesEMS: Emerging Memory Solutions, Mar 2017, Lausanne, Switzerland |
Roundabout: A Network-on-Chip router with adaptive buffer sharingNEWCAS 2017 - 15th IEEE International New Circuits and Systems Conference, Jun 2017, Strasbourg, France. pp.65-68, ⟨10.1109/NEWCAS.2017.8010106⟩ |
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Scalable and Power-Efficient Implementation of an Asynchronous Router with Buffer SharingDSD 2017 - 20th Euromicro Conference on Digital System Design, Aug 2017, Vienna, Australia. pp.171-178, ⟨10.1109/DSD.2017.55⟩ |
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Design space exploration for complex automotive applications: an engine control system case studyRAPIDO: Rapid Simulation and Performance Evaluation, Jan 2016, Prague, Czech Republic. ⟨10.1145/2852339.2852341⟩ |
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Flot automatique d’évaluation pour l’exploration d’architectures à base de mémoires non volatilesComPAS 2016 - Conférence francophone d'informatique en Parallélisme, Architecture et Système, Jul 2016, Lorient, France |
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OpenMP scheduling on ARM big.LITTLE architectureMULTIPROG 2016 - 9th International Workshop on Programmability and Architectures for Heterogeneous Multicores, HIPEAC, Jan 2016, Prague, Czech Republic |
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Speed and Accuracy Dilemma in NoC Simulation: What about Memory Impact?ReCoSoC: Reconfigurable Communication-centric Systems-on-Chip, Jun 2016, Tallinn, Estonia |
Performance Prediction of Application Mapping in Manycore Systems with Artificial Neural NetworksMCSoC: Embedded Multicore/Many-core Systems-on-Chip, Sep 2016, Lyon, France. pp.185-192, ⟨10.1109/MCSoC.2016.17⟩ |
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Loop Optimization in Presence of STT-MRAM Caches: a Study of Performance-Energy TradeoffsPATMOS: Power and Timing Modeling, Optimization and Simulation, Sep 2016, Bremen, Germany. pp.162-169, ⟨10.1109/PATMOS.2016.7833682⟩ |
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A Workflow for Fast Evaluation of Mapping Heuristics Targeting Cloud InfrastructuresDREAMCloud: Dynamic Resource Allocation and Management in Embedded, High Performance and Cloud Computing, Jan 2016, Prague, Czech Republic |
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Full-System Simulation of big.LITTLE Multicore Architecture for Performance and Energy ExplorationMCSoC: Embedded Multicore/Many-core Systems-on-Chip, Sep 2016, Lyon, France. pp.201-208, ⟨10.1109/MCSoC.2016.20⟩ |
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A trace-driven approach for fast and accurate simulation of manycore architecturesASP-DAC: Asia and South Pacific Design Automation Conference, Jan 2015, Chiba, Tokyo, Japan. pp.707-712, ⟨10.1109/ASPDAC.2015.7059093⟩ |
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An Integrated Framework for Model-Based Design and Analysis of Automotive Multi-Core SystemsFDL: Forum on specification & Design Languages, Sep 2015, Barcelona, Spain |
A Distributed Energy-aware Task Mapping to Achieve Thermal Balancing and Improve Reliability of Many-core SystemsSBCCI: Symposium on Integrated Circuits and Systems Design, Aug 2015, Salvador de Bahia, Brazil. ⟨10.1145/2800986.2800992⟩ |
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Trading-off System Load and Communication in Mapping Heuristics for Improving NoC-Based MPSoCs ReliabilityISQED 2015 - 16th International Symposium on Quality Electronic Design, Mar 2015, Santa Clara, United States. pp.392-396, ⟨10.1109/ISQED.2015.7085457⟩ |
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Design Exploration for next Generation High-Performance Manycore On-chip Systems: Application to big.LITTLE ArchitecturesISVLSI: International Symposium on Very Large Scale Integration, Jul 2015, Montpellier, France. pp.551-556, ⟨10.1109/ISVLSI.2015.28⟩ |
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Adaptive Power monitoring for self-aware embedded systemsNORCAS 2015 - 1st Nordic Circuits and Systems Conference, Oct 2015, Oslo, Norway. ⟨10.1109/NORCHIP.2015.7364364⟩ |
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Potential Applications Based on NVM Emerging TechnologiesDATE 2015 - 18th Design, Automation and Test in Europe Conference and Exhibition, Mar 2015, Grenoble, France. pp.1012-1017, ⟨10.7873/DATE.2015.1120⟩ |
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Emerging Non-volatile Memory Technologies Exploration Flow for Processor ArchitectureISVLSI 2015 - International Symposium on Very Large Scale Integration, Jul 2015, Montpellier, France. pp.460-465, ⟨10.1109/ISVLSI.2015.126⟩ |
On the Performance Exploration of 3D NoCs with Resistive-Open TSVsISVLSI 2015 - International Symposium on Very Large Scale Integration, Jul 2015, Montpellier, France. pp.579-584, ⟨10.1109/ISVLSI.2015.49⟩ |
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Performance exploration of partially connected 3D NoCs under manufacturing variabilityNEWCAS 2014 - 12th IEEE International New Circuits and Systems Conference, Jun 2014, Trois-Rivieres, QC, Canada. pp.61-64, ⟨10.1109/NEWCAS.2014.6933985⟩ |
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Power efficient Thermally Assisted Switching Magnetic memory based memory systemsReCoSoC: Reconfigurable and Communication-Centric Systems-on-Chip, May 2014, Montpellier, France. ⟨10.1109/ReCoSoC.2014.6861357⟩ |
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Method for dynamic power monitoring on FPGAsFPL: Field Programmable Logic and Applications, Sep 2014, Munich, Germany. ⟨10.1109/FPL.2014.6927457⟩ |
Power efficiency in exascale HPC systemsEcole d’été de la plateforme HPC@LR, Jul 2013, Montpellier, France |
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Evaluation of hybrid MRAM/CMOS cells for reconfigurable computingNEWCAS: New Circuits and Systems, Jun 2013, Paris, France. ⟨10.1109/NEWCAS.2013.6573676⟩ |
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Embedded memory hierarchy exploration based on magnetic RAMFTFC: Faible Tension Faible Consommation, Jun 2013, Paris, France. ⟨10.1109/FTFC.2013.6577780⟩ |
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Simultaneous multithreading support in embedded distributed memory MPSoCsDAC 2013 - 50th Design Automation Conference, May 2013, Austin, United States. pp.83:1-83:7, ⟨10.1145/2463209.2488836⟩ |
Trends on the Application of Emerging Nonvolatile Memory to Processors and Programmable DeviceISCAS: International Symposium on Circuits and Systems, May 2013, Beijing, China. pp.101-104, ⟨10.1109/ISCAS.2013.6571792⟩ |
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Instruction-Driven Timing CPU Model for Efficient Embedded Software Development Using OVPICECS: International Conference on Electronics, Circuits, and Systems, Dec 2013, Abu Dhabi, United Arab Emirates. pp.855-858, ⟨10.1109/ICECS.2013.6815549⟩ |
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High Performance SoC Design Using Magnetic Logic and MemoryVLSI-SoC: Very Large Scale Integration - System-on-Chip, Oct 2011, Hong Kong, China. pp.10-33, ⟨10.1007/978-3-642-32770-4_2⟩ |
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Adaptation Strategies in Multiprocessors System on ChipVLSI-SoC: Very Large Scale Integration - System-on-Chip, Sep 2010, Madrid, Spain. pp.233-257, ⟨10.1007/978-3-642-28566-0_10⟩ |
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Accuracy evaluation of GEM5 simulator systemReCoSoC 2012 - 7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip, Jul 2012, York, United Kingdom. pp.1-7, ⟨10.1109/ReCoSoC.2012.6322869⟩ |
Modular Framework for Multi-level Multi-device MPSoC Simulation2011 IEEE International Symposium on Parallel and Distributed Processing Workshops and PhD Forum, May 2011, Canada. pp.6, ⟨10.1109/IPDPS.2011.134⟩ |
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Open-Scale: A Scalable, Open-Source NOC-based MPSoC for Design Space ExplorationReConFig 2011 - International Conference on Reconfigurable Computing and FPGAs, Nov 2011, Cancun, Mexico. pp.357-362, ⟨10.1109/ReConFig.2011.66⟩ |
Evaluation of a distributed fault handler method for MPSoCISCAS: International Symposium on Circuits and Systems, May 2011, Rio de Janeiro, Brazil. pp.2329-2332, ⟨10.1109/ISCAS.2011.5938069⟩ |
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Design of MRAM Based Logic Circuits and its ApplicationsGLSVLSI'11: Great Lakes Symposium on VLSI, Switzerland. pp.431-436 |
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Predictive Dynamic Frequency Scaling for Multi-Processor Systems-on-ChipISCAS'2011: International Symposium on Circuits and Systems, 2011, Rio De Janeiro, RJ, Brazil. pp.1500-1503 |
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Evaluating the Impact of Task Migration in Multi-Processor Systems-on-ChipSBCCI 2010 - 23rd Symposium on Integrated Circuits and Systems Design, Sep 2010, Sao Paulo, Brazil. pp.73-78, ⟨10.1145/1854153.1854174⟩ |
Survey of New Trends in Industry for Programmable Hardware: FPGAs, MPPAs, MPSoCs, Structured ASICs, eFPGAs and New Wave of Innovation in FPGAs2010 International Conference on Field Programmable Logic and Applications; FPL2010, Aug 2010, Milan, Italy. pp.291-297, ⟨10.1109/FPL.2010.66⟩ |
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Providing Better Multi-Processor Systems-on-Chip Resources Utilization by Means of Using a Control-Loop Feedback MechanismReConFig 2010 - International Conference on ReConFigurable Computing and FPGAs, Dec 2010, Cancun, Mexico. pp.382-387, ⟨10.1109/ReConFig.2010.17⟩ |
An In-Memory Monitoring Database For Self Adaptive MP²SoCsDASIP: Design and Architectures for Signal and Image Processing, Oct 2010, Edimbourg, United Kingdom. pp.97-104, ⟨10.1109/DASIP.2010.5706252⟩ |
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Flexible and Distributed Real-Time Control on a 4G Telecom MPSoCISCAS'10: IEEE International Symposium on Circuits and Systems, Paris, France. pp.3961-3964 |
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Heterogeneous vs Homogeneous MPSoC Approaches for a Mobile LTE ModemDATE 2010 - Design, Automation and Test in Europe, Mar 2010, Dresden, Germany. pp.184-189 |
Exploration of Virtualization Techniques for Achieving Adaptability in Heterogeneous MPSoCsColloque GDR SoC-SiP, 2010, Paris, France |
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A Homogeneous MPSoC with Dynamic Task Mapping for Software Defined RadioISVLSI'10: IEEE Computer Society Annual Symposium on VLSI, Lixouri, Cephalonia, Greece. pp.345-350 |
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A Self-Adaptive Communication Protocol Allowing Fine Tuning Between Flexibility and Performance in Homogeneous MPSoC SystemsReconfigurable Communication-centric Systems on Chip, Karlsruhe, Germany. pp.N/A |
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D-Scale: A Scalable System-Level Dependable Method for MPSoCsATS: Asian Test Symposium, 2010, Shanghai, China. pp.198-205 |
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A Cost-Effective Solution to Increase System Reliability and Maintain Global Performance under Unreliable Silicon in MPSoCReConFig'10: International Conference on ReConFigurable Computing and FPGAs, Cancun, Mexico. pp.346-351 |
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Adaptative Integrated Systems for Optimal Hardware UsageEcole d'hiver Francophone sur les Technologies de Conception des Systèmes Embarqués Hétérogènes (FETCH 2010), Jan 2010, Chamonix, France |
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Bio-inspired Systems: Self-adaptability from Chips to Sensor-network ArchitecturesERSA: Engineering of Reconfigurable Systems and Algorithms, Jul 2009, Las Vegas, United States. pp.45-54 |
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The Jubi Approach: a Tool Set for Hardware Acceleration in Sensor Network Applications FieldPRIME'09: 2009 Ph.D. Research in Microelectronics and Electronics, pp.40-43 |
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MRAM based eFPGAs: programming and silicon flows, exploration environments, MRAM current state in Industry and its unique potentials for FPGAsReConFig'09: International Conference on ReConFigurable Computing and FPGAs, Dec 2009, Cancun, Mexico, pp.6 |
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Exploration of Power Reduction and Performance Enhancement in LEON3 Processor with ESL Reprogrammable e-FPGA In Processor Pipeline and as a Co-processorDATE 2009 - 12th Design, Automation and Test in Europe Conference and Exhibition, Apr 2009, Nice, France. pp.184-189, ⟨10.1109/DATE.2009.5090655⟩ |
A Bio-Inspired Agent Framework for Hardware Accelerated Distributed Pervasive ApplicationsAHS'09: NASA/ESA Conference on Adaptive Hardware and Systems, Jul 2009, San Fransisco, United States. pp.415-422, ⟨10.1109/AHS.2009.54⟩ |
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MPSoCs: from design to practiceIDT'09: 4th IEEE International Design and Test Workshop, France |
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Dynamic and Distributed Frequency Assignment for Energy and Latency Constrained MP-SoCDATE 2009 - 12th Design, Automation and Test in Europe Conference and Exhibition, Apr 2009, Nice, France. pp.1564-1567, ⟨10.1109/DATE.2009.5090912⟩ |
JubiTool: Unified Design Flow for the Perplexus SIMD Hardware AcceleratorCEC'09: IEEE Congress on Evolutionary Computation, 2009, Trondheim, Norway. pp.2070-2075 |
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MPI-Based Adaptive Task Migration Support on the HS-Scale SystemISVLSI 2008 - IEEE Computer Society Annual Symposium on VLSI, Apr 2008, Montpellier, France. pp.105-110, ⟨10.1109/ISVLSI.2008.87⟩ |
Baf: A Bio-Inspired Agent Framework for Distributed Pervasive ApplicationsGEM'08: Genetic and Evolutionary Mechanisms, Las Vegas, USA, pp.N/A |
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Temperature-Aware Distributed Run-Time Optimization on MP-SoC Using Game TheoryISVLSI'08: IEEE Computer Society Annual Symposium on VLSI, Apr 2008, Montpellier, France, pp.375-380 |
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The Perplexus Programming Framework: Combining Bio-inspiration and Agent-Oriented Programming for the Simulation of Large Scale Complex SystemsICES 2008 - International Conference on Evolvable Systems, Sep 2008, Prague, Czech Republic. pp.402-407, ⟨10.1007/978-3-540-85857-7_36⟩ |
A Non-Volatile Run-Time FPGA using Thermally Assisted Switching MRAMSFPL'08: IEEE International Conference on Field Programmable Logic and Applications, Heidelberg, Allemagne, pp.421-426 |
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Hierarchical Code Correction and Reliability Management in Embedded NOR Flash MemoriesETS: European Test Symposium, May 2008, Verbania, Italy. pp.84-90 |
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A Decentralised Task Mapping Approach for Homogeneous Multi-Processor Network-On-ChipsReCoSoc'08: 4th International Workshop on Reconfigurable Communication Centric System-On-Chips, Barcelona, Spain. pp.40-47 |
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A Flexible Modeling and Simulation Framework for Design Space ExplorationSOC 2008 - International Symposium on System-on-Chip, Nov 2008, Tampere, Finland. pp.001-004, ⟨10.1109/ISSOC.2008.4694863⟩ |
A Non-Volatile Field Programmable Gate Array using Thermally Assisted Switching MRAMsICESCA'08: International Conference on Embedded Systems & Critical Applications, May 2008, Gammarth, Tunisia. pp.95-100 |
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Exploration of Task Migration Policies on the HS-Scale SystemReCoSoc'08: 4th International Workshop on Reconfigurable Communication Centric System-On-Chips, Barcelona, Spain. pp.48-54 |
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Game-Theoretic Approach for Temperature-Aware Frequency Assignment with Task Synchronization on MP-SoCReConFig'08: International Conference on Reconfigurable Computing and FPGAs, Cancun, Mexico, pp.235-240 |
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Power Consumption Reduction Explorations in Processors by Enhancing Performance using Small ESL Reprogrammable eFPGAsReConFig'08: International Conference on Reconfigurable Computing and FPGA's, Cancun, Mexico, pp.313-318 |
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eFPGA Architecture Explorations: CAD & Silicon Analysis of Beyond 90nm Technologies to Investigate New Dimensions of Future InnovationsReCoSoc 2008 - 4th International Workshop on Reconfigurable Communication-Centric SoCs, Jul 2010, Barcelona, Spain. pp.17-24 |
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Convergence Analysis of Run-Time Distributed Optimization on Adaptive Systems Using Game TheoryFPL'08: International Conference on Field Programmable Logic and Applications, Sep 2008, Heidelberg, Germany. pp.555-558, ⟨10.1109/FPL.2008.4630007⟩ |
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Bio-Inspiration Helps Computers: An New MachineFPL'08: The 18th International Conference on Field-Programmable Logic and Applications, Sep 2008, Heidelberg, Germany. pp.697-698 |
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An exploration of run-time ditributed task mapping on massively parallel on-chip architectureSéminaire Invité UFRGS/PUCRS, Porto Alegre, Brazil |
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TEC-Tree: A Low-Cost, Parallelizable Tree for Efficient Defense Against Memory Replay AttacksCHES'07: Workshop on Cryptographic Hardware and Embedded Systems, Sep 2007, Vienna, Austria, pp.289-302, ⟨10.1007/978-3-540-74735-2_20⟩ |
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Current Mask Generation: an Analog Circuit to Thwart DPA AttacksVLSI-SoC 2005 - 13th International Conference on Very Large Scale Integration of System on Chip, Oct 2005, Perth, Australia. pp.317-330, ⟨10.1007/978-0-387-73661-7_20⟩ |
Application Case Studies on HS-Scale, a MP-SOC for Embbeded SystemsEmbedded Computer Systems: Architectures, Modeling and Simulation (SAMOS), Jul 2007, Samos, Greece. pp.88-95, ⟨10.1109/ICSAMOS.2007.4285738⟩ |
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Technological Hybridization for Efficient Runtime Reconfigurable FPGAsISVLSI'07: IEEE Computer Society Annual Symposium on VLSI, May 2007, Porto Allegre, Brazil, pp.29-34 |
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Run-Time Mapping and Communication Strategies for Homogeneous NoC-Based MPSoCsFCCM'07: International Symposium on Field-Programmable Custom Computing Machines, Apr 2007, Napa, California, pp.295-296 |
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A Code Compression Method with Encryption and Integrity CheckingCryptArchi: Cryptographic Architectures, Jun 2007, Montpellier, France |
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PERPLEXUS: Pervasive Computing Framework for Modeling Complex Virtually-Unbounded SystemsNASA/ESA AHS-2007 Conference on Adaptive Hardware and Systems, Aug 2007, pp.587-591 |
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IBC-EI: An Instruction Based Compression Method with Encryption and Integrity CheckingReCoSoC'07: International Workshop on Reconfigurable Communication Centric System-On-Chips, Jun 2007, Montpellier, France. pp.138-145 |
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Architecture for Highly Reliable Embedded Flash MemoriesDDECS: Design and Diagnostics of Electronic Circuits and Systems, Apr 2007, Krakow, Poland. pp.75-80, ⟨10.1109/DDECS.2007.4295257⟩ |
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HS Scale: A Run-Time Adaptable MP-SoC ArchitectureReCoSoC'07: International Workshop on Reconfigurable Communication Centric System-On-Chips, Jun 2007, Montpellier, France. pp.CDROM |
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An Adaptative MP-SoC Architecture for Embedded SystemsCAR'07: 2nd National Workshop on Control Architectures of Robots: From Models to Execution on Distributed Control Architectures, Jun 2007, Paris, France. pp.101-107 |
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HS-Scale: A Hardware-Software Scalable MP-SOC Architecture for Embedded SystemsISVLSI'07: IEEE Computer Society Annual Symposium on VLSI, 2007, Porto Allegre, Brazil, pp.21-28 |
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Architectural Issues in Homogeneous NOC-Based MPSOCRSP'07: 18th IEEE/IFIP International Workshop on Rapid System Prototyping, May 2007, Porto Alegre, Brazil, pp.139-142 |
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Evaluation of Design for Reliability Techniques in Embedded Flash MemoriesDATE: Design, Automation and Test in Europe, Apr 2007, Nice, France. pp.1593-1598, ⟨10.1109/DATE.2007.364529⟩ |
The Perplexus ProjectDASIP'07: Workshop on Design and Architectures for Signal and Image Processing, Nov 2007, Grenoble, France, France. pp.N/A |
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A Contextual Resources Use: A Proof of Concept Through the APACHES'PlatormDDECS: Design and Diagnostics of Electronic Circuits and Systems, Apr 2006, Prague, Czech Republic. pp.44-49, ⟨10.1109/DDECS.2006.1649568⟩ |
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PE-ICE: Parallelized Encryption and Integrity Checking EngineDDECS'06: 9th IEEE International Workshop on Design and Diagnostics of Electronic Circuits and Systems, Apr 2006, Prague, Czech Republic. pp.143-144 |
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A Leak Resistant SoC to Counteract Side Channel AttacksSOC'06: International Symposium on System-On-Chip, Nov 2006, Tampere, Finlande, pp.N/A |
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A Parallelized Way to Provide Data Encryption and Integrity Checking on a Processor-Memory BusDAC: Design Automation Conference, Jul 2006, San Francisco, CA, United States |
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How to Add the Integrity Checking Capability to Block Encryption AgorithmsIEEE PRIME'06: Ph.D. Research in MicroElectronics and Electronics, Jun 2006, Otranto, Lecce, Italy. pp.369-372 |
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Implémentation Matérielle d'une Arithmétique Résistante aux FuitesRenPar/ SympAAA/ CFSE - Rencontres Francophones en Parallélisme, Architecture, Adéquation Algorithmes Architecture et Système, Oct 2006, Canet en Roussillon, France. pp.57-74 |
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Remanent SRAM Structure for Runtime Reconfigurable FPGAReCoSoC'06: Second Reconfigurable Communication-Centric Systems-on-Chip Workshop, Jul 2006, Montpellier, France. pp.124-130 |
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Conception d'un FPGA Reconfigurable Dynamiquement à la Mémoire de Reconfiguration Non Volatile MagnétiqueJNRDM: Journées Nationales du Réseau Doctoral de Microélectronique, May 2006, Rennes, France |
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How to Add the Integrity Checking Capability to Block Encryption AlgorithmsPRIME'06, Jun 2006, France. pp.369-372 |
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Magnetic Tunnelling Junction Based FPGAFPGA 2006 - ACM/SIGDA 14th International Symposium on Field Programmable Gate Arrays, Feb 2006, Monterey, CA, United States. pp.123-130, ⟨10.1145/1117201.1117220⟩ |
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Run-Time Resources Management on Coarse Grained, Packet-Switching Reconfigurable Architecture: A Case Study Through the aPACHES' PlatformARC: Applied Reconfigurable Computing, Mar 2006, Delft, Netherlands. pp.134-145, ⟨10.1007/11802839_19⟩ |
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Dynamic hardware multiplexing: improving adaptability with a run time reconfiguration managerISVLSI 2006 - IEEE Computer Society Annual Symposium on VLSI, Mar 2006, Karlsruhe, Germany. pp.251-256, ⟨10.1109/ISVLSI.2006.38⟩ |
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How to Secure Embedded Programmable Gate Arrays?ReCoSoC 2006 - 2nd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, Jul 2006, Montpellier, France. pp.52-59 |
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A Leak Resistant Architecture Against Side Channel AttacksFPL: Field-Programmable Logic and Applications, Aug 2006, Madrid, Spain. pp.881-884, ⟨10.1109/FPL.2006.311335⟩ |
Securing Embedded Programmable Gate Arrays in Secure CircuitsIPDP 2006 - 20th IEEE International Parallel & Distributed Processing Symposium, Apr 2006, Rhodes Island, Greece. pp.215-221, ⟨10.1109/IPDPS.2006.1639483⟩ |
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New Non-Volatile FPGA Concept Using Magnetic Tunneling JunctionISVLSI'06: IEEE Computer Society Annual Symposium on VLSI, Mar 2006, Karlsruhe (Germany), pp.269-274 |
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Efficient Combination of data Encryption and Integrity Checking for Embedded SystemsReCoSoC'06: Second Reconfigurable Communication-Centric Systems-on-Chip Workshop, Jul 2006, Montpellier, France. pp.68-75 |
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Packet-Switching Network-On-Chip Features Exploration and CharacterizationVLSI-SOC'05: IFIP International Conference on Very Large Scale Integration, Oct 2005, Perth, Australia. pp.403-409 |
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Non-Volatile SRAM-FPGA based on Magnetic Tunnelling JunctionRECoSoC'05: 1st International Workshop on Reconfigurable Communication Centric System-On-Chips, Jun 2005, Montpellier, France. pp.113-120 |
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Magnetic remanent memory structures for dynamically reconfigurable FPGAFPL 2005 - 14th International Conference on Field Programmable Logic and Applications, Aug 2005, Tampere, Finland. pp.687-690, ⟨10.1109/FPL.2005.1515813⟩ |
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Run-Time Scheduling for Random Multi Tasking in Reconfigurable CoprocessorsFPL'05 IEEE : 15th International Workshop on Field-Programmable Logic and Applications, Aug 2005, Tampere (Finlande), pp.703-706 |
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A GALS Network on Chip with Quality of Service supportSAME'05: Sophia-Antipolis Forum on MicroElectronics, Oct 2005, Sophia Antipolis, France. pp.199-207 |
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A New Hardware Counter Measure for Masking Power Signatures of CryptocoresRECoSoC'05: 1st International Workshop on Reconfigurable Communication Centric System-On-Chips, Jun 2005, Montpellier, France. pp.169-176 |
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Current Mask Generation: A Transistor Level Security Against DPA AttacksSBCCI 2005 - 18th annual symposium on Integrated circuits and system design, Sep 2005, Florianolpolis, Brazil. pp.115-120, ⟨10.1145/1081081.1081114⟩ |
Automatic Task Scheduling/Loop Unrolling Using Dedicated RTR Controllers in Coarse Grain Recongigurable ArchitecturesIPDPS'05: International Parallel and Distributed Processing Symposium, RAW'05: Reconfigurable Architectures Workshop, Apr 2005, Denver, Colorado (USA), pp.148 |
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Current Mask Generation: A hardware Countermeasure Against DPA AttacksSBCCI'05: 18th Symposium on Integrated Circuits and Systems Design, Sep 2005 |
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Architectures de réseaux intégrés sur siliciumEPML'05: : Equipe Projet Multi-Laboratoires "Retards de Transmission et Télé-Opération" CNRS DSTIC, Jan 2005, Montpellier, France |
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Intégration d'un Coeur Reconfigurable dans un Composant SécuriséJNRDM 2005 - 8e Journées Nationales du Réseau Doctoral de Microélectronique, May 2005, Paris, France. pp.464-465 |
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A RTR Hardware Controller for DSP Kernel Scheduling in Coarse Grain Reconfigurable ArchitectureIPDPS'05: International Parallel and Distributed Processing SymposiumRAW'05: Reconfigurable Architectures Workshop, Apr 2005, pp.485-489 |
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A Mesh Based Network on Chip characterization : A GALS ApproachDCIS 2005 - 20th Conference on Design of Circuits and Integrated Systems, Nov 2005, Lisbonne, Portugal. pp.10-15 |
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Gestion Matérielle du Parallélisme pour les Architectures Reconfigurables à Grain EpaisJFAAA'05: Journées Francophones sur l'Adéquation Algorithme Architecture, Jan 2005, Dijon, France. pp.15-20 |
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Hardware Engines for Bus Encryption: a Survey of Existing TechniquesDATE 2005 - 8th Design, Automation and Test in Europe Conference and Exhibition, Mar 2005, Munich, Germany. pp.40-45, ⟨10.1109/DATE.2005.170⟩ |
Réseau d'interconnexion pour les systèmes sur pucesJNRDM'04: 7èmes Journées Nationales du Réseau Doctoral de Microélectronique, May 2004, Marseille, France. pp.451-453 |
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Network-on-Chip Powered Distributed Computing StructuresALCHEMY'04: Architectures, Languages and Compilers to Harness the End of Moore Years, Nov 2004, LRI (Laboratoire de Recherche en Informatique) Orsay, France |
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System On Chip (SOC) : Du Composant... au ComposantJournées Nationales du GDR et RTP Nanoélectronique, May 2004, Aussois, France |
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Réseaux d'interconnexion pour les systèmes sur Puce : le réseau HERMESSCS 2004 - Signaux, Circuits et Systèmes, Mar 2004, Monastir, Tunisia. pp.35-40 |
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Méthodologies et Métriques pour Architectures Reconfigurables DynamiquementWorkshop du Réseau Thématique Pluridisciplinaire System-On-Chip RTP SoC, May 2004, La Londe-les-Maures, France |
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Metrics for Digital Signal Processing Architectures Characterization: Remanence and ScalabilitySAMOS 2004 - 4th International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation, Jul 2004, Samos, Greece. pp.128-137 |
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Metrics for Reconfigurable Architectures Characterization: Remanence and ScalabilityIPDPS: International Parallel and Distributed Processing Symposium, Apr 2003, Nice, France. pp.176-180, ⟨10.1109/IPDPS.2003.1213324⟩ |
A Novel Approach for Architectural Model Characterization. An Example through the Systolic Ring.FPL 2003 - 12th International Workshop on Field-Programmable Logic and Applications, Sep 2003, Lisbon, Portugal. pp.722-732, ⟨10.1007/978-3-540-45234-8_70⟩ |
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Comparaison d'Architectures Dédiées au Traitement Numériques des Données : du Processeur aux Architectures ReconfigurablesRenPar/ SympAAA/ CFSE - Rencontres Francophones en Parallélisme, Architecture, Adéquation Algorithmes Architecture et Système, Oct 2003, La Colle sur Loup, France. pp.322-326 |
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Are Coarse Grain Reconfigurable Architectures Suitable for Cryptography?12th International Conference on Very Large Scale Integration of System-on-Chip (VLSI-SoC), Dec 2003, Darmstadt, Germany. pp.276-281 |
Comparaison des Architectures Dédiées au Traitement des Données NumériquesJNRDM'03 : 6ièmes Journées Nationales du Réseau Doctoral de Microélectronique, May 2003, Toulouse (France), France. pp.115-117 |
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Architectures Reconfigurables Dynamiquement pour Applications TSIColloque du GDR CAO de Circuits et Systèmes Intégrés, May 2002, Paris, France. pp.67-70 |
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Caractérisation et Comparaison d'Architectures Reconfigurables Dynamiquement, un exemple : Le Systolic RingJFAAA'02: Journées Francophones sur l'Adéquation Algorithme Architecture, Dec 2002, Monastir, Tunisie. pp.30-34 |
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Highly Scalable Dynamically Reconfigurable Systolic Ring-Architecture for DSP ApplicationDATE: Design, Automation and Test in Europe, Mar 2002, Paris, France. pp.553-566, ⟨10.1109/DATE.2002.998355⟩ |
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Efficient Edge AI Learning with Equilibrium Propagation: A Practical Solution For Gradient ComputationDAC 2026 - 63rd Design Automation Conference, Jul 2026, California, United States. |
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Energy-Efficiency Metric for Real-Time Monitoring of OpenMP Programs Executing on Multicore Systems13e Colloque National du GDR SoC², Jun 2019, Montpellier, France |
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Trace-driven simulation of multithreaded applications in gem52nd ARM Research Summit Workshop, Sep 2017, Cambridge, United Kingdom. , 2017 |
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Exploration of Magnetic RAM Based Memory Hierarchy for Multicore ArchitectureISVLSI: International Symposium on Very Large Scale Integration, Jul 2014, Tampa, FL, United States. pp.248-251, 2014, ⟨10.1109/ISVLSI.2014.29⟩ |
Multithreading for Compute Accelerators Through Distributed Shared Memory DesignDAC: Design Automation Conference, Jun 2014, San Francisco, United States. IEEE Design Automation Conference, 2014, Work-in-Progress Session |
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Multi-level MPSoC modeling for reducing software development cycleICECS: International Conference on Electronics, Circuits, and Systems, Dec 2013, Abu Dhabi, United Arab Emirates. 20th IEEE International Conference on Electronics, Circuits, and Systems, pp.489-492, 2013, ⟨10.1109/ICECS.2013.6815460⟩ |
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Self-adaptability in Multi-processor Embedded SystemsColloque GDR SoC-SiP, Jun 2009, Paris, France. 2009 |
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Distributed Pervasive Phylogenetic Application using a Bio-Inspired Agent FrameworkColloque GDR SoC-SiP, 2008, Paris, France. 2008 |
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Perplexus ProjectColloque du GDR SoC-SiP, 2007, Paris, France. 2007 |
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Towards Self-Adaptability a Scalable MP-SOC Architecture ApproachColloque du GDR SoC-SiP, 2007, Paris, France. 2007 |
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Emerging Non-Volatile Technologies for Runtime FPGA Configuration MemoryFPGA'07: Fifteenth ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, Monterey, CA, USA, ACM, pp.227, 2007 |
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Dynamic Hardware Multiplexing for Coarse Grain Reconfigurable ArchitecturesFPGA'05: ACM/SIGDA 9th International Symposium on Field Programmable Gate Arrays, Feb 2005, Monterey, CA, United States. ACM Press, 2005 |
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A Parallel Architecture for Software and Hardware ExplorationRECoSoC: Reconfigurable Communication Centric System-On-Chips, Jun 2005, Montpellier, France. 2005 |
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Packet-Switching Network-On-Chip Feature Exploration and CharacterizationRECoSoC'05: Reconfigurable Communication-Centric SoCs, Jun 2005, Montpellier, France. 2005 |
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Embedded Programmable Devices Using Magnetic RAM CellsEUSPEN: European Society for Precision Engineering and Nanotechnology, May 2005, Montpellier, France. 5th International Conference of the European Society for Precision Engineering and Nanotechnology, pp.337-340, 2005 |
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The Systolic Ring: A Scalable Dynamically Reconfigurable Core for Embedded SystemsSAME 2002 - Sophia-Antipolis Forum on MicroElectronics, Oct 2002, Sophia-Antipolis, France. pp.85-90, 2002 |
Selected Papers from the International Workshop on Reconfigurable Communication-centric Systems on Chips (ReCoSoC' 2010)Hindawi publishing corporation, pp.164, 2011 |
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Proceedings of the 2009 International Conference on Engineering of Reconfigurable Systems and AlgorithmsWORLDCOMP'09 CSREA Press ISBN : 1-60132-101-5, 340 p., 2009 |
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ReCoSoC'08: 4th International Workshop on Reconfigurable CommunicationIEEE Computer Society, pp.N/A, 2008, 978-84-691-3603-4 |
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ReCoSoC'07: Reconfigurable Communication-Centric SoCspp.CD-ROM, 2007 |
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Towards Autonomous Scalable Integrated SystemsDesign Technology for Heterogeneous Embedded Systems, Springer, pp.63-89, 2012, 978-94-007-1124-2. ⟨10.1007/978-94-007-1125-9_4⟩ |
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An Introduction to Multi-Core System on Chip - Trends and ChallengesHübner, Michael; Becker, Jürgen. Multiprocessor System-on-Chip - Hardware Design and Tool Integration, Springer, pp.1-21, 2011, Chapter 1, 978-1-4419-6459-5. ⟨10.1007/978-1-4419-6460-1_1⟩ |
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Embedded Systems Security for FPGA Security Trends for FPGAS |
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Countermeasures Against Physical Attacks in FPGAs Security Trends for FPGAS |
Current Mask Generation: An Analog Circuit to Thwart DPA AttacksVLSI-SoC: From Systems to Silicon, Springer, pp.317-330, 2007, 978-0-387-73660-0 |
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A Comparison of Two Approaches Providing Data Encryption and Authentication on a Processor Memory BusNadine Azémard, Philippe Maurine, Johan Vounckx. Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 4148/2006, Springer Berlin / Heidelberg, pp.267-279, 2006, Lecture Notes in Computer Science, 978-3-540-39094-7. ⟨10.1007/11847083_44⟩ |
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Dynamically Reconfigurable Architectures for Digital Signal Processing ApplicationsSOC Design Methodologies, 90, Kluwer Academic Publishers 2002, pp.63-74, 2002, IFIP — The International Federation for Information Processing, 978-1-4757-6530-4. ⟨10.1007/978-0-387-35597-9_6⟩ |
Data Processing System with Energy TransferFrance, Patent n° : FR20160053238. 2016 |
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Architecture de Transport de Données en Anneau comprenant un Réseau de RétropopagationFrance, N° de brevet: FR20020004162. 2002 |
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Architecture de Calcul Logique comprenant plusieurs Modes de ConfigurationFrance, N° de brevet: FR0204161. 2002 |
MultimodalBirdsAutre publication scientifique hal-05540404v1 |