Jean-Philippe Noel
24
Documents
Publications
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Intra-cell Resistive-Open Defect Analysis on a Foundry 8T SRAM-based IMC ArchitectureETS 2023 - 28th IEEE European Test Symposium, May 2023, Venise, Italy. ⟨10.1109/ETS56758.2023.10174107⟩
Communication dans un congrès
hal-04164663v1
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Binary ReRAM-based BNN first-layer implementation2023 Design, Automation & Test in Europe Conference & Exhibition (DATE), Apr 2023, Antwerp, Belgium. pp.1-6, ⟨10.23919/DATE56975.2023.10137057⟩
Communication dans un congrès
hal-04270562v1
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Analysis of Read Port Short Defects in an 8T SRAM-based IMC Architecture16e Colloque National du GDR SoC², Jun 2022, Strasbourg, France
Communication dans un congrès
lirmm-03990078v1
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A near-instantaneous and non-invasive erasure design technique to protect sensitive data stored in secure SRAMsESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference, Sep 2021, Grenoble, France. pp. 455-458, ⟨10.1109/ESSCIRC53450.2021.9567885⟩
Communication dans un congrès
cea-03605067v1
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Computational SRAM Design Automation using Pushed-Rule Bitcells for Energy-Efficient Vector Processing2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), Mar 2020, Grenoble, France. pp.1187-1192, ⟨10.23919/DATE48585.2020.9116506⟩
Communication dans un congrès
cea-02889406v1
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Reconfigurable tiles of computing-in-memory SRAM architecture for scalable vectorizationISLPED 2020: ACM/IEEE International Symposium on Low Power Electronics and Design, Aug 2020, Boston, MA, United States. pp.121-126, ⟨10.1145/3370748.3406550⟩
Communication dans un congrès
cea-02963719v1
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Memory Sizing of a Scalable SRAM In-Memory Computing Tile Based ArchitectureIFIP/IEEE International Conference on Very Large Scale Integration and System-on-Chip (VLSI-SoC), Oct 2019, Cuzco, Peru
Communication dans un congrès
cea-02399937v1
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Prospects for energy-efficient edge computing with integrated HfO 2-based ferroelectric devicesIFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SOC), Oct 2018, Verona, Italy. ⟨10.1109/VLSI-SoC.2018.8644809⟩
Communication dans un congrès
hal-01916992v1
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Smart Instruction Codes for In-Memory Computing Architectures Compatible with Standard SRAM InterfacesDesign, Automation and Test in Europe, Mar 2018, Dresde, Germany
Communication dans un congrès
cea-01757656v1
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Software Platform Dedicated for In-Memory Computing Circuit EvaluationRSP'17 (Rapid System Prototyping), Oct 2017, Séoul, South Korea. ⟨10.1145/3130265.3130322⟩
Communication dans un congrès
cea-01625320v1
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DRC 2 : Dynamically Reconfigurable Computing Circuit based on Memory Architecture IEEE International Conference on Rebooting Computing, Oct 2016, San Diego, France
Communication dans un congrès
cea-01376554v1
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Capacitor based SneakPath compensation circuit for transistor-less ReRAM architecturesProceedings of the 2016 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH), Jul 2016, Beijing, China. pp.7-12, ⟨10.1145/2950067.2950073⟩
Communication dans un congrès
hal-01435118v1
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SneakPath compensation circuit for programming and read operations in RRAM-based CrossPoint architectures2015 15th Non-Volatile Memory Technology Symposium (NVMTS), Oct 2015, Beijing, China. ⟨10.1109/NVMTS.2015.7457426⟩
Communication dans un congrès
hal-01745689v1
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Storage class memory with computing row buffer: A design space exploration2021, pp.1-6. ⟨10.23919/DATE51398.2021.9473992⟩
Autre publication scientifique
cea-03605068v1
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Smart Instruction Codes For In-Memory Computing Architectures Compatible With Standard Sram Interfaces2018
Autre publication scientifique
cea-01757665v1
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Optimisation de dispositifs FDSOI pour la gestion de la consommation et de la vitesse : application aux mémoires et fonctions logiquesAutre. Université de Grenoble, 2011. Français. ⟨NNT : 2011GRENT069⟩
Thèse
tel-00701765v2
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