
Loic Lagadec
133
Documents
Présentation
Publications
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Publications
Secure by design Systems on ChipCyber on Board, Naval-Group, May 2025, Hyères, France, France
Communication dans un congrès
hal-05077279
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Enforcing RISC-V TEE Security Against Cache Timing AttacksInternational Workshops on Cryptographic architectures embedded in logic devices, Jun 2025, Autrans (Grenoble), France
Communication dans un congrès
hal-05041492
v1
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Enhancing Keystone Security Against Cache Timing Attacks: A Modular ApproachColloque 2025 du GDR SoC2, Jun 2025, Lorient, France
Communication dans un congrès
hal-05056900
v1
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Software design patterns for a STRIDE approach on an AUV fleetCyber on Board, Naval-Group, May 2025, Hyères, France
Communication dans un congrès
hal-05077355
v1
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TrustSoC: Light and Efficient Heterogeneous SoC Architecture, Secure-by-design2023 Asian Hardware Oriented Security and Trust Symposium (AsianHOST), Dec 2023, Tianjin, China. pp.1-6, ⟨10.1109/AsianHOST59942.2023.10409311⟩
Communication dans un congrès
hal-04419064
v1
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Secured-by-design systems-on-chip: a MBSE ApproachRapid System Prototyping, Sep 2023, Hambourg, Germany. ⟨10.1145/3625223.3649277⟩
Communication dans un congrès
hal-04373771
v1
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TrustSoC : Architecture SoC hétérogène légère et efficace sécurisée par conceptionConférence francophone d’informatique en Parallélisme, Architecture et Système (COMPAS), LISTIC - Laboratoire d’Informatique, Systèmes, Traitement de l’Information et de la Connaissance, Jul 2023, Annecy, France
Communication dans un congrès
hal-04213598
v1
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Débogage Multivers de Modèles UMLAFADL, Jun 2023, Rennes, France
Communication dans un congrès
hal-04234535
v1
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Temporal Breakpoints for Multiverse DebuggingSoftware Language Engineering 2023, Oct 2023, Lisbonne, Portugal
Communication dans un congrès
hal-04234632
v1
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RISC-V Embedded AI for IDS ApplicationsRESSI 2024 : Rendez-vous de la Recherche et de l'Enseignement de la Sécurité des Systèmes d'Information, May 2024, Eppe-Sauvage, France
Communication dans un congrès
hal-04498047
v2
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Debugging Paxos in the UML MultiverseMODELS-C/MoDeVVa, Oct 2023, Västerås, Sweden
Communication dans un congrès
hal-04234688
v1
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JIT Compiler Security through Low-Cost RISC-V Extension30th Reconfigurable Architectures Workshop, May 2023, St Petersburg (Florida), United States
Communication dans un congrès
hal-04031296
v1
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Gigue: A JIT Code Binary Generator for Hardware TestingVMIL, Oct 2023, Cascais, Portugal. ⟨10.1145/3623507.3623553⟩
Communication dans un congrès
hal-04469651
v1
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Dolmen: FPGA Swarm for Safety and Liveness Verification2022 Design, Automation & Test in Europe Conference & Exhibition (DATE), Mar 2022, Antwerp, Belgium. pp.1425-1430, ⟨10.23919/DATE54114.2022.9774528⟩
Communication dans un congrès
hal-03708237
v1
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Practical multiverse debugging through user-defined reductionsMODELS '22: ACM/IEEE 25th International Conference on Model Driven Engineering Languages and Systems, Oct 2022, Montreal Quebec Canada, Canada. pp.87-97, ⟨10.1145/3550355.3552447⟩
Communication dans un congrès
hal-03891589
v1
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An Extended Modeling Approach for Marine/Deep-Sea ObservatoryThe 8th International Conference on Advanced Machine Learning and Technologies and Applications (AMLTA2022), May 2022, The Caire, Egypt. pp.502-514, ⟨10.1007/978-3-031-03918-8_42⟩
Communication dans un congrès
hal-03687138
v1
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Porting a JIT Compiler to RISC-V: Challenges and OpportunitiesProceedings of the 19th International Conference on Managed Programming Languages and Runtimes (MPLR '22), Sep 2022, Brussels, Belgium
Communication dans un congrès
hal-03725841
v1
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Benchmarking Quantized Neural Networks on FPGAs with FINNDATE Friday Workshop on System-level Design Methods for Deep Learning on Heterogeneous Architectures, Feb 2021, Grenoble, France
Communication dans un congrès
hal-03085342
v1
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Carnac: Algorithm Variability for Fast Swarm Verification on FPGA2021 31st International Conference on Field-Programmable Logic and Applications (FPL), Aug 2021, Dresden, Germany. pp.185-189, ⟨10.1109/FPL53798.2021.00038⟩
Communication dans un congrès
hal-03550389
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Prototyping FPGA through overlays2021 IEEE International Workshop on Rapid System Prototyping (RSP), Oct 2021, Paris, France. pp.15-21, ⟨10.1109/RSP53691.2021.9806222⟩
Communication dans un congrès
hal-03761788
v1
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Efficient Leader Election in Wireless Sensor and IoT Networks31st European Conference on Operational Research (EURO 2021), Jul 2021, Athens, Greece
Communication dans un congrès
hal-03410822
v1
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Menhir: Generic High-Speed FPGA Model-Checker2020 23rd Euromicro Conference on Digital System Design (DSD), Aug 2020, Kranj, Slovenia. pp.65-72, ⟨10.1109/DSD51259.2020.00022⟩
Communication dans un congrès
hal-03028409
v1
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Designing a combined personal communicator and data entry terminal for disaster relief & remote operationsIEEE Global Humanitarian Technology Conference (GHTC), Oct 2019, Seattle, WA, United States
Communication dans un congrès
hal-02553261
v1
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A New Leader Election Algorithm based on the WBS Algorithm Dedicated to Smart-cities3rd International Conference on Future Networks and Distributed Systems (ICFNDS '19), Jul 2019, Paris, France. pp.1-5, ⟨10.1145/3341325.3342014⟩
Communication dans un congrès
hal-02303247
v2
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Temperature-based models of batteries for the simulation of Wireless Sensor Networks3rd International Conferenceon on Future Networks and Distributed Systems, Jul 2019, Paris, France. pp.1-6, ⟨10.1145/3341325.3342013⟩
Communication dans un congrès
hal-02303250
v1
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Fast Evaluation of Homomorphic Encryption Schemes Based on Ring-LWE2018 9th IFIP International Conference on New Technologies, Mobility and Security (NTMS), Feb 2018, Paris, France. ⟨10.1109/NTMS.2018.8328693⟩
Communication dans un congrès
hal-01757093
v1
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Detecting Gaps and Voids in WSNs and IoT Networks: the Minimum x-Coordinate based MethodInternational Conference on Future Networks and Distr buted Systems (ICFNDS), Jun 2018, Amman, Jordan. ⟨10.1145/3231053.3231090⟩
Communication dans un congrès
hal-01829227
v1
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An Integrated Toolchain for Overlay-centric System-on-chip13th International Symposium on Reconfigurable Communication-centric Systems-on-Chip 2018 (ReCoSoC 2018), Jul 2018, Lille, France. ⟨10.1109/ReCoSoC.2018.8449388⟩
Communication dans un congrès
hal-01867638
v1
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CupCarbon-Lab: An IoT EmulatorIEEE Consumer Communications & Networking Conference, Jan 2018, Las Vegas, United States. ⟨10.1109/CCNC.2018.8319313⟩
Communication dans un congrès
hal-01704422
v1
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Detecting Gaps and Voids in WSNs and IoT Networks: the Angle-based MethodInternational Conference on Future Networks and Distributed Systems (ICFNDS), Jun 2018, Amman, Jordan. ⟨10.1145/3231053.3231089⟩
Communication dans un congrès
hal-01836035
v1
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DoTRo: A New Dominating Tree Routing Algorithm for Efficient and Fault-Tolerant Leader Election in WSNs and IoT Networks4th International Conference on Mobile, Secure and Programmable Networking (MSPN 2018), Jun 2018, Paris, France. pp.42-53
Communication dans un congrès
hal-01829251
v1
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Asserting causal properties in High Level Synthesis2017 IEEE 2nd International Verification and Security Workshop (IVSW), Jul 2017, Thessaloniki, Greece
Communication dans un congrès
hal-01623030
v1
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A High Abstraction Level Constraint for Object Localization in Marine ObservatoriesCSCI 2017, Dec 2017, Las Vegas, United States
Communication dans un congrès
hal-01653617
v1
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PAnTHErS: A Prototyping and Analysis Tool for Homomorphic Encryption SchemesSECRYPT: 14th International Conference on Security and Cryptography, Jul 2017, Madrid, Spain
Communication dans un congrès
hal-01595789
v1
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Soft timing closure for soft programmable logic cores: The ARGen approachARC 2017 - 13th International Symposium on Applied Reconfigurable Computing, Delft University of Technology Apr 2017, Delft, Netherlands
Communication dans un congrès
hal-01475251
v1
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A Cost-effective Approach for Efficient Time-sharing of Reconfigurable ArchitecturesFPGA4GPC'2017, May 2017, Hambourg, Germany. ⟨10.1109/FPGA4GPC.2017.8008959⟩
Communication dans un congrès
hal-01656613
v1
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Overlay Architectures For FPGA Resource VirtualizationGDR SOC SIP, Jun 2016, Nantes, France
Communication dans un congrès
hal-01405912
v1
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Speeding Up Robot Control Software Through Seamless Integration With FPGASHARC'16, Jun 2016, Brest, France
Communication dans un congrès
hal-01480221
v1
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Overlay Architectures for Heterogeneous FPGA Cluster Management.DASIP 2016, Oct 2016, Rennes, France
Communication dans un congrès
hal-01405890
v1
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ZeFF : Une plateforme pour l’intégration d’architectures overlay dans le CloudCOMPAS 2016, Jul 2016, Lorient, France
Communication dans un congrès
hal-01405860
v1
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CaRDIN: An Agile Environment for EdgeComputing on Reconfigurable Sensor Networks3rd IEEE International Conference on Computational Science and Computational Intelligence (CSCI 2016), Dec 2016, Las Vegas, United States
Communication dans un congrès
hal-01406641
v1
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Fast Prototyping of a New Reconfigurable Architecture : Toward Tailored Space FPGAConférence d’informatique en Parallélisme, Architecture et Système (Compas), Jun 2015, Villeneuve d'Ascq, France. pp.10
Communication dans un congrès
hal-01153568
v1
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A Meta Model Supporting both Hardware and Smalltalk-based Execution of FPGA CircuitsIWST 2015, ESUG, Jul 2015, Bressia, Italy. ⟨10.1145/2811237.2811296⟩
Communication dans un congrès
hal-01179466
v1
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A Role Language to Interpret Multi-Formalism System of Systems ModelsSyscon 2015, IEEE, Apr 2015, Vancouver, Canada
Communication dans un congrès
hal-01156518
v1
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Role Framework to Support Collaborative Virtual Prototyping of System of SystemsWETICE 2015, IEEE, Jun 2015, Larnaca, Cyprus
Communication dans un congrès
hal-01192720
v1
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A Design Approach to Automatically Generate On-Chip Monitors during High-Level Synthesis of Hardware AcceleratorGLSVLSI 2014, May 2014, Houston, United States
Communication dans un congrès
hal-01009551
v1
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FPGAs virtuels : enjeux et usagesCOMPAS 2014, Apr 2014, Neuchâtel, Switzerland
Communication dans un congrès
hal-00989984
v1
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From Smalltalk to Silicon: Towards a methodology to turn Smalltalk code into FPGAIWST 14, Aug 2014, Cambridge, United Kingdom
Communication dans un congrès
hal-01326520
v1
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A Prototyping Platform for Virtual Reconfigurable UnitsRECOSOC 2014, May 2014, Montpellier, France
Communication dans un congrès
hal-01006128
v1
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New reconfigurable fault tolerant FPGA architecture: A design for mission critical applicationsWorkshop on Reconfigurable Computing (WRC), Jan 2014, Vienne, Austria. pp.WRC 2014
Communication dans un congrès
hal-00921552
v1
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Design Approach to Automatically Synthesize ANSI-C Assertions during High-Level Synthesis of Hardware AcceleratorsICSAS 2014 - International symposium on circuits and systems, Jun 2014, Melbourne, Australia
Communication dans un congrès
hal-01009572
v1
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A Design Approach to Automatically Synthesize ANSI-C Assertions during High-Level Synthesis of Hardware AcceleratorsISCAS 2014 - IEEE International Symposium on Circuits and Systems, May 2014, Melbourne, Australia. pp.XX
Communication dans un congrès
hal-00944548
v1
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Une approche de conception pour générer automatiquement des moniteurs sur puce pendant la synthèse de haut niveau d'accélérateurs matérielsCOMPAS 2014 - Conférence en Parallélisme, Architecture et Système, Apr 2014, Neuchâtel, Suisse
Communication dans un congrès
hal-00989918
v1
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A Model-Driven Approach to Enhance Tool Interoperability using the Theory of Models of ComputationSLE 2013 - 6th International Conference on Software Language Engineering, Oct 2013, United States
Communication dans un congrès
hal-00912574
v1
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Fast Template-based Heterogeneous MPSoC Synthesis on FPGA9th Int. Symposium on Applied Reconfigurable Computing, Mar 2013, Los Angeles, United States
Communication dans un congrès
hal-00780378
v1
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Enhance the reusability of Models and their Behavioral correctnessMODELS 2013 - Workshop GEMOC, Sep 2013, Miami, United States
Communication dans un congrès
hal-00912587
v1
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A framework for high-level synthesis of heterogeneous MP-SoCGLSVLSI, May 2012, Salt Lake City, United States. pp.283-286, ⟨10.1145/2206781.2206850⟩
Communication dans un congrès
hal-00726481
v1
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Behavioral System Level Power Consumption Modeling of Mobile Video Streaming applicationsColloque du GDR SoC SiP, Jun 2012, Paris, France. pp.39
Communication dans un congrès
hal-00724988
v1
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HLS-based Fast Design Space Exploration of ad hoc hardware accelerators: a key tool for MPSoC Synthesis on FPGAInternational Conference on Design and Architectures for Signal and Image Processing (DASIP), Oct 2012, Germany
Communication dans un congrès
hal-00747713
v1
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Experiment centric teaching for reconfigurable processorSymposium en Architecture Nouvelle de Machines, May 2011, Saint Malo, France. pp.1-14
Communication dans un congrès
hal-00598843
v1
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Constititution d'une chaine d'outils pour une technologie reconfigurableSymposium en Architecture Nouvelle de Machines, May 2011, Saint Malo, France
Communication dans un congrès
hal-00598841
v1
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FPGA Physical-Design Automation using Model-Driven EngineeringRECOSOC, Jun 2011, Montpellier, France. pp.1-6
Communication dans un congrès
hal-00598838
v1
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Fast Prototyping Environment for Embedded Reconfigurable UnitsRECOSOC, Jun 2011, France. pp.1-8
Communication dans un congrès
hal-00598833
v1
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Regular 2D Nasic-based Architecture and Design Space ExplorationNANOARCH 2011, Jun 2011, San Diego, United States. pp.70-77
Communication dans un congrès
hal-00598850
v1
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FPGA SDK for Nanoscale ArchitecturesRECOSOC, Jun 2011, Montpellier, France. pp.1-8
Communication dans un congrès
hal-00598837
v1
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MDE-based FPGA Physical Design Fast Model-Driven Prototyping with SmalltalkIWST 2011, Aug 2011, Edinburgh, United Kingdom. pp.1-13
Communication dans un congrès
hal-00620820
v1
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Biniou: Prototypage d'architecture reconfigurable: Volet matériel et flot d'exploitationJournée du GDR Soc-Sip, Thème architectures reconfigurables, Jul 2011, Paris, France
Communication dans un congrès
hal-00598851
v1
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Smalltalk debug lives in the MatrixInternational Workshop on Smalltalk Technologies, Sep 2010, Barcelona, Spain. pp.1-10
Communication dans un congrès
hal-00508413
v1
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Flot ADL d'exploration et de prototypage d'architectures reconfigurablesColloque annuel du GDR Soc-Sip, 2010, Cergy pontoise, France
Communication dans un congrès
hal-00491881
v1
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Teaching reconfigurable computer : the Biniou approachReCoSoc 2010, 2010, Karlshrue, Germany. pp.127-134
Communication dans un congrès
hal-00491907
v1
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Virtual SoPC Rad-Hardening for Satellite ApplicationsReCoSoC'10, May 2010, Karlsruhe, Germany. 2 p
Communication dans un congrès
hal-00489327
v1
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Contribution du Lab-STICC au projet FP6 MorpheusColloque annuel du GDR Soc-SIP, 2009, Paris, France
Communication dans un congrès
hal-00487895
v1
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Software-Like Debugging Methodology for Reconfigurable PlatformsInternational Symposium on Parallel&Distributed Processing, 2009, Rome, European Union. pp.1-4, ⟨10.1109/IPDPS.2009.5161224⟩
Communication dans un congrès
hal-00487893
v1
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Présentation de l'Université de Bretagne Occidentale / Université Européenne de Bretagne et des activités du LAB-STICCFacultés des sciencs exactes, 2009, Béjaia, Algeria
Communication dans un congrès
hal-00492389
v1
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Spatial design backend : CDFG mapping on eFPGA and DREAM IPsAMWAS, 2008, Lugano, Switzerland
Communication dans un congrès
hal-00487900
v1
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MADEO : Object Oriented Programming, Modelization, and Tools for FPGASEuropean Smalltalk User Group, 2008, Amsterdam, Netherlands
Communication dans un congrès
hal-00487899
v1
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Multi-Level Simulation of Heterogeneous Reconfigurable PlatformsReCoSoC, 2008, Barcelone, France
Communication dans un congrès
hal-00487892
v1
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Building CAD tools as an Efficient Learning for both EE and CS studentsReconfigurable Computing Education, 2008, Montpellier, France
Communication dans un congrès
hal-00487891
v1
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Chaîne de programmation pour architecture hétérogène reconfigurableSYMPosium en Architectures nouvelles de machines, 2008, Fribourgh, Suisse
Communication dans un congrès
hal-00488899
v1
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On the Way to Design Computing Architectures with Emerging Nanoscale TechnologiesColloque annuel GDR-SOC-Sip, Jun 2008, Paris, France
Communication dans un congrès
hal-00380878
v1
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Building CAD Prototyping Tool for Emerging Nanoscale FabricsEuropean Nano Systems 2007, Dec 2007, Paris, France. pp.25-30
Communication dans un congrès
hal-00259374
v1
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CDFG Platform in MORPHEUSAETHER - MORPHEUS Workshop AMWAS'07, Oct 2007, Paris, France
Communication dans un congrès
hal-00487063
v1
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Synthesis in MorpheusAMWAS, 2007, Paris, France
Communication dans un congrès
hal-00487908
v1
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A layered methodology for fast deployment of new technologiesENS 2007, Dec 2007, Paris, France. pp.20-24
Communication dans un congrès
hal-00202506
v1
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Building CAD Prototyping Tool for Emerging Nanoscale FabricsENS 2007, Dec 2007, Paris, France. pp.25-30
Communication dans un congrès
hal-00202507
v1
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The Case Study of Block turbo Decoders on a Framework for Portable Synthesis on FPGA39th Hawaii International conference on System Sciences, 2006, United States. pp.250b
Communication dans un congrès
hal-00083395
v1
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Compiler level integration of a portable CAD framework for reconfigurable circuitsFirst ReCoSoc workshop, 2005, Montpellier, France
Communication dans un congrès
hal-00083730
v1
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Du reconfigurable aux nano-fabriques : composants nano-électroniques et outils de modélisationSympA'2005 : 8ème édition du symposium en architectures nouvelles de machines, 2005, France. pp.195-206
Communication dans un congrès
hal-00083254
v1
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Madeo, une approche MDA pour la programmation et la synthèse d'architectures reconfigurablesSympA'2005 : 8ème édition du symposium en architectures nouvelles de machines, 2005, Le Croisic, France. pp.1-12
Communication dans un congrès
hal-00083256
v1
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Compiler and system techniques for SOC distributed reconfigurable accelerators2004, pp.293-302
Communication dans un congrès
hal-00083035
v1
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Abstract Execution Mechanisms in a Synthesis Framework3rd Workshop on Non-Silicon computation (NSC3), 2004, Munich, Germany
Communication dans un congrès
hal-00083008
v1
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Outils génériques pour le reconfigurable: Applications aux architectures commerciales2003, pp.399-408
Communication dans un congrès
hal-00083016
v1
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Toward a CAD Tool for SYCL programmingIWOCL '23: International Workshop on OpenCL, Apr 2023, Cambridge, United Kingdom. ACM, pp.1-2, ⟨10.1145/3585341.3585358⟩
Poster de conférence
hal-04303747
v1
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Securing a High-Level Language Virtual Machine Through its ISA: Pharo as a Case StudyGDR SOC², Jun 2021, Rennes, France
Poster de conférence
hal-04542157
v1
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DoTRo: A New Dominating Tree Routing Algorithm for Efficient and Fault-Tolerant Leader Election in WSNs and IoT NetworksRenault É., Boumerdassi S., Bouzefrane S. (eds). Mobile, Secure, and Programmable Networking. MSPN 2018, 11005, Springer, Cham, pp.42-53, 2019, Lecture Notes in Computer Science, 978-3-030-03100-8. ⟨10.1007/978-3-030-03101-5_5⟩
Chapitre d'ouvrage
hal-02501870
v1
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Spatial DesignVoros, Nikolaos and Rosti, Alberto and Hübner, Michael (Eds.). Dynamic System Reconfiguration in Heterogeneous Platforms. The MORPHEUS Approach, Springer, chapter 13, 2009, Lecture Notes in Electrical Engineering, Vol. 40, ⟨10.1007/978-90-481-2427-5⟩
Chapitre d'ouvrage
hal-00484065
v1
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A LUT based high level synthesis framework for reconfigurable architecturesDomain-Specific Processors : Systems, Architectures, Modeling and Simulations, Marcel Dekker, pp.19-39, 2003
Chapitre d'ouvrage
hal-00084269
v1
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Procédé de configuration d'un circuit logique programmable, circuit logique programmable et dispositif pour implémenter le procédéFrance, N° de brevet: FR3115134. 2022
Brevet
hal-04032489
v1
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Support matériel pour la distribution de moteurs IA embarqués2ème conférence française annuelle dédiée à la cyber embarquée et à son écosystème (CyberOnBoard), 2025
Autre publication scientifique
hal-05041703
v1
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High-performance language virtual machines: an analysis and challenges2022
Autre publication scientifique
hal-03770053
v1
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Rapport et bilan pour le projet VALMADEO pour l'étape 32008
Autre publication scientifique
hal-00487350
v1
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Projet VALMADEO, étape 22007
Autre publication scientifique
hal-00487915
v1
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Rapport et bilan pour le projet VALMADEO pour étape 12006
Autre publication scientifique
hal-00487924
v1
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Hierarchical System of Digital Twins: A Holistic Architecture for Swarm System Analysis2025
Pré-publication, Document de travail
hal-04932447
v1
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SoSAF: A Pharo-Based Framework for Enhancing System of Systems Dependencies Analysis2024
Pré-publication, Document de travail
hal-04820422
v1
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Phadeo : un environnement pour FPGA virtuel2015
Pré-publication, Document de travail
hal-01179474
v1
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Remarkable Challenges of High-Performance Language Virtual Machines[Research Report] Inria Lille - Nord Europe. 2022
Rapport
hal-03770065
v1
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