Accéder directement au contenu

Marcello TRAIOLA

16
Documents

Présentation

I obtained my “laurea” degrees (BSc and MSc) in Computer Engineering - cum laude - both from the University of Naples “Federico II” , in Italy, in 2012 and 2016, respectively. In 2019, I obtained my Ph.D. degree in Computer Engineering from the University of Montpellier , working at the Laboratory of Computer Science, Robotics and Microelectronics of Montpellier (LIRMM) , in France. In 2013, I was at Fiat Chrysler Automobiles (now part of the group Stellantis ) Information Technology, Excellence and Methods S.p.A. (FCA ITEM), Pomigliano d’arco (Naples, Italy), as a software engineer intern. From October 2019 to January 2020, I was in the United States for a four-months internship at the semiconductor company MediaTek USA Inc , as an R&D engineer. From February 2020 to September 2021, I was with the Heterogeneous Systems Design team at the Lyon Institute of Nanotechnology (Institut des Nanotechnologies de Lyon, INL), in France, as a post-doctoral researcher. Since October 2021, I am with the TARAN research group (ex CAIRN) at the Inria research center at Rennes University , in France, first as a post-doctoral researcher and then as Inria permanent researcher (CRCN), since October 2022 My fields of research concern mainly emerging computing paradigms, with a focus on hardware digital design, testing, and reliability. I am an IEEE member.

Publications

"arnaud-virazel"
Image document

Emerging Computing Devices: Challenges and Opportunities for Test and Reliability

Alberto Bosio , Ian O'Connor , Marcello Traiola , Jorge Echavarria , Jürgen Teich
ETS 2021 - 26th IEEE European Test Symposium, May 2021, Bruges, Belgium. pp.1-10, ⟨10.1109/ETS50041.2021.9465409⟩
Communication dans un congrès lirmm-03379074v1
Image document

Reducing Overprovision of Triple Modular Reduncancy Owing to Approximate Computing

Bastien Deveautour , Marcello Traiola , Arnaud Virazel , Patrick Girard
IOLTS 2021 - 27th IEEE International Symposium on On-Line Testing and Robust System Design, Jun 2021, Torino, Italy. pp.1-7, ⟨10.1109/IOLTS52814.2021.9486699⟩
Communication dans un congrès lirmm-03380025v1
Image document

Design, Verification, Test and In-Field Implications of Approximate Computing Systems

Alberto Bosio , Stefano Di Carlo , Patrick Girard , Ernesto Sanchez , Alessandro Savino
ETS 2020 - 25th IEEE European Test Symposium, May 2020, Tallinn, Estonia. pp.1-10, ⟨10.1109/ETS48528.2020.9131557⟩
Communication dans un congrès lirmm-03035724v1
Image document

A Novel Test Flow for Approximate Digital Circuits

Marcello Traiola , Arnaud Virazel , Patrick Girard , Mario Barbareschi , Alberto Bosio
DATE 2020 - EDAA/IEEE/ACM Design Automation & Test in Europe Conference, PhD Forum, Mar 2020, Grenoble, France
Communication dans un congrès lirmm-03993654v1
Image document

Maximizing Yield for Approximate Integrated Circuits

Marcello Traiola , Arnaud Virazel , Patrick Girard , Mario Barbareschi , Alberto Bosio
DATE 2020 - 23rd Design, Automation and Test in Europe Conference and Exhibition, Mar 2020, Grenoble, France. pp.810-815, ⟨10.23919/DATE48585.2020.9116341⟩
Communication dans un congrès lirmm-03036002v1
Image document

QAMR: an Approximation-Based FullyReliable TMR Alternative for Area Overhead Reduction

Bastien Deveautour , Marcello Traiola , Arnaud Virazel , Patrick Girard
ETS 2020 - 25th IEEE European Test Symposium, May 2020, Tallinn, Estonia. pp.1-6, ⟨10.1109/ETS48528.2020.9131574⟩
Communication dans un congrès lirmm-03035640v1
Image document

On the Comparison of Different ATPG approaches for Approximate Integrated Circuits

Marcello Traiola , Arnaud Virazel , Patrick Girard , Mario Barbareschi , Alberto Bosio
DDECS 2018 - 1st International Symposium on Design and Diagnostics of Electronic Circuits and Systems, Apr 2018, Budapest, Hungary. pp.85-90, ⟨10.1109/DDECS.2018.00022⟩
Communication dans un congrès lirmm-03032856v1
Image document

Testing Approximate Digital Circuits: Challenges and Opportunities

Marcello Traiola , Arnaud Virazel , Patrick Girard , Mario Barbareschi , Alberto Bosio
LATS 2018 - 19th IEEE Latin American Test Symposium, Mar 2018, Sao Paulo, Brazil. pp.1-6, ⟨10.1109/LATW.2018.8349681⟩
Communication dans un congrès lirmm-03033024v1
Image document

Investigation of Mean-Error Metrics for Testing Approximate Integrated Circuits

Marcello Traiola , Arnaud Virazel , Patrick Girard , Mario Barbarcschi , Alberto Bosio
DFT 2018 - 31st IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, Oct 2018, Chicago, United States. pp.1-6, ⟨10.1109/DFT.2018.8602939⟩
Communication dans un congrès lirmm-02099895v1
Image document

Towards approximation during test of Integrated Circuits

Imran Wali , Marcello Traiola , Arnaud Virazel , Patrick Girard , Mario Barbareschi
DDECS 2017 - 20th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, Apr 2017, Dresden, Germany. pp.28-33, ⟨10.1109/DDECS.2017.7934574⟩
Communication dans un congrès lirmm-01718580v1
Image document

Can we Approximate the Test of Integrated Circuits?

Imran Wali , Marcello Traiola , Arnaud Virazel , Patrick Girard , Mario Barbareschi
WAPCO: Workshop On Approximate Computing, Jan 2017, Stockholm, Sweden
Communication dans un congrès lirmm-02004418v1

Towards digital circuit approximation by exploiting fault simulation

Marcello Traiola , Arnaud Virazel , Patrick Girard , Mario Barbareschi , Alberto Bosio
EWDTS: East-West Design & Test Symposium, Sep 2017, Novi Sad, Serbia. ⟨10.1109/EWDTS.2017.8110108⟩
Communication dans un congrès lirmm-01718583v1