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Marcello TRAIOLA
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Documents
Présentation
I obtained my “laurea” degrees (BSc and MSc) in Computer Engineering - cum laude - both from the University of Naples “Federico II” , in Italy, in 2012 and 2016, respectively.
In 2019, I obtained my Ph.D. degree in Computer Engineering from the University of Montpellier , working at the Laboratory of Computer Science, Robotics and Microelectronics of Montpellier (LIRMM) , in France.
In 2013, I was at Fiat Chrysler Automobiles (now part of the group Stellantis ) Information Technology, Excellence and Methods S.p.A. (FCA ITEM), Pomigliano d’arco (Naples, Italy), as a software engineer intern.
From October 2019 to January 2020, I was in the United States for a four-months internship at the semiconductor company MediaTek USA Inc , as an R&D engineer.
From February 2020 to September 2021, I was with the Heterogeneous Systems Design team at the Lyon Institute of Nanotechnology (Institut des Nanotechnologies de Lyon, INL), in France, as a post-doctoral researcher.
Since October 2021, I am with the TARAN research group (ex CAIRN) at the Inria research center at Rennes University , in France, first as a post-doctoral researcher and then as Inria permanent researcher (CRCN), since October 2022
My fields of research concern mainly emerging computing paradigms, with a focus on hardware digital design, testing, and reliability. I am an IEEE member.
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A Survey of Testing Techniques for Approximate Integrated CircuitsProceedings of the IEEE, 2020, 108 (12), pp.2178-2194. ⟨10.1109/JPROC.2020.2999613⟩
Article dans une revue
lirmm-02395609v1
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A Test Pattern Generation Technique for Approximate Circuits Based on an ILP-Formulated Pattern Selection ProcedureIEEE Transactions on Nanotechnology, 2019, 18, pp.849-857. ⟨10.1109/TNANO.2019.2923040⟩
Article dans une revue
lirmm-02395306v1
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Emerging Computing Devices: Challenges and Opportunities for Test and ReliabilityETS 2021 - 26th IEEE European Test Symposium, May 2021, Bruges, Belgium. pp.1-10, ⟨10.1109/ETS50041.2021.9465409⟩
Communication dans un congrès
lirmm-03379074v1
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Reducing Overprovision of Triple Modular Reduncancy Owing to Approximate ComputingIOLTS 2021 - 27th IEEE International Symposium on On-Line Testing and Robust System Design, Jun 2021, Torino, Italy. pp.1-7, ⟨10.1109/IOLTS52814.2021.9486699⟩
Communication dans un congrès
lirmm-03380025v1
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Design, Verification, Test and In-Field Implications of Approximate Computing SystemsETS 2020 - 25th IEEE European Test Symposium, May 2020, Tallinn, Estonia. pp.1-10, ⟨10.1109/ETS48528.2020.9131557⟩
Communication dans un congrès
lirmm-03035724v1
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A Novel Test Flow for Approximate Digital CircuitsDATE 2020 - EDAA/IEEE/ACM Design Automation & Test in Europe Conference, PhD Forum, Mar 2020, Grenoble, France
Communication dans un congrès
lirmm-03993654v1
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Maximizing Yield for Approximate Integrated CircuitsDATE 2020 - 23rd Design, Automation and Test in Europe Conference and Exhibition, Mar 2020, Grenoble, France. pp.810-815, ⟨10.23919/DATE48585.2020.9116341⟩
Communication dans un congrès
lirmm-03036002v1
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QAMR: an Approximation-Based FullyReliable TMR Alternative for Area Overhead ReductionETS 2020 - 25th IEEE European Test Symposium, May 2020, Tallinn, Estonia. pp.1-6, ⟨10.1109/ETS48528.2020.9131574⟩
Communication dans un congrès
lirmm-03035640v1
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On the Comparison of Different ATPG approaches for Approximate Integrated CircuitsDDECS 2018 - 1st International Symposium on Design and Diagnostics of Electronic Circuits and Systems, Apr 2018, Budapest, Hungary. pp.85-90, ⟨10.1109/DDECS.2018.00022⟩
Communication dans un congrès
lirmm-03032856v1
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Testing Approximate Digital Circuits: Challenges and OpportunitiesLATS 2018 - 19th IEEE Latin American Test Symposium, Mar 2018, Sao Paulo, Brazil. pp.1-6, ⟨10.1109/LATW.2018.8349681⟩
Communication dans un congrès
lirmm-03033024v1
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Investigation of Mean-Error Metrics for Testing Approximate Integrated CircuitsDFT 2018 - 31st IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, Oct 2018, Chicago, United States. pp.1-6, ⟨10.1109/DFT.2018.8602939⟩
Communication dans un congrès
lirmm-02099895v1
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Towards approximation during test of Integrated CircuitsDDECS 2017 - 20th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, Apr 2017, Dresden, Germany. pp.28-33, ⟨10.1109/DDECS.2017.7934574⟩
Communication dans un congrès
lirmm-01718580v1
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Can we Approximate the Test of Integrated Circuits?WAPCO: Workshop On Approximate Computing, Jan 2017, Stockholm, Sweden
Communication dans un congrès
lirmm-02004418v1
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Towards digital circuit approximation by exploiting fault simulationEWDTS: East-West Design & Test Symposium, Sep 2017, Novi Sad, Serbia. ⟨10.1109/EWDTS.2017.8110108⟩
Communication dans un congrès
lirmm-01718583v1
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Design, Verification, Test, and In-Field Implications of Approximate Digital Integrated CircuitsApproximate Computing Techniques, Springer International Publishing, pp.349-385, 2022, ⟨10.1007/978-3-030-94705-7_12⟩
Chapitre d'ouvrage
hal-03888027v1
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Test and Reliability of Approximate HardwareApproximate Computing, Springer International Publishing, pp.233-266, 2022, ⟨10.1007/978-3-030-98347-5_10⟩
Chapitre d'ouvrage
hal-03888016v1
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