Matthieu Moy
Présentation
Publications
Publications
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A Transistor Level Relational Semantics for Electrical Rule Checking by SMT SolvingDesign, Automation and Test in Europe Conference, Mar 2024, Valencia, Spain. pp.1-6, ⟨10.23919/DATE58400.2024.10546537⟩ |
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Electrical Rule Checking of Integrated Circuits using Satisfiability Modulo TheoryDATE 2023 - Design, Automation and Test in Europe Conference, Apr 2023, Anvers (Antwerpen), Belgium. pp.1-2, ⟨10.23919/DATE56975.2023.10137147⟩ |
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Affine Multibanking for High-Level SynthesisIMPACT'22 - 12th International Workshop on Polyhedral Compilation Techniques, Jun 2022, Budapest, Hungary |
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S4BXI: the MPI-ready Portals 4 SimulatorMASCOTS 2021 - 29th IEEE International Symposium on the Modeling, Analysis, and Simulation of Computer and Telecommunication Systems, Nov 2021, Houston, United States. pp.1-8, ⟨10.1109/MASCOTS53633.2021.9614285⟩ |
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Promise Plus: Flexible Synchronization for Parallel Computations on ArraysFSEN 2021 - 9th IPM International Conference on Fundamentals of Software Engineering, May 2021, Tehran, Iran. pp.1-7, ⟨10.1007/978-3-030-89247-0_13⟩ |
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Simulation of the Portals 4 protocol, and case study on the BXI interconnectHPCS 2020 - International Conference on High Performance Computing & Simulation, Dec 2020, Barcelona, Spain. pp.1-8 |
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Scaling Up the Memory Interference Analysis for Hard Real-Time Many-Core SystemsDATE 2020 - Design, Automation and Test in Europe Conference, Mar 2020, Grenoble, France. pp.1-4 |
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Standard-compliant parallel systemC simulation of loosely-timed Transaction Level ModelsASP-DAC 2020 - 25th Asia and South Pacific Design Automation Conference, Jan 2020, Beijing, China. pp.1-6, ⟨10.1109/ASP-DAC47756.2020.9045568⟩ |
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Response Time Analysis of Dataflow Applications on a Many-Core Processor with Shared-Memory and Network-on-ChipRTNS 2019 - 27th International Conference on Real-Time Networks and Systems, Nov 2019, Toulouse, France. pp.61-69, ⟨10.1145/3356401.3356416⟩ |
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Quels objets en NVRAM ? Placement en mémoires de travail hétérogènesCompas 2018 - Conférence d’informatique en Parallélisme, Architecture et Système, Jul 2018, Toulouse, France. pp.1-8 |
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Estimating the Impact of Architectural and Software Design Choices on Dynamic Allocation of Heterogeneous MemoriesRSP 2018 - 29th International Symposium on Rapid System Prototyping, Oct 2018, Turin, Italy. pp.1-7 |
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Parallel Code Generation of Synchronous Programs for a Many-core ArchitectureDATE 2018 - Design, Automation and Test in Europe, Mar 2018, Dresden, Germany. pp.1139-1142, ⟨10.23919/DATE.2018.8342182⟩ |
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Response Time Analysis of Synchronous Data Flow Programs on a Many-Core ProcessorRTNS, Nov 2016, Brest, France |
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SycView: Visualize and Profile SystemC Simulations3rd Workshop on Design Automation for Understanding Hardware Designs, DUHDe 2016, Mar 2016, Dresden, Germany |
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Efficient Execution of Dependent Tasks on Many-Core ProcessorsRTSOPS, Jul 2016, Toulouse, France |
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WCET analysis in shared resources real-time systems with TDMA busesRTNS 2015, Nov 2015, Lille, France. ⟨10.1145/2834848.2834871⟩ |
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Challenges for the Parallelization of Loosely Timed SystemC ProgramsIEEE International Symposium on Rapid System Prototyping, Oct 2015, Amsterdam, Netherlands |
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Co-Simulation of Functional SystemC TLM Models with Power/Thermal SolversVirtual Prototyping of Parallel and Embedded Systems (VIPES), May 2013, Boston, United States |
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Fast and Accurate TLM Simulations using Temporal Decoupling for FIFO-based CommunicationsDesign, Automation and Test in Europe (DATE), Mar 2013, Grenoble, France. pp.1185 |
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Parallel Programming with SystemC for Loosely Timed Models: A Non-Intrusive ApproachDATE, Mar 2013, Grenoble, France. pp.9 |
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System-Level Modeling of Energy in TLM for Early Validation of Power and Thermal ManagementDesign, Automation, and Test in Europe (DATE), Mar 2013, Grenoble, France. pp.1609 |
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PAGAI: a path sensitive static analyzerTools for Automatic Program AnalysiS (TAPAS 2012), Sep 2012, Deauville, France. pp.3, ⟨10.1016/j.entcs.2012.11.003⟩ |
Co-Simulation of a SystemC TLM Virtual Platform with a Power Simulator at the Architectural Level: Case of a Set-Top BoxDAC, Jun 2012, San Francisco, United States. pp.SESSION 10U: USER TRACK |
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Succinct Representations for Abstract InterpretationStatic analysis symposium (SAS), Sep 2012, Deauville, France. pp.283-299, ⟨10.1007/978-3-642-33125-1_20⟩ |
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Faithfulness Considerations for Virtual Prototyping of Systems-on-Chip3rd Workshop on: Rapid Simulation and Performance Evaluation: Methods and Tools, Jan 2011, Greece |
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Causality closure for a new class of curves in real-time calculusProceedings of the 1st International Workshop on Worst-Case Traversal Time, Nov 2011, Vienna, Austria. pp.3--10, ⟨10.1145/2071589.2071590⟩ |
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Efficient Encoding of SystemC/TLM in PromelaDATICS-IMECS, Mar 2011, Hong Kong SAR China |
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Modeling of Time in Discrete-Event Simulation of Systems-on-ChipMEMOCODE, Jul 2011, Cambridge, United Kingdom |
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Efficient and Playful Tools to Teach Unix to New StudentsITiCSE, Jun 2011, Darmstadt, Germany. pp.0 |
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Arrival Curves for Real-Time Calculus: the Causality Problem and its SolutionsTools and Algorithms for the Construction and Analysis of Systems, Mar 2010, Paphos, Cyprus. pp.358 |
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PinaVM: a SystemC Front-End Based on an Executable Intermediate RepresentationInternational Conference on Embedded Software, Oct 2010, Scottsdale, United States. pp.79 |
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Performance Evaluation of Components Using a Granularity-based Interface Between Real-Time Calculus and Timed Automata8th Workshop on Quantitative Aspects of Programming Languages, Mar 2010, Paphos, Cyprus. pp.166, ⟨10.4204/EPTCS⟩ |
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SystemC/TLM Semantics for Heterogeneous System-on-Chip Validation2008 Joint IEEE-NEWCAS and TAISA Conference, Jun 2008, Montréal, Canada |
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Automatic Generation of Schedulings for Improving the Test Coverage of Systems-on-a-ChipFormal Methods in Computer Aided Design (FMCAD'06), Nov 2006, San Jose, United States. pp.171-178, ⟨10.1109/FMCAD.2006.10⟩ |
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LusSy: A toolbox for the analysis of systems-on-a-chip at the transactional levelInternational Conference on Application of Concurrency to System Design (ACSD), Jun 2005, Saint-Malo, France. pp.26 - 35, ⟨10.1109/ACSD.2005.23⟩ |
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Pinapa: An extraction tool for systemc descriptions of systems-on-a-chipACM international conference on Embedded software, Jun 2005, New-York, United States. pp.317 - 324, ⟨10.1145/1086228.1086286⟩ |
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Electrical Rule Checking of Integrated Circuits using Satisfiability Modulo TheoryColloque du GDR SoC2, Jun 2023, Lyon, France |
Chapter "Formal VerificationFrank Ghenassia. Transaction-Level Modeling with SystemC. TLM Concepts and Applications for Embedded Systems, Springer, 15 p., 2005, ISBN: 0-387-26232-6 |
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A Theoretical and Experimental Review of SystemC Front-ends2010 |
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ac2lus: Bringing SMT-solving and Abstract Interpretation Techniques to Real-Time Calculus through the Synchronous Language Lustre2010 |
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A SystemC/TLM semantics in Promela and its Possible Applications2007 |
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Affine Multibanking for High-Level Synthesis[Research Report] RR-9440, Inria - Research Centre Grenoble – Rhône-Alpes. 2021 |
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Automatic translation of C/C++ parallel code into synchronous formalism using an SSA intermediate form[Research Report] RR-6976, INRIA. 2009, pp.16 |
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Techniques and Tools for the Verification of Systems-on-a-Chip at the Transaction LevelComputer Science [cs]. Institut National Polytechnique de Grenoble - INPG, 2005. English. ⟨NNT : ⟩ |
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Modélisation à haut niveau d'abstraction pour les systèmes embarquésSystèmes embarqués. Université de Grenoble, 2014 |