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MR
michel renovell
187
Documents
Researcher identifiers
michel-renovell-
0000-0002-3896-8231
- IdRef : 031539130
Presentation
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Dead-reckoning for marine animals: trade-offs between estimation accuracy and power consumptionBLS7 2021 - 7th International Bio-Logging Science Symposium, Oct 2021, Honolulu, United States
Conference papers
hal-03392214v1
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Impact of process variations on the detectability of resistive short defects: Comparative analysis between 28nm Bulk and FDSOI technologiesLATS 2018 - 19th IEEE Latin American Test Symposium, Mar 2018, Sao Paulo, Brazil. ⟨10.1109/LATW.2018.8349696⟩
Conference papers
lirmm-02064921v1
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Analysis of short defects in FinFET based logic cellsLATS 2017 - 18th IEEE Latin American Test Symposium, Mar 2017, Bogota, Colombia. ⟨10.1109/LATW.2017.7906755⟩
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hal-01709620v1
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Mitigating Read & Write Errors in STT-MRAM Memories under DVSETS: European Test Symposium, May 2017, Limassol, Cyprus. ⟨10.1109/ETS.2017.7968209⟩
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hal-01525720v1
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Detection of resistive open and short defects in FDSOI under delay-based test: Optimal VDD and body biasing conditionsETS: European Test Symposium, May 2017, Limassol, Cyprus. ⟨10.1109/ETS.2017.7968208⟩
Conference papers
hal-01709615v1
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Comprehensive Study for Detection of Weak Resistive Open and Short Defects in FDSOI TechnologyISVLSI: International Symposium on Very Large Scale Integration, Jul 2017, Bochum, Germany. pp.320-325, ⟨10.1109/ISVLSI.2017.63⟩
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hal-01709614v1
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Comparative study of Bulk, FDSOI and FinFET technologies in presence of a resistive short defectLATS: Latin-American Test Symposium, Mar 2016, Foz do Iguacu, Brazil. pp.129-134, ⟨10.1109/LATW.2016.7483352⟩
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lirmm-01374300v1
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Behavior and test of open-gate defects in FinFET based cellsETS: European Test Symposium, May 2016, Amsterdam, Netherlands. ⟨10.1109/ETS.2016.7519305⟩
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Mixed-level simulation tool for design optimization of electrical impedance spectroscopy systemsIWIS: International Workshop on Impedance Spectroscopy, Sep 2016, Chemnitz, Germany
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Impact of VT and Body-Biasing on Resistive short detection in 28nm UTBB FDSOI – LVT and RVT configurationsISVLSI: International Symposium on Very Large Scale Integration, Jul 2016, Pittsburgh, PA, United States. pp.164-169, ⟨10.1109/ISVLSI.2016.102⟩
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lirmm-01374292v1
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Toward adaptation of ADCs to operating conditions through on-chip correctionISVLSI: International Symposium on Very Large Scale Integration, Jul 2015, Montpellier, France. pp.634-639, ⟨10.1109/ISVLSI.2015.62⟩
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lirmm-01233117v1
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Power-aware voltage tuning for STT-MRAM reliabilityETS: European Test Symposium, May 2015, Cluj-Napoca, Romania. ⟨10.1109/ETS.2015.7138748⟩
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lirmm-01922971v1
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A framework for efficient implementation of analog/RF alternate test with model redundancyISVLSI: International Symposium on Very Large Scale Integration, Jul 2015, Montpellier, France. pp.621-626, ⟨10.1109/ISVLSI.2015.30⟩
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lirmm-01233104v1
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A generic methodology for building efficient prediction models in the context of alternate testingIMSTW: International Mixed-Signals Test Workshop, Jun 2015, Paris, France. ⟨10.1109/IMS3TW.2015.7177873⟩
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lirmm-01233150v1
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Investigations on alternate analog/RF test with model redundancySTEM Workshop, May 2014, Paderborn, Germany
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Evaluation of indirect measurement selection strategies in the context of analog/RF alternate testingLATW: Latin American Test Workshop, Mar 2014, Fortaleza, Brazil. ⟨10.1109/LATW.2014.6841930⟩
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Self-Adaptive NFC SystemsIOLTS: International On-Line Testing Symposium, Jul 2014, Platja d'Aro, Spain
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New implementions of predictive alternate analog/RF test with augmented model redundancyDATE 2014 - 17th Design, Automation and Test in Europe Conference and Exhibition, Mar 2014, Dresden, Germany. ⟨10.7873/DATE2014.144⟩
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lirmm-00994714v1
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Study of adaptive tuning strategies for Near Field Communication (NFC) transmitter moduleIMS3TW: International Mixed-Signals, Sensors, and Systems Test Workshop, Sep 2014, Porto ALegre, Brazil. ⟨10.1109/IMS3TW.2014.6997401⟩
Conference papers
lirmm-01119365v1
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Solutions for the self-adaptation of communicating systems in operationIOLTS: International On-line Test Symposium, Jul 2014, Platja d’Aro, Spain. pp.234-239, ⟨10.1109/IOLTS.2014.6873705⟩
Conference papers
hal-01118068v1
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Pre-characterization Procedure for a Mixed Mode Simulation of IR-Drop Induced DelaysLATW: Latin American Test Workshop, Apr 2013, Cordoba, Argentina. ⟨10.1109/LATW.2013.6562657⟩
Conference papers
lirmm-00820067v1
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A Comparative Analysis of Indirect Measurement Selection Strategies for Analog/RF Alternate Testing3rd IEEE International Workshop on Test and Validation of High Speed Analog Circuits, Sep 2013, Anaheim, CA, United States
Conference papers
lirmm-00985422v1
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MIRID: Mixed-Mode IR-Drop Induced Delay SimulatorATS: Asian Test Symposium, Nov 2013, Jiaosi Township, Taiwan. pp.177-182, ⟨10.1109/ATS.2013.41⟩
Conference papers
lirmm-00932357v1
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Accurate and Efficient Analytical Electrical Model of Antenna for NFC ApplicationsNEWCAS: New Circuits and Systems, Jun 2013, Paris, France. pp.137-141, ⟨10.1109/NEWCAS.2013.6573657⟩
Conference papers
lirmm-00839190v1
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On the use of redundancy to reduce prediction error in alternate analog/RF testIMS3TW: International Mixed-Signals, Sensors, and Systems Test Workshop, May 2012, Taipei, Taiwan. pp.34-39, ⟨10.1109/IMS3TW.2012.17⟩
Conference papers
lirmm-00803556v1
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Making predictive analog/RF alternate test strategy independent of training set sizeITC'2012: International Test Conference, Nov 2012, Anaheim, CA, United States. pp.9, ⟨10.1109/TEST.2012.6401560⟩
Conference papers
lirmm-00803564v1
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Smart selection of indirect parameters for DC-based alternate RF IC testingVTS: VLSI Test Symposium, Apr 2012, Hyatt Maui, HI, United States. pp.19-24, ⟨10.1109/VTS.2012.6231074⟩
Conference papers
lirmm-00803453v1
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An IR-Drop Simulation Principle Oriented to Delay TestingDCIS 2012 - 27th Conference on Design of Circuits and Integrated Systems, Nov 2012, Avignon, France. pp.404-409
Conference papers
lirmm-00804254v1
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Adaptive LUT-Based System for In Situ ADC Auto-correctionIMS3TW'10: 16th IEEE International Mixed-Signals, Sensors and Systems Test Workshop, La Grande Motte, Montpellier, France. pp.N/A
Conference papers
lirmm-00494424v1
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ANC-Based Method for Testing Converters with Random-Phase HarmonicsIMS3TW'10: 16th International Mixed-Signals, Sensors and Systems Test Workshop, La Grande Motte, Montpellier, France. pp.N/A
Conference papers
lirmm-00494578v1
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A Multi-Converter DFT Technique for Complex SIP: Concepts and ValidationECCTD: European Conference on Circuit Theory and Design, Aug 2009, Antalya, Turkey. pp.747-750
Conference papers
lirmm-00448863v1
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An Analysis of the Timing Behavior of CMOS Digital Blocks under Simultaneous Switching Noise ConditionsDDECS'09: IEEE Design and Diagnostics of Electronic Circuits and Systems, Apr 2009, Liberec, Czech Republic. pp.158-163
Conference papers
lirmm-00386906v1
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Influence of Gate Oxide Short Defects on the Stability of Minimal Sized SRAM Core-Cell by Applying Non-Split ModelsDTIS: Design and Technology of Integrated Systems in Nanoscale Era, 2009, Cairo, Egypt. pp.225-229
Conference papers
lirmm-00370798v1
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Analyzing the Impact of Simultaneous Switching Noise on the Timing Behavior of CMOS Digital BlocksLATW'09: 10th Latin-American Test Workshop, Mar 2009, Armaçao dos Buzios, Brazil, pp.N/A
Conference papers
lirmm-00367718v1
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LH-BIST for Digital Correction of ADC OffsetDTIS: Design and Technology of Integrated Systems in Nanoscale Era, 2009, Cairo, Egypt. pp.199-203
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lirmm-00375659v1
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Deriving an Electrical Model for Delay Faults Caused by Crosstalk Aggravated Resistive Short DefectsLATW'09: 10th Latin-American Test Workshop, Mar 2009, Armaçao dos Buzios, Brazil, pp.N/A
Conference papers
lirmm-00367708v1
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An Electrical Model for the Fault Simulation of Small Delay Faults Caused by Crosstalk Aggravated Resistive Short DefectsVTS'09: 27th VLSI Test Symposium, May 2009, Santa Cruz, Californie, United States. pp.21-26, ⟨10.1109/VTS.2009.57⟩
Conference papers
lirmm-00374941v1
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A Simulator of Small-Delay Faults Caused by Resistive-Open DefectsETS: European Test Symposium, May 2008, Verbania, Italy. pp.113-118
Conference papers
lirmm-00285886v1
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On the Detection of SSN-Induced Logic Errors Through On-Chip MonitoringIOLTS: International On-Line Testing Symposium, Jul 2008, Rhodes, Greece. pp.233-238, ⟨10.1109/IOLTS.2008.19⟩
Conference papers
lirmm-00294767v1
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A Model for Resistive Open Recursivity in CMOS Random LogicEWDTS: East-West Design & Test Symposium, Oct 2008, Lviv, Ukraine. pp.21-24
Conference papers
lirmm-00381465v1
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On-Chip Monitor for the Detection of Logic Errors due to Simultaneous Switching NoiseLATW'08: 9th Latin-American Test Workshop, Puebla, Mexico, pp.11-16
Conference papers
lirmm-00260194v1
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Analyzing the Logic Behavior of Digital CMOS Circuits in Presence of Simultaneous Switching NoiseLATW: Latin American Test Workshop, Mar 2007, Cuzco, Peru
Conference papers
lirmm-00199261v1
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SUPERB: Simulator Utilizing Parallel Evaluation of Resistive BridgesATS: Asian Test Symposium, Oct 2007, Beijing, China. pp.433-438
Conference papers
lirmm-00179272v1
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Impact of Simultaneous Switching Noise on the Static Behavior of Digital CMOS CircuitsATS: Asian Test Symposium, Oct 2007, Beijing, China. pp.239-244
Conference papers
lirmm-00179262v1
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System-in-Package, a Combination of Challenges and SolutionsETS: European Test Symposium, May 2007, Freiburg, Germany. pp.193-199
Conference papers
lirmm-00158123v1
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"Analogue Network of Converters": A DFT Technique to Test a Complete Set of ADCs and DACs Embedded in a Complex SiP or SOCETS: European Test Symposium, May 2007, Freiburg, Germany. pp.211-216, ⟨10.1109/ETS.2007.1⟩
Conference papers
lirmm-00158527v1
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Accessibility to Embedded A/MS Cores: An Oscillation-Based S-R DFTETS: European Test Symposium, May 2007, Freiburg, Germany. pp.77-81
Conference papers
lirmm-00158961v1
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Fully-Efficient ADC Test Technique for ATE with Low Resolution Arbitrary Wave GeneratorsIMSTW'07: International Mixed-Signals Testing Workshop and 3rd International GHz/Gbps Test Workshop, Jun 2007, Povoa de Varzim, Portugal. pp.196-201
Conference papers
lirmm-00161708v1
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A Specific ATPG Technique for Resistive Open with Sequence Recursive DependencyATS: Asian Test Symposium, Nov 2006, Fukuoka, Japan. pp.273-278, ⟨10.1109/ATS.2006.261031⟩
Conference papers
lirmm-00117022v1
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Testing for Realistic Spot Defects in CMOS Technology: a Unified ViewEWDTW: East-West Design & Test Workshop, Sep 2006, Sochi, Russia
Conference papers
lirmm-00096254v1
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State of the art in soc testing: The analog challengeDTIS: Design and Technology of Integrated Systems in Nanoscale Era, 2006, Tunis, Tunisia
Conference papers
lirmm-00407019v1
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“Analogue Network of Converters”: A DFT Technique to Test a Complete Set of ADCs and DACs Embedded in a Complex SiP or SOCETS: European Test Symposium, May 2006, Southampton, United Kingdom. pp.159-164
Conference papers
lirmm-00115676v1
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Delta-Iddq Testing of Resistive Short DefectsATS: Asian Test Symposium, Nov 2006, Fukuoka, Japan. pp.63-68
Conference papers
lirmm-00117020v1
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Experimental Validation of the "Analogue Network of Converters" Technique to Test Complex SiP/SoCIEEE International Mixed-Signal Testing Workshop, Jun 2006, Paris, France. pp.84-88
Conference papers
lirmm-00119266v1
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Analysing the Memory Effect of Resistive Open in CMOS Random LogicDTIS: Design and Technology of Integrated Systems in Nanoscale Era, 2006, Tunis, Tunisia. pp.251-256
Conference papers
lirmm-00093383v1
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Electrical Behavior of GOS Fault Affected Domino Logic CellDELTA'06: IEEE International Workshop on Electronics DesignTest & Applications, Jan 2006, Kuala Lumpur, Malaysia, pp.183-189
Conference papers
lirmm-00102703v1
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Modeling Halo Implant Failures in MOS Sub-Micron TechnologyLATW: Latin American Test Workshop, Mar 2005, Salvador, Bahia, Brazil. pp.29-33
Conference papers
lirmm-00106513v1
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A Set of Test Configurations for the Global Routing of Hierarchical SRAM-Based FPGAIBERCHIP, 2005, Salvador da Bahía, Brazil. pp.277-280
Conference papers
lirmm-00106512v1
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Electrical Behavior of GOS Faults in Domino LogicDDECS'05: IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, Apr 2005, Sopron, Hungary, pp.210-215
Conference papers
lirmm-00105991v1
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The Transient Reponse Analysis Method Applied to the Test of Field Programmable Analog Arrays: Feasibility StudyLATW: Latin American Test Workshop, Mar 2005, Salvador, Brazil. pp.252-257
Conference papers
lirmm-00106518v1
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Testing the Interconnect Networks and I/O Resources of Field Programmable Analog ArraysVTS: VLSI Test Symposium, May 2005, Palm Springs, CA, United States. pp.389-400, ⟨10.1109/VTS.2005.85⟩
Conference papers
lirmm-00105998v1
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Resistive Bridge Fault Model Evolution From Conventional to Ultra Deep Submicron TechnologiesVTS'05: 23rd IEEE VLSI Test Symposium, May 2005, Palm Springs, CA (USA), pp.343-348
Conference papers
lirmm-00105997v1
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Analysis and Attenuation Proposal in Ground Bounce: IILATW: Latin American Test Workshop, Mar 2005, Salvador, Bahia, Brazil. pp.34-39
Conference papers
lirmm-00106514v1
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Electrical Analysis of a Domino Logic Cell with GOS FaultsDBT'05: International Workshop on Current & Defect Based Testing, May 2005, Palm Springs, CA, United States
Conference papers
lirmm-00374937v1
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Fast and Fully-Efficient Test Flow for ADCsIMSTW'05: 11th IEEE International Mixed-Signal Testing Workshop, Jun 2005, Cannes, pp.244-249
Conference papers
lirmm-00106523v1
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The Pros and Cons of Very-Low-Voltage Testing: An Analysis Based on Resistive Bridging FaultsGI/ITG Workshop Testmethoden und Zuverlassigkeit von Schaltungen und Systemen, Feb 2004, Dresden, Germany. pp.149-153
Conference papers
lirmm-00108660v1
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BIST of Delay Faults in the Logic Architecture of Symmetrical FPGAsIOLTS: International On-Line Testing Symposium, Jul 2004, Madeira Island, Portugal. pp.187-192, ⟨10.1109/OLT.2004.1319686⟩
Conference papers
lirmm-00108824v1
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Testing the Configurable Analog Blocks of Field Programmable Analog ArraysITC: International Test Conference, Oct 2004, Charlotte, United States. pp.893-902
Conference papers
lirmm-00108897v1
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Manufacturing-Oriented Testing of Delay Faults in the Logic Architecture of Symmetrical FPGAsETS: European Test Symposium, May 2004, Ajaccio, Corsica, France. pp.117-122
Conference papers
lirmm-00108905v1
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Scan design and secure chip [secure IC testing]IOLTS: International On-Line Testing Symposium, Jul 2004, Madeira Island, Portugal. pp.219-224, ⟨10.1109/OLT.2004.1319691⟩
Conference papers
lirmm-00108909v1
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Automatic Test Pattern Generation for Resistive Bridging FaultsIEEE International Workshop on Current and Defect-Based Testing, May 2004, Napa Valley, CA, pp.89-94
Conference papers
lirmm-00108661v1
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An Approach to the Built-in-Self of Field Programmable Analog ArraysVTS: VLSI Test Symposium, Apr 2004, Napa Valley, CA, United States. pp.383-388
Conference papers
lirmm-00108908v1
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Digital and Analog System Testing: Fundamentals and New ChallengesICM 2004 - 16th International Conference on Microelectronics, Dec 2004, Tunis, Tunisia. pp.8-10, ⟨10.1109/ICM.2004.1434191⟩
Conference papers
lirmm-00108936v1
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A Multi-Configuration Strategy for an Application Dependant Testing of FPGAsVTS: VLSI Test Symposium, Apr 2004, Napa Valley, CA, United States. pp.154-159, ⟨10.1109/VTEST.2004.1299239⟩
Conference papers
lirmm-00108844v1
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The Pros and Cons of Very-Low-Voltage Testing: An Analysis Based on Resistive Bridging FaultsVTS'04: 22nd IEEE VLSI Test Symposium, Apr 2004, Napa Valley, CA (USA), pp.171-178
Conference papers
lirmm-00108845v1
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Automatic Test Pattern Generation for Resistive Bridging FaultsETS: European Test Symposium, May 2004, Ajaccio, Corsica, France. pp.160-165
Conference papers
lirmm-00108902v1
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Impact of Gate Oxide Reduction Failure on Analog Applications: Example of the Current MirrorLATW: Latin American Test Workshop, Mar 2004, Cartagena, Spain. pp.12-17
Conference papers
lirmm-00108659v1
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Principe et Problèmatique pour le Test des System-0n-ChipSCS'04: SignauxCircuits et Systèmes, Mar 2004, Monastir (Tunisie), pp.1-3
Conference papers
lirmm-00108842v1
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Realistic Fault Models for Defects in Electronic CircuitsBEC'04: International Baltic Electronic Conference, Oct 2004, pp.33-37
Conference papers
lirmm-00109134v1
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Testing Global Interconnects of Field Programmable Analog ArraysIMSTW'04: 10th International Mixed-Signal Testing Workshop, Jun 2004, Portland, Oregon, United States
Conference papers
lirmm-00108657v1
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High Quality TPG for Delay Faults in Look-Up Tables of FPGAsDELTA'04: 2nd International Workshop on Electronic DesignTest and Applications, Jan 2004, Perth (Australia), pp.83-88
Conference papers
lirmm-00108830v1
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Fundamentals of System Testing: Challenges for System-On-ChipsICM'04: 16th International Conference on Microelectronics, Dec 2004, P., France. pp.176-180
Conference papers
lirmm-00109135v1
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Analysis and Attenuation Proposal in Ground BounceATS: Asian Test Symposium, Nov 2004, Kenting Taiwan. pp.460-463, ⟨10.1109/ATS.2004.25⟩
Conference papers
lirmm-00108931v1
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A New Methodology for ADC Test Flow OptimizationITC: International Test Conference, Sep 2003, Charlotte, NC, United States. pp.201-209, ⟨10.1109/TEST.2003.1270841⟩
Conference papers
lirmm-00269527v1
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Requirements for Delay Testing of Look-Up Tables in SRAM-Based FPGAsETW: European Test Workshop, May 2003, Maastricht, Netherlands. pp.147-152
Conference papers
lirmm-00269530v1
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GOSMOS: A Gate Oxide Short Defect Embedded in a MOS Compact ModelLATW: Latin American Test Workshop, Feb 2003, Natal, Brazil
Conference papers
lirmm-00269604v1
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On the Efficiency of Measuring ADC Dynamic Parameters to Detect ADC Static ErrorsLATW: Latin American Test Workshop, Feb 2003, Natal, Brazil. pp.198-203
Conference papers
lirmm-00269498v1
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Simulating Resistive Bridging and Stuck-At FaultsITC 2003 - IEEE International Test Conference, Sep 2003, Charlotte, NC, United States. pp.1051-1059, ⟨10.1109/TCAD.2006.871626⟩
Conference papers
lirmm-00269611v1
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An Automatic Tool for Generation of ADC BIST ArchitectureIMSTW: International Mixed-Signal Testing Workshop, Jun 2003, Sevilla, Spain. pp.79-84
Conference papers
lirmm-00269580v1
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Automatic Generation of LH-BIST Architecture for ADC TestingIWADC'03: IEEE International Workshop on ADC Modelling and Testing, Sep 2003, Perugia, Italy. pp.7-12
Conference papers
lirmm-00269683v1
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Testing Challenges for Modern FPGAsECS: Electronic Circuits and Systems, Sep 2003, Bratislava, Slovenia. pp.1-9
Conference papers
lirmm-00269565v1
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On the Synthesis of Analog Cascaded Filters with Optimal Test Point InsertionLATW: Latin American Test Workshop, Feb 2003, Natal, Brazil. pp.212-216
Conference papers
lirmm-00269499v1
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Structural Testing of Modern Reconfigurable ChipsEWDTC 2003 - East-West Design & Test Conference, Sep 2003, Moscou, Russia. pp.5-9
Conference papers
lirmm-00269648v1
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Timing Defect Analysis in Look-Up Tables of SRAM-Based FPGAsLATW: Latin American Test Workshop, Feb 2003, Natal, Brazil. pp.26-31
Conference papers
lirmm-00269497v1
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Conditions pour le Test de Pannes de Délai des Look-Up Table dans les FPGA à Base de SRAMJNRDM: Journées Nationales du Réseau Doctoral de Microélectronique, May 2003, Toulouse, France. pp.381-383
Conference papers
lirmm-00269544v1
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Defect Analysis for Delay-Fault BIST in FPGAsIOLTS: International On-Line Testing Symposium, Jul 2003, Kos, Greece. pp.124-128, ⟨10.1109/OLT.2003.1214378⟩
Conference papers
lirmm-00269553v1
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OBIST Applied to FPAAs: A Case StudyLATW 2003 - 4th IEEE Latin American Test Workshop, Feb 2003, Natal, Brazil. pp.238-243
Conference papers
lirmm-00269501v1
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Hard to Detect Bridging Defects in a Cross-Point Digital SwitchLATW: Latin American Test Workshop, Feb 2003, Natal, Brazil. pp.12-18
Conference papers
lirmm-00269496v1
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Delay Testing of MOS Transistor with Gate Oxide ShortATS: Asian Test Symposium, Nov 2003, Xian, China. pp.168-173
Conference papers
lirmm-00269641v1
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Analysis of the Specification Influence on the Efficiency of an Optimized Test Flow for ADCsIMSTW: International Mixed-Signal Testing Workshop, Jun 2003, Sevilla, Spain. pp.185-190
Conference papers
lirmm-00269583v1
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Designing Testable Analog Filters with Optimal DFT InsertionIMSTW: International Mixed-Signal Testing Workshop, Jun 2002, Montreux, Switzerland. pp.201-203
Conference papers
lirmm-00269341v1
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Evaluation of ADC Static Parameters via Frequency DomainIMSTW'02: 8th IEEE International Mixed-Signal Testing Workshop, Jun 2002, Montreux, Switzerland. pp.165-169
Conference papers
lirmm-00269347v1
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Modeling Gate Oxide Short Defects in CMOS Minimum TransistorsETW: European Test Workshop, 2002, Corfu, Greece. pp.15-20
Conference papers
lirmm-00268527v1
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Implementation of an Experimental IEEE 1149.4 Mixed-Signal Test ChipBTW 2002 - 1st IEEE International Board Test Workshop, Oct 2002, Baltimore, United States. paper 4.2
Conference papers
lirmm-00269342v1
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Experimental test infrastructure supporting IEEE 11494 StandardETW: European Test Workshop, 2002, Corfou, Greece
Conference papers
lirmm-00268606v1
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Testing the Unidimensionnal Interconnect Architecture of Symmetrical SRAM-based FPGADELTA: Electronic Design, Test and Applications, Jan 2002, Christchurch, New Zealand. pp.297-301, ⟨10.1109/DELTA.2002.994634⟩
Conference papers
lirmm-00268528v1
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On the Evaluation of ADC Static Parameters Through Dynamic TestingADDA & EWADC, Jun 2002, Prague, Czech Republic. pp.95-98
Conference papers
lirmm-00269338v1
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Mesure des Paramètres Statiques des Convertisseurs A/N par une Analyse SpectraleColloque du GDR CAO de Circuits et Systèmes Intégrés, May 2002, Paris, France. pp.47-50
Conference papers
lirmm-00269325v1
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A New FPGA for DSP Applications Integrating BIST CapabilitiesLATW'02: 3rd IEEE Latin American Test Workshop, Feb 2002, Montevideo, Uruguay. pp.76-81
Conference papers
lirmm-00269328v1
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Estimating Static Parameters of A-to-D Converters from Spectral AnalysisLATW: Latin American Test Workshop, Feb 2002, Montevideo, Uruguay. pp.174-179
Conference papers
lirmm-00269320v1
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A high accuracy triangle-wave signal generator for on-chip ADC testingETW 2002 - 7th IEEE European Test Workshop, May 2002, Corfu, Greece. pp.89-94, ⟨10.1109/ETW.2002.1029644⟩
Conference papers
lirmm-00268483v1
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Low Voltage Testing of Gate Oxide Short in CMOS TechnologyDDECS: Design and Diagnostics of Electronic Circuits and Systems, 2002, Brno, Czech Republic. pp.168-174
Conference papers
lirmm-00268526v1
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A Non-Split Model for Realistic Gate Oxide Short in CMOS TechnologyDCIS: Design of Circuits and Integrated Systems, 2002, Santander, Spain. pp.197-204
Conference papers
lirmm-00268432v1
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Non-Linear and Non-Split Transistor MOS Model for Gate Oxyde ShortDBT: Defect Based Testing, Apr 2002, Monterey, CA, United States. pp.11-16
Conference papers
lirmm-00269333v1
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Pannes Temporelles dans les FPGAColloque du GDR CAO de Circuits et Systèmes Intégrés, May 2002, Paris, France. pp.43-46
Conference papers
lirmm-00269327v1
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Boolean and Current Detection of MOS Transistor with Gate Oxide ShortIEEE International Test Conference, Oct 2001, Baltimore, USA, pp.10
Conference papers
lirmm-00370400v1
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A built-in multi-mode stimuli generator for analogue and mixed-signal testingBrazilian Symposium on Integrated Circuit Design, 1998, Rio de Janeiro, Brazil. pp.175-178, ⟨10.1109/SBCCI.1998.715435⟩
Conference papers
hal-00005876v1
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From dependable computing systems to computing for integrated dependable systems?FTCS: Fault-Tolerant Computing Symposium, Jun 1998, Munich, Germany. pp.296-301, ⟨10.1109/FTCS.1998.689480⟩
Conference papers
hal-00013844v1
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A multi-mode stimuli generator for analogue and mixed-signal built-in-self-testIMSTW: International Mixed Signal Testing Workshop, Jun 1998, The Hague, Pays-Bas. pp.100-106
Conference papers
hal-01384740v1
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A multi-mode signature analyzer for analog and mixed circuitsVLSI: Integrated Systems on Silicon, Aug 1997, Gramado, Brazil. pp.65-76, ⟨10.1007/978-0-387-35311-1_6⟩
Conference papers
hal-01399998v1
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Implementing model redundancy in predictive alternate test to improve test confidenceETS: European Test Symposium, May 2013, Avignon, France. 18th IEEE European Test Symposium, 2013, ⟨10.1109/ETS.2013.6569386⟩
Conference poster
lirmm-00820077v1
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Influence of Parasitic Memory Effect on Single-Cell Faults in SRAMsDDECS'11: 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits ans Systems, Germany. pp.159-162, 2011
Conference poster
lirmm-00591995v1
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Logic Errors in CMOS Circuits due to Simultaneous Switching NoiseETS: European Test Symposium, May 2007, Freiburg, Germany. 12th IEEE European Test Symposium, pp.59-64, 2007
Conference poster
lirmm-00154744v1
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First International Conference on Embedded Systems and Critical Applications (ICESCA 2008)2008
Books
lirmm-00342663v1
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International Conference on Design and Test of Integrated Systems in Nanoscale Technology (DTIS 2006)IEEE, 447 p., 2006, 0-7803-9726-6. ⟨10.1109/DTIS.2006.1708761⟩
Books
lirmm-00136926v1
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Test de Circuits et de Systèmes IntégrésCollection EGEM, Ed.Hermès, 2004, 2-7462-0864-4
Books
lirmm-00109158v1
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The First IEEE International Workshop on Electronic Design, Test and Applications (DELTA 2002)IEEE Computer Society, 2002, 0-7695-1453-7
Books
lirmm-00268664v1
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Field-Programmable Logic and Applications: Reconfigurable Computing Is Going MainstreamSpringer, 2438, 2002, Lecture Notes in Computer Science, 978-3-540-44108-3. ⟨10.1007/3-540-46117-5⟩
Books
lirmm-00268656v1
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Mixed-level simulation tool for design optimization of electrical impedance spectroscopy systemsKanoun, Olfa. Impedance Spectroscopy
Book sections
lirmm-02007013v1
Advanced Applications: Battery Research, Bioimpedance, System Design, Walter de Gruyter, pp.71-80, 2018, 9783110558920. ⟨10.1515/9783110558920-008⟩ |
Models for Bridging DefectsModels in Hardware Testing, 43, Springer Netherlands, pp.33-70, 2010, Frontiers in Electronic Testing, 978-90-481-3281-2
Book sections
lirmm-00371365v1
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SIP Test ArchitecturesMorgan Kaufmann Publishers. System-on-chip Test Architectures: Nanometer Design for Testability, Elsevier, pp.405-441, 2007, 978-0-12-373973-5
Book sections
lirmm-00195243v1
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On-Chip Generator of a Saw-Tooth Test Stimulus for ADC BISTSOC Design Methodologies, 90, Kluwer Academic Publishers, pp.425-436, 2002, IFIP — The International Federation for Information Processing, 978-1-4757-6530-4. ⟨10.1007/978-0-387-35597-9_36⟩
Book sections
lirmm-00268477v1
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Contrat Nano TEST 2A702, Programme CEE MEDEA (Rapport Intermédiaire)08027, 2008
Reports
lirmm-00344415v1
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Contrat Nano TEST 2A702, Programme CEE MEDEA (Rapport Technique de fin d'année)08026, 2008
Reports
lirmm-00344408v1
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A Compact Model for Electrical Simulation of MOS Transistor with Gate Oxide Short Defect[Research Report] 04080, Lirmm, University of Montpellier. 2004
Reports
lirmm-00109221v1
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