
Michel Robert
Présentation
Michel ROBERT (PhD:1987) is Professor at the University of Montpellier (France), where he’s teaching microelectronics in the engineering program. His present research interests at the Montpellier Laboratory of Informatics, Robotics, and Micro-electronics (LIRMM) are design and modelisation of system on chip architectures. He is author or co-author of more than 300 publications in the field of CMOS integrated circuits design. He has supervised around forty doctoral thesis. He chaired the IFIP WG 10.5 (International Federation for Information Processing) from 2007 to 2011.
He served as director of the doctoral school, of the LIRMM research laboratory, then of the laboratory of excellence for digital solutions and modeling for the environment and the living, before becoming president of the University of Montpellier (2012-2015). He has held various national responsibilities in monitoring and evaluation in higher education and research. He was Director of the Institutional Evaluation Department of the High Council for the Evaluation of Research and Higher Education (Hcéres) from 2016 to 2021.
Publications
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The Meaning of Assessment in Higher Education and ResearchSBC/SBMicro/CASS-RS Special Event, IEEE CASS Rio Grande do Sul Chapter, Jun 2021, Rio Grande, Brazil
Communication dans un congrès
lirmm-03279878
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L’impact énergétique des flux de données numériquesColloque Energie du CNRS, Cellule énergie du CNRS, Dec 2021, Paris, France
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hal-03521821
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Exploration of Energy-Proportional Distributed Systems13e Colloque National du GDR SoC², Jun 2019, Montpellier, France
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hal-03326292
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Full-System Simulation of big.LITTLE Multicore Architecture for Performance and Energy ExplorationMCSoC: Embedded Multicore/Many-core Systems-on-Chip, Sep 2016, Lyon, France. pp.201-208, ⟨10.1109/MCSoC.2016.20⟩
Communication dans un congrès
lirmm-01418745
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OpenMP scheduling on ARM big.LITTLE architectureMULTIPROG 2016 - 9th International Workshop on Programmability and Architectures for Heterogeneous Multicores, HIPEAC, Jan 2016, Prague, Czech Republic
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lirmm-01377630
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Design Exploration for next Generation High-Performance Manycore On-chip Systems: Application to big.LITTLE ArchitecturesISVLSI: International Symposium on Very Large Scale Integration, Jul 2015, Montpellier, France. pp.551-556, ⟨10.1109/ISVLSI.2015.28⟩
Communication dans un congrès
lirmm-01255927
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Simultaneous multithreading support in embedded distributed memory MPSoCsDAC 2013 - 50th Design Automation Conference, May 2013, Austin, United States. pp.83:1-83:7, ⟨10.1145/2463209.2488836⟩
Communication dans un congrès
lirmm-01391168
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Adaptation Strategies in Multiprocessors System on ChipVLSI-SoC: Very Large Scale Integration - System-on-Chip, Sep 2010, Madrid, Spain. pp.233-257, ⟨10.1007/978-3-642-28566-0_10⟩
Communication dans un congrès
hal-01515993
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Open-Scale: A Scalable, Open-Source NOC-based MPSoC for Design Space ExplorationReConFig 2011 - International Conference on Reconfigurable Computing and FPGAs, Nov 2011, Cancun, Mexico. pp.357-362, ⟨10.1109/ReConFig.2011.66⟩
Communication dans un congrès
hal-01139181
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Adaptative Integrated Systems for Optimal Hardware UsageEcole d'hiver Francophone sur les Technologies de Conception des Systèmes Embarqués Hétérogènes (FETCH 2010), Jan 2010, Chamonix, France
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lirmm-00450767
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Differential Power Analysis Enhancement with Statistical PreprocessingDATE: Design, Automation and Test in Europe, 2010, Dresden, Germany. pp.1301-1304, ⟨10.1109/DATE.2010.5457007⟩
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lirmm-00548738
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Providing Better Multi-Processor Systems-on-Chip Resources Utilization by Means of Using a Control-Loop Feedback MechanismReConFig 2010 - International Conference on ReConFigurable Computing and FPGAs, Dec 2010, Cancun, Mexico. pp.382-387, ⟨10.1109/ReConFig.2010.17⟩
Communication dans un congrès
lirmm-00548837
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Adaptation in MP-SoCs: Opportunities for Meeting the Upcoming Design ChallengesNEWCAS 2010 - 8th IEEE International New Circuits and Systems Conference, Jun 2010, Montreal, QC, Canada
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lirmm-00504878
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Spatial EM Jamming: a Countermeasure Against EM Analysis ?VLSI-SoC'10: 18th IEEE/IFIP International Conference on VLSI and System-on-Chip, Madrid, Spain. pp.105-110
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lirmm-00544358
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Incoherence Analysis and its Application to Time Domain EM Analysis of Secure CircuitsAPEMC 2010 - Asia-Pacific Symposium on Electromagnetic Compatibility, Apr 2010, Beijing, China. pp.1039-1042, ⟨10.1109/APEMC.2010.5475481⟩
Communication dans un congrès
lirmm-00607894
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On-Chip Timing Slack MonitoringVLSI-SoC: Very Large Scale Integration - System-on-Chip, Oct 2009, Florianopolis, Brazil. pp.89-94, ⟨10.1109/VLSISOC.2009.6041336⟩
Communication dans un congrès
lirmm-00429350
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Systèmes intégrés "Hétérogènes" FlexiblesFETCH'09: Ecole d'Hiver Francophone sur les Technologies de Conception des Systèmes Embarqués Hétérogènes, Jan 2009, Chexbres, Switzerland
Communication dans un congrès
lirmm-00358501
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Un nouveau système d'instrumentation en ligne pour la caractérisation et l'adaptation dynamique aux variationsFTFC: Faible Tension - Faible Consommation, Jun 2009, Neuchâtel, Suisse
Communication dans un congrès
lirmm-00404810
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Digital Timing Slack Monitors and their Specific Insertion Flow for Adaptive Compensation of VariabilitiesPATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 2009, Delft, Netherlands. pp.266-275, ⟨10.1007/978-3-642-11802-9_31⟩
Communication dans un congrès
istex
lirmm-00433462
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An Innovative Timing Slack Monitor for Variation Tolerant CircuitsICICDT: International Conference on IC Design & Technology, May 2009, Austin, TX, United States. pp.215-218, ⟨10.1109/ICICDT.2009.5166299⟩
Communication dans un congrès
lirmm-00371174
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A Bio-Inspired Agent Framework for Hardware Accelerated Distributed Pervasive ApplicationsAHS'09: NASA/ESA Conference on Adaptive Hardware and Systems, Jul 2009, San Fransisco, United States. pp.415-422, ⟨10.1109/AHS.2009.54⟩
Communication dans un congrès
lirmm-00419914
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Evaluation on FPGA of Triple Rail Logic Robustness Against DPA and DEMADATE: Design, Automation and Test in Europe, 2009, Nice, France. pp.634-639, ⟨10.1109/DATE.2009.5090744⟩
Communication dans un congrès
lirmm-00372847
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Enhancing Electromagnetic Attacks using Spectral Coherence based CartographyVLSI-SoC 2009 - 17th IFIP International Conference on Very Large Scale Integration, Oct 2009, Florianopolis, Brazil. pp.11-16, ⟨10.1109/VLSISOC.2009.6041323⟩
Communication dans un congrès
lirmm-00429342
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JubiTool: Unified Design Flow for the Perplexus SIMD Hardware AcceleratorCEC'09: IEEE Congress on Evolutionary Computation, 2009, Trondheim, Norway. pp.2070-2075
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lirmm-00372859
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Setup and Hold Timing Violations Induced by Process Variations, in a Digital MultiplierISVLSI: International Symposium on Very Large Scale Integration, Apr 2008, Montpellier, France. pp.316-321, ⟨10.1109/ISVLSI.2008.70⟩
Communication dans un congrès
lirmm-00280809
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Statistical Sizing of an eSRAM Dummy Bitline Driver for Read Margin Improvement in the Presence of Variability AspectsISVLSI'08: IEEE Computer Society Annual Symposium on VLSI, Apr 2008, Montpellier, France, pp.310-315
Communication dans un congrès
lirmm-00280716
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Bio-Inspiration Helps Computers: An New MachineFPL'08: The 18th International Conference on Field-Programmable Logic and Applications, Sep 2008, Heidelberg, Germany. pp.697-698
Communication dans un congrès
lirmm-00326534
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The Perplexus Programming Framework: Combining Bio-inspiration and Agent-Oriented Programming for the Simulation of Large Scale Complex SystemsICES 2008 - International Conference on Evolvable Systems, Sep 2008, Prague, Czech Republic. pp.402-407, ⟨10.1007/978-3-540-85857-7_36⟩
Communication dans un congrès
lirmm-00282971
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Prototyping Secure Triple Track Logic (STTL) Robustness Against DPA & DEMA on FPGACryptArchi: Cryptographic Architectures, Jun 2008, Tregastel, France
Communication dans un congrès
lirmm-00373539
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Statistical Sizing Methodology of an SRAM in Presence of Signal Races and Variability ConditionsIFIP VLSI-SOC 2008 - IFIP/IEEE WG 10.5 International Conference on Very Large Scale Integration, pp.193-198
Communication dans un congrès
lirmm-00332762
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MPI-Based Adaptive Task Migration Support on the HS-Scale SystemISVLSI 2008 - IEEE Computer Society Annual Symposium on VLSI, Apr 2008, Montpellier, France. pp.105-110, ⟨10.1109/ISVLSI.2008.87⟩
Communication dans un congrès
lirmm-00280687
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Baf: A Bio-Inspired Agent Framework for Distributed Pervasive ApplicationsGEM'08: Genetic and Evolutionary Mechanisms, Las Vegas, USA, pp.N/A
Communication dans un congrès
lirmm-00374063
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Étude des violations de temps d'établissement et de maintien dues aux variations du processus de fabrication dans un opérateur arithmétiqueJNRDM 2008 - 11e Journées Nationales du Réseau Doctoral de Microélectronique, May 2008, Bordeaux, France
Communication dans un congrès
lirmm-00281175
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Triple Rail Logic Robustness against DPAReConFig 2008 - International Conference on Reconfigurable Computing and FPGAs, Dec 2008, Cancun, Mexico. pp.415-420, ⟨10.1109/ReConFig.2008.75⟩
Communication dans un congrès
lirmm-00350573
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A Comparative Study of Variability Impact on Static Flip-Flop Timing CharacteristicsICICDT: International Conference on IC Design and Technology, Jun 2008, Grenoble, France. pp.167-170
Communication dans un congrès
lirmm-00305246
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A Non-Volatile Field Programmable Gate Array using Thermally Assisted Switching MRAMsICESCA'08: International Conference on Embedded Systems & Critical Applications, May 2008, Gammarth, Tunisia. pp.95-100
Communication dans un congrès
lirmm-00282964
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Evaluating the Robustness of Secure Triple Track Logic Through PrototypingSBCCI'08: Symposium on Integrated Circuits and Systems Design, Sep 2008, Gramado, Brazil, France. pp.193-198, ⟨10.1145/1404371.1404425⟩
Communication dans un congrès
lirmm-00373516
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A Novel Dummy Bitline Driver for Read Margin Improvement in an eSRAMDELTA 2008 - 4th IEEE International Symposium on Electronic Design, Test and Applications, Jan 2008, Hong Kong, China. pp.107-110, ⟨10.1109/DELTA.2008.72⟩
Communication dans un congrès
lirmm-00243966
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Impact de la variabilité des caractéristiques temporelles des cellules combinatoires et séquentielles sur un opérateur numériqueFTFC: Faible Tension - Faible Consommation, May 2008, Louvain-La-Neuve, Belgique
Communication dans un congrès
lirmm-00283731
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The Perplexus ProjectDASIP'07: Workshop on Design and Architectures for Signal and Image Processing, Nov 2007, Grenoble, France, France. pp.N/A
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lirmm-00202692
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Variabilité de Process et Performances des Mémoires SRAM EmbarquéesFTFC'07: 6èmes Journées d'Etudes Faible Tension Faible Consommation, May 2007, Paris, France, pp.7-11
Communication dans un congrès
lirmm-00178319
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Méthodologie d'estimation de l'influence de la variabilité sur un opérateur numériqueFTFC 2007 - 6e journées d'Etudes Faible Tension Faible Consommation, May 2007, Paris, France
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lirmm-00204621
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Process Variabilities and Performances in a 90nm embedded SRAMIEEE International Integrated Reliability Workshop, Oct 2007, pp.050-055
Communication dans un congrès
lirmm-00198373
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Uma Arquitetura Dinamicamente Reconfiguràvel para Criptografia Robusta contra Ataques pour Canais ColateraisREC'07: Actas das III Jornadas Sobre Sistemas Reconfiguràveis, Feb 2007, Lisboa, Portugal, pp.45-53
Communication dans un congrès
lirmm-00188346
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Current Mask Generation: an Analog Circuit to Thwart DPA AttacksVLSI-SoC 2005 - 13th International Conference on Very Large Scale Integration of System on Chip, Oct 2005, Perth, Australia. pp.317-330, ⟨10.1007/978-0-387-73661-7_20⟩
Communication dans un congrès
lirmm-00102782
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Application Case Studies on HS-Scale, a MP-SOC for Embbeded SystemsEmbedded Computer Systems: Architectures, Modeling and Simulation (SAMOS), Jul 2007, Samos, Greece. pp.88-95, ⟨10.1109/ICSAMOS.2007.4285738⟩
Communication dans un congrès
lirmm-00179513
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Improvement of Dual Rail Logic as a Countermeasure Against DPAVLSI-SoC 2007 - IFIP International Conference on Very Large Scale Integration, Oct 2007, Atlanta, GA, United States. pp.270-275, ⟨10.1109/VLSISOC.2007.4402510⟩
Communication dans un congrès
lirmm-00186174
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Process Variability Considerations in the Design of an eSRAMMTDT 2007 - IEEE International Workshop on Memory Technology, Design and Testing, Dec 2007, Taipei, Taiwan. pp.23-26, ⟨10.1109/MTDT.2007.4547609⟩
Communication dans un congrès
lirmm-00275258
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An Adaptative MP-SoC Architecture for Embedded SystemsCAR'07: 2nd National Workshop on Control Architectures of Robots: From Models to Execution on Distributed Control Architectures, Jun 2007, Paris, France. pp.101-107
Communication dans un congrès
lirmm-00179505
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HS Scale: A Run-Time Adaptable MP-SoC ArchitectureReCoSoC'07: International Workshop on Reconfigurable Communication Centric System-On-Chips, Jun 2007, Montpellier, France. pp.CDROM
Communication dans un congrès
lirmm-00179482
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HS-Scale: A Hardware-Software Scalable MP-SOC Architecture for Embedded SystemsISVLSI'07: IEEE Computer Society Annual Symposium on VLSI, 2007, Porto Allegre, Brazil, pp.21-28
Communication dans un congrès
lirmm-00154074
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A Cryptographic Coarse Grain Reconfigurable Architecture Robust Against DPAIPDPS 2007 - 21th International Parallel and Distributed Processing Symposium, Mar 2007, Long Beach, CA, United States. pp.1-8
Communication dans un congrès
lirmm-00179638
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Architectural Issues in Homogeneous NOC-Based MPSOCRSP'07: 18th IEEE/IFIP International Workshop on Rapid System Prototyping, May 2007, Porto Alegre, Brazil, pp.139-142
Communication dans un congrès
lirmm-00179622
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Analysis and Improvement of Dual Rail Logic as a Countermeasure Against DPAPATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 2007, Gothenburg, Sweden. pp.340-351, ⟨10.1007/978-3-540-74442-9_33⟩
Communication dans un congrès
istex
lirmm-00175100
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A Leak Resistant Architecture Against Side Channel AttacksFPL: Field-Programmable Logic and Applications, Aug 2006, Madrid, Spain. pp.881-884, ⟨10.1109/FPL.2006.311335⟩
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lirmm-00102784
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Implémentation Matérielle d'une Arithmétique Résistante aux FuitesRenPar/ SympAAA/ CFSE - Rencontres Francophones en Parallélisme, Architecture, Adéquation Algorithmes Architecture et Système, Oct 2006, Canet en Roussillon, France. pp.57-74
Communication dans un congrès
lirmm-00107317
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A Leak Resistant SoC to Counteract Side Channel AttacksSOC'06: International Symposium on System-On-Chip, Nov 2006, Tampere, Finlande, pp.N/A
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lirmm-00352713
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Security Evaluation of Dual Rail Logic Against DPA AttacksVLSI-SoC 2006 - 14th IFIP International Conference on Very Large Scale Integration, Oct 2006, Nice, France. pp.181-186, ⟨10.1109/VLSISOC.2006.313230⟩
Communication dans un congrès
lirmm-00109692
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Dynamic hardware multiplexing: improving adaptability with a run time reconfiguration managerISVLSI 2006 - IEEE Computer Society Annual Symposium on VLSI, Mar 2006, Karlsruhe, Germany. pp.251-256, ⟨10.1109/ISVLSI.2006.38⟩
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lirmm-00102766
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Run-Time Scheduling for Random Multi Tasking in Reconfigurable CoprocessorsFPL'05 IEEE : 15th International Workshop on Field-Programmable Logic and Applications, Aug 2005, Tampere (Finlande), pp.703-706
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lirmm-00106057
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A GALS Network on Chip with Quality of Service supportSAME'05: Sophia-Antipolis Forum on MicroElectronics, Oct 2005, Sophia Antipolis, France. pp.199-207
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lirmm-00106526
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Asynchronous Dual rail Cells to Secure Cryptosystem Against Side Channel AttacksSAME'05: Sophia-Antipolis Forum on MicroElectronics, Oct 2005, Sophia-Antipolis
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lirmm-00106539
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A Method to Design Compact Dual-rail Asynchronous PrimitivesPATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 2005, Leuven, Belgium. pp.571-580, ⟨10.1007/11556930_58⟩
Communication dans un congrès
istex
hal-00105846
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An Integrated Image Motion Sensor for Micro Camera ModuleVLSI-SoC: Very Large Scale Integration - System-on-Chip, Oct 2005, Perth, Australia. pp.333-338
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lirmm-00106497
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Pixel Level Silicon Integration of Motion EstimationDDECS: Design and Diagnostics of Electronic Circuits and Systems, Apr 2005, Sopron, Hungary. pp.93-98
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lirmm-00105989
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Focal Plane Integration of Image Texture Coding for Pixel CorrespondencePRIME: PhD Research in Microelectronics and Electronics, Jul 2005, Lausanne, Switzerland. pp.327-330
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lirmm-00106065
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Packet-Switching Network-On-Chip Features Exploration and CharacterizationVLSI-SOC'05: IFIP International Conference on Very Large Scale Integration, Oct 2005, Perth, Australia. pp.403-409
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lirmm-00106440
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Design of Compact Dual Rail Asynchronous PrimitivesDCIS 2005 - 20th Conference on Design of Circuits and Integrated Systems, 2005, Lisbonne, Portugal
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lirmm-00106434
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Current Mask Generation: A Transistor Level Security Against DPA AttacksSBCCI 2005 - 18th annual symposium on Integrated circuits and system design, Sep 2005, Florianolpolis, Brazil. pp.115-120, ⟨10.1145/1081081.1081114⟩
Communication dans un congrès
lirmm-03704230
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Méthode de Conception de Primitives Asynchrones Double RailFTFC'05 : 5èmes Journées d'Etudes Francophones Faible Tension - Faible Consommation, May 2005, Paris, France, pp.23-27
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lirmm-00106003
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Automatic Task Scheduling/Loop Unrolling Using Dedicated RTR Controllers in Coarse Grain Recongigurable ArchitecturesIPDPS'05: International Parallel and Distributed Processing Symposium, RAW'05: Reconfigurable Architectures Workshop, Apr 2005, Denver, Colorado (USA), pp.148
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lirmm-00105985
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Test Engineering Education in Europe: The EuNICE Test ProjectEDUTECH'05, 2005, France
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lirmm-00106506
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A RTR Hardware Controller for DSP Kernel Scheduling in Coarse Grain Reconfigurable ArchitectureIPDPS'05: International Parallel and Distributed Processing SymposiumRAW'05: Reconfigurable Architectures Workshop, Apr 2005, pp.485-489
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lirmm-00105958
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A Mesh Based Network on Chip characterization : A GALS ApproachDCIS 2005 - 20th Conference on Design of Circuits and Integrated Systems, Nov 2005, Lisbonne, Portugal. pp.10-15
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lirmm-00106054
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An Image Sensor with Global Motion Estimation for Micro Camera ModuleACIVS: Advanced Concepts for Intelligent Vision Systems, Sep 2005, Anvers, Belgium. pp.713-721
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lirmm-00106498
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La Technologie Asynchrone QDI pour la Sécurité des CryptosystèmesJNRDM 2005 - 8e Journées Nationales du Réseau Doctoral de Microélectronique, May 2005, Paris, France. pp.461-463
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lirmm-00106530
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Estimation du Mouvement Global par Mesures Locales PériphériquesREAD: Rétines Electroniques / Asic-FPGA et DSP pour la Vision et le Traitement d'Images en Temps Réel, Jun 2005, Institut National des Télécommunications, Ivry, France. pp.77-82
Communication dans un congrès
lirmm-00106520
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Gestion Matérielle du Parallélisme pour les Architectures Reconfigurables à Grain EpaisJFAAA'05: Journées Francophones sur l'Adéquation Algorithme Architecture, Jan 2005, Dijon, France. pp.15-20
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lirmm-00106510
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Automatic Layout Synthesis Based Performance OptimizationIWLS: International Workshop on Logic Synthesis, Jun 2004, Temecula, CA, United States. pp.80-85
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lirmm-00108654
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Metrics for Digital Signal Processing Architectures Characterization: Remanence and ScalabilitySAMOS 2004 - 4th International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation, Jul 2004, Samos, Greece. pp.128-137
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lirmm-00269656
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System On Chip (SOC) : Du Composant... au ComposantJournées Nationales du GDR et RTP Nanoélectronique, May 2004, Aussois, France
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lirmm-00108673
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Réseaux d'interconnexion pour les systèmes sur Puce : le réseau HERMESSCS 2004 - Signaux, Circuits et Systèmes, Mar 2004, Monastir, Tunisia. pp.35-40
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lirmm-00352701
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Défi en CAO de Circuits et Systèmes Intégrés : Recherche, Formations, MétiersCNFM'04 : 8ème Journées Pédagogiques du Comité National de Formation en Microélectronique, 2004, Saint-Malo, France. pp. 31-37
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hal-00005846
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Block Constraints Budgeting in Timing-Driven Hierarchical FlowDCIS: Design of Circuits and Integrated Systems, Nov 2004, Bordeaux, France. pp.930-935
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lirmm-00108941
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CAO des Circuits et Systèmes sur Puce : Etat de l'Art, Enjeux et Perspectives ScientifiquesArchitectures d'Interfaces et MicrocontrôleursPuissance en Electronique, May 2004, Carry le Rouet, France
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lirmm-00108669
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Réseau d'interconnexion pour les systèmes sur pucesJNRDM'04: 7èmes Journées Nationales du Réseau Doctoral de Microélectronique, May 2004, Marseille, France. pp.451-453
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lirmm-00355900
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Design Optimization with Automated Cell GenerationPATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 2004, Santorini, Greece. pp.722-731, ⟨10.1007/978-3-540-30205-6_74⟩
Communication dans un congrès
istex
lirmm-00108894
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A Flexible Aware Budgeting for Hierarchical Flow Timing ClosureICCAD 2004 - 1st IEEE International Conference on Computer Aided Design, Nov 2004, San Jose, United States. pp.261-265, ⟨10.1109/ICCAD.2004.1382583⟩
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lirmm-00108940
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Conception et Modélisation de Briques Elémentaires CMOSCNFM'04 : 8ème Journées Pédagogiques du Comité National de Formation en Microélectronique, 2004, Saint-Malo, France. pp.35-37
Communication dans un congrès
lirmm-00108672
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Secured Structures for Secured Asynchronous QDI CircuitsDCIS: Design of Circuits and Integrated Systems, Nov 2004, Bordeaux, France
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hal-01393250
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Comparaison des Architectures Dédiées au Traitement des Données NumériquesJNRDM'03 : 6ièmes Journées Nationales du Réseau Doctoral de Microélectronique, May 2003, Toulouse (France), France. pp.115-117
Communication dans un congrès
lirmm-00269542
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An I.P. Migration and Prototyping Strategy Using Transistor Level SynthesisDCIS: Design of Circuits and Integrated Systems, Nov 2003, Ciudad Real, Spain. pp.266-271
Communication dans un congrès
lirmm-00269694
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A Novel Approach for Architectural Model Characterization. An Example through the Systolic Ring.FPL 2003 - 12th International Workshop on Field-Programmable Logic and Applications, Sep 2003, Lisbon, Portugal. pp.722-732, ⟨10.1007/978-3-540-45234-8_70⟩
Communication dans un congrès
istex
lirmm-00269558
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Metrics for Reconfigurable Architectures Characterization: Remanence and ScalabilityIPDPS: International Parallel and Distributed Processing Symposium, Apr 2003, Nice, France. pp.176-180, ⟨10.1109/IPDPS.2003.1213324⟩
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A Fast Prototyping and IP Migration Strategy Using Transistor Level SynthesisSAME: Sophia-Antipolis Forum on MicroElectronics, Oct 2003, Sophia Antipolis, France
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Systèmes Microélectroniques Complexes sur Puce (SOC) : Du Circuit à la PlateformeColloque Intertronic "Conception Numérique Intégrée : Hardware&Software", 2003, Montpellier, France
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Circuits et Systèmes Microélectroniques Complexes : Modélisation et Calcul ScientifiqueAcadémie des Technologies, France. pp.P nd
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Comparaison d'Architectures Dédiées au Traitement Numériques des Données : du Processeur aux Architectures ReconfigurablesRenPar/ SympAAA/ CFSE - Rencontres Francophones en Parallélisme, Architecture, Adéquation Algorithmes Architecture et Système, Oct 2003, La Colle sur Loup, France. pp.322-326
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Are Coarse Grain Reconfigurable Architectures Suitable for Cryptography?12th International Conference on Very Large Scale Integration of System-on-Chip (VLSI-SoC), Dec 2003, Darmstadt, Germany. pp.276-281
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Person Identification Technique Using Human Iris RecognitionIV 2002 - 15th International Conference on Vision Interface, May 2002, Calgary, Canada. pp.294-299
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Une Nouvelle Opération au CNFM : Le Programme SoC (Système sur Puce)CNFM 2002 - 7es Journées Pédagogiques du Comité National de Formation en Microélectronique, Nov 2002, St Malo, France. pp.67-70
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Iris Recognition System for Person IdentificationPRIS: Pattern Recognition in Information Systems, 2002, Alicante, Spain. pp.71-75
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Architectures Reconfigurables Dynamiquement pour Applications TSIColloque du GDR CAO de Circuits et Systèmes Intégrés, May 2002, Paris, France. pp.67-70
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Caractérisation et Comparaison d'Architectures Reconfigurables Dynamiquement, un exemple : Le Systolic RingJFAAA'02: Journées Francophones sur l'Adéquation Algorithme Architecture, Dec 2002, Monastir, Tunisie. pp.30-34
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Systèmes Microélectroniques Complexes sur Puce (SoC)CNFM: Comité National de Formation en Microélectronique, Nov 2002, St Malo, France
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A wavelet core for video processingICIP 2000 - 7th IEEE International Conference on Image Processing, Sep 2000, Vancouver, Canada. pp.395-398, ⟨10.1109/ICIP.2000.899406⟩
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A Physical Synthesis Design Flow based on Virtual ComponentsDCIS: Design of Circuits and Integrated Systems, Nov 2000, Montpellier, France. pp.740-745
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Tool Box for Performance Driven Macrocell layout SynthesisEurochip Workshop on VLSI Design Training, Sep 1993, Toledo, Spain. pp.56-61
Communication dans un congrès
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Evaluation of Speed up Strategy from Gate Performance ModellingIFIP Workshop on Logic and Architecture Synthesis, Dec 1993, Grenoble, France, pp.193-208
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Flexible Macrocell layout Generator4th ACM/SIGDA Physical Design Workshop, Layout Synthesis for the New Generation of VLSI ASIC Technologies, Apr 1993, UCLA Conference Center, CA, USA, pp.105-116
Communication dans un congrès
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Application of Explicit Delay Time Modelling to CMOS Data Path Evaluation and Transistor SisingPATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 1992, Paris, France. pp.102-108
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An Accurate and Efficient Delay Time Modelling and its Application to CMOS Data Path Evaluation and Transistor SizingWorld Congress on Computation and Applied Mathematics, IMACS: International Association for Mathematics and Computers in Simulation, Jul 1991, Dublin, Ireland. pp.1661-1663
Communication dans un congrès
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Formal Sizing Rules of CMOS CircuitsEDAC 1991 - European Conference on Design Automation, Feb 1991, Amsterdam, Netherlands. pp.96-100, ⟨10.1109/EDAC.1991.206368⟩
Communication dans un congrès
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Evaluation of VLSI Layout Implementation for EfficiencyEURO-ASIC 1991 - European Conference on Design Automation with European Event in ASIC Design, May 1991, Paris, France. pp.362-365, ⟨10.1109/EUASIC.1991.212836⟩
Communication dans un congrès
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Distributed Pervasive Phylogenetic Application using a Bio-Inspired Agent FrameworkColloque GDR SoC-SiP, 2008, Paris, France. 2008
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Perplexus ProjectColloque du GDR SoC-SiP, 2007, Paris, France. 2007
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Towards Self-Adaptability a Scalable MP-SOC Architecture ApproachColloque du GDR SoC-SiP, 2007, Paris, France. 2007
Poster de conférence
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Dynamic Hardware Multiplexing for Coarse Grain Reconfigurable ArchitecturesFPGA'05: ACM/SIGDA 9th International Symposium on Field Programmable Gate Arrays, Feb 2005, Monterey, CA, United States. ACM Press, 2005
Poster de conférence
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Test Engineering Education in Europe: The CRTC Experience Through the EuNICE-Test ProjectAchim Rettberg and Christophe Bobda. IFIP TC10 Working Conference: EduTech'05, Oct 2005, France. , pp.63-77, 2005
Poster de conférence
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Packet-Switching Network-On-Chip Feature Exploration and CharacterizationRECoSoC'05: Reconfigurable Communication-Centric SoCs, Jun 2005, Montpellier, France. 2005
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The Systolic Ring: A Scalable Dynamically Reconfigurable Core for Embedded SystemsSAME 2002 - Sophia-Antipolis Forum on MicroElectronics, Oct 2002, Sophia-Antipolis, France. pp.85-90, 2002
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Le sens de l'évaluation dans l'enseignement supérieur et la recherche2020, 978-2-9573353-0-5
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First International Conference on Embedded Systems and Critical Applications (ICESCA 2008)2008
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SOC Design MethodologiesSpringer, 2002, ⟨10.1007/978-0-387-35597-9⟩
Ouvrages
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Towards Autonomous Scalable Integrated SystemsDesign Technology for Heterogeneous Embedded Systems, Springer, pp.63-89, 2012, 978-94-007-1124-2. ⟨10.1007/978-94-007-1125-9_4⟩
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istex
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An Introduction to Multi-Core System on Chip - Trends and ChallengesHübner, Michael; Becker, Jürgen. Multiprocessor System-on-Chip - Hardware Design and Tool Integration, Springer, pp.1-21, 2011, Chapter 1, 978-1-4419-6459-5. ⟨10.1007/978-1-4419-6460-1_1⟩
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Side Channel AttacksSecurity Trends for FPGAS
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istex
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From Secured to Secure Reconfigurable Systems, Springer, pp.47-72, 2011, 978-94-007-1337-6. ⟨10.1007/978-94-007-1338-3_3⟩ |
Current Mask Generation: An Analog Circuit to Thwart DPA AttacksVLSI-SoC: From Systems to Silicon, Springer, pp.317-330, 2007, 978-0-387-73660-0
Chapitre d'ouvrage
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Formal Evaluation of the Robustness of Dual-Rail Logic Against DPA AttacksNadine Azémard, Philippe Maurine, Johan Vounckx. Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 4148/2006, Springer Berlin / Heidelberg, pp.634-644, 2006, Lecture Notes in Computer Science, 978-3-540-39094-7. ⟨10.1007/11847083_44⟩
Chapitre d'ouvrage
istex
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Dynamically Reconfigurable Architectures for Digital Signal Processing ApplicationsSOC Design Methodologies, 90, Kluwer Academic Publishers 2002, pp.63-74, 2002, IFIP — The International Federation for Information Processing, 978-1-4757-6530-4. ⟨10.1007/978-0-387-35597-9_6⟩
Chapitre d'ouvrage
lirmm-00108929
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Implementation of a Wavelet Transform Architecture for Image ProcessingVLSI: Systems on a Chip, 34, Springer US, pp.101-112, 2000, IFIP Advances in Information and Communication Technology, 978-1-4757-1014-4. ⟨10.1007/978-0-387-35498-9_10⟩
Chapitre d'ouvrage
lirmm-03704293
v1
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Data Processing System with Energy TransferFrance, Patent n° : FR20160053238. 2016
Brevet
lirmm-02145436
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Architecture de Transport de Données en Anneau comprenant un Réseau de RétropopagationFrance, N° de brevet: FR20020004162. 2002
Brevet
lirmm-00268654
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Architecture de Calcul Logique comprenant plusieurs Modes de ConfigurationFrance, N° de brevet: FR0204161. 2002
Brevet
lirmm-00268653
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Propriété Intellectuelle : La Vérification Système en Question2003, pp.34-43
Autre publication scientifique
lirmm-00269735
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Emerging NVM Technologies in Main Memory for Energy-Efficient HPC: an Empirical Study2019
Pré-publication, Document de travail
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La Recherche dans les Micro et Nanotechnologies : Du Nanoobjet au Système2003, pp.P nd
Rapport
(rapport contrat/projet)
lirmm-00269738
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Systèmes Microélectroniques sur Puce : Complexité et Interconnections2003
Rapport
(rapport contrat/projet)
lirmm-00269737
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Library Free Integrated Circuits for Submicron Technologies[Research Report] Lirmm, University of Montpellier. 2002
Rapport
(rapport de recherche)
lirmm-00268592
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Library free integrated circuit design for submicron technologies2002
Rapport
(rapport contrat/projet)
lirmm-00259937
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Library Free Integrated Circuit Design for Submicron Technologies2000
Rapport
(rapport contrat/projet)
lirmm-00259939
v1
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