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Philippe Maurine
224
Documents
Researcher identifiers
philippe-maurine- Google Scholar : https://scholar.google.fr/citations?hl=fr&user=VduRIsgAAAAJ&view_op=list_works&sortby=pubdate
- IdRef : 144880717
-
0000-0002-9706-5710
- Google Scholar : https://scholar.google.fr/citations?user=VduRIsgAAAAJ&hl=fr
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Butterfly probes: estimating the derivative of the magnetic fieldEMC COMPO 2024 - 14th International Workshop on the Electromagnetic Compatibility of Integrated Circuits, Oct 2024, Turin, Italy
Conference papers
hal-04699339v1
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The EVIL Machine: Encode, Visualize and Interpret the LeakageSAC 2023 - 38th ACM/SIGAPP Symposium on Applied Computing, Mar 2023, Tallinn, Estonia. pp.1566-1575, ⟨10.1145/3555776.3577688⟩
Conference papers
lirmm-04230167v1
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On the scaling of EMFI probesFDTC 2021 - Workshop on Fault Detection and Tolerance in Cryptography, Sep 2021, Milan, Italy. pp.67-73, ⟨10.1109/FDTC53659.2021.00019⟩
Conference papers
lirmm-03476820v1
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Exploring flexible and 3D printing technologies for the design of high spatial resolution EM probesNEWCAS 2021 - 19th IEEE International New Circuits and Systems Conference, Jun 2021, Toulon, France. pp.1-4, ⟨10.1109/NEWCAS50681.2021.9462763⟩
Conference papers
lirmm-03278789v1
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Spatial Dependency Analysis to Extract Information from Side-Channel MixturesASHES 2021 - 5th Workshop on Attacks and Solutions in Hardware Security @CCS 2021, Nov 2021, Virtual Event, South Korea. pp.73-84, ⟨10.1145/3474376.3487280⟩
Conference papers
lirmm-03476806v1
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Iterative Method for Performance Prediction Improvement of Integrated CircuitsDCIS 2021 - 36th Conference on Design of Circuits and Integrated Systems, Nov 2021, Vila do Conde, Portugal. pp.1-5, ⟨10.1109/DCIS53048.2021.9666182⟩
Conference papers
lirmm-03710383v1
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Leakage Assessment through Neural Estimation of the Mutual InformationACNS 2020 - International Conference on Applied Cryptography and Network Security, Oct 2020, Rome, Italy. pp.144-162, ⟨10.1007/978-3-030-61638-0_9⟩
Conference papers
hal-02980501v1
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Electromagnetic Fault Injection : How Faults OccurFDTC 2019 - Workshop on Fault Diagnosis and Tolerance in Cryptography, Aug 2019, Atlanta, GA, United States. pp.9-16, ⟨10.1109/FDTC.2019.00010⟩
Conference papers
lirmm-02328109v1
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Breaking Mobile Firmware Encryption through Near-Field Side-Channel AnalysisASHES 2019 - 3rd Attacks and Solutions in Hardware Security Workshop, Nov 2019, London, United Kingdom. pp.23-32, ⟨10.1145/3338508.3359571⟩
Conference papers
lirmm-03660638v1
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Thermal Scans for Detecting Hardware TrojansCOSADE 2018 - 9th International Workshop on Constructive Side-Channel Analysis and Secure Design, Apr 2018, Singapour, Singapore. pp.117-132, ⟨10.1007/978-3-319-89641-0_7⟩
Conference papers
lirmm-01823444v1
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The impact of pulsed electromagnetic fault injection on true random number generatorsFDTC 2018 - Workshop on Fault Diagnosis and Tolerance in Cryptography, Sep 2018, Amsterdam, Netherlands. pp.43-48, ⟨10.1109/FDTC.2018.00015⟩
Conference papers
lirmm-01943112v1
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Exploiting Phase Information in Thermal Scans for Stealthy Trojan DetectionDSD 2018 - 21st Euromicro Conference on Digital System Design, Aug 2018, Prague, Slovakia. pp.573-576, ⟨10.1109/DSD.2018.00100⟩
Conference papers
lirmm-01872499v1
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Standard CAD Tool-Based Method for Simulation of Laser-Induced Faults in Large-Scale CircuitsISPD 2018 - International Symposium on Physical Design, Mar 2018, Monterey, CA, United States. pp.160-167, ⟨10.1145/3177540.3178243⟩
Conference papers
lirmm-01743368v1
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Electromagnetic Activity vs. Logical Activity: Near Field Scans for Reverse EngineeringCARDIS 2018 - 17th International Conference on Smart Card Research and Advanced Applications, Nov 2018, Montpellier, France. pp.140-155, ⟨10.1007/978-3-030-15462-2_10⟩
Conference papers
lirmm-01943151v1
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Role of Laser-Induced IR Drops in the Occurrence of Faults: Assessment and SimulationDSD 2017 - Euromicro Symposium on Digital System Design, Aug 2017, Vienna, Austria. pp.252-259, ⟨10.1109/DSD.2017.43⟩
Conference papers
lirmm-01699776v1
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An {EM} Fault Injection Susceptibility Criterion and Its Application to the Localization of HotspotsCARDIS 2017 - 16th International Conference on Smart Card Research and Advanced Applications, Nov 2017, Lugano, Switzerland. pp.180-195, ⟨10.1007/978-3-319-75208-2_11⟩
Conference papers
lirmm-02100194v1
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Impacts of Technology Trends on Physical Attacks?COSADE 2017 - 8th International Workshop on Constructive Side-Channel Analysis and Secure Design, Apr 2017, Paris, France. pp.190-206, ⟨10.1007/978-3-319-64647-3_12⟩
Conference papers
lirmm-01690188v1
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Importance of IR Drops on the Modeling of Laser-Induced Transient FaultsSMACD 2017 - 14th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, Jun 2017, Giardini Naxos, Italy. ⟨10.1109/SMACD.2017.7981593⟩
Conference papers
hal-01721087v1
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Method for evaluation of transient-fault detection techniquesESREF: European Symposium on Reliability of Electron devices, Failure physics and analysis, Sep 2017, Bordeaux, France
Conference papers
hal-01721081v1
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A Fully-Digital Em Pulse DetectorDATE 2016 - 19th Design, Automation and Test in Europe Conference and Exhibition, Mar 2016, Dresden, Germany. pp.439-444
Conference papers
lirmm-01269860v1
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On-Chip Fingerprinting of IC Topology for Integrity VerificationDATE 2016 - 19th Design, Automation and Test in Europe Conference and Exhibition, Mar 2016, Dresden, Germany. pp.133-138, ⟨10.3850/9783981537079_0169⟩
Conference papers
lirmm-01269856v1
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Body Biasing Injection Attacks in PracticeCS2: Cryptography and Security in Computing Systems, Jan 2016, Prague, Czech Republic. pp.49-54, ⟨10.1145/2858930.2858940⟩
Conference papers
lirmm-01434143v1
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An Embedded Digital Sensor against EM and BB Fault InjectionFDTC: Fault Diagnosis and Tolerance in Cryptography, Aug 2016, Santa Barbara, CA, United States. pp.78-86, ⟨10.1109/FDTC.2016.14⟩
Conference papers
lirmm-01434028v1
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Electromagnetic Analysis Perturbation using Chaos GeneratorTruedevice 2016, Nov 2016, Barcelona, Spain
Conference papers
hal-01455446v1
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Granularity and detection capability of an adaptive embedded Hardware Trojan detection systemHOST: Hardware Oriented Security and Trust, May 2016, McLean, VA, United States. pp.135-138, ⟨10.1109/HST.2016.7495571⟩
Conference papers
lirmm-01434150v1
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Thoroughly analyzing the use of ring oscillators for on-chip hardware trojan detectionReConFig: ReConFigurable Computing and FPGAs, Dec 2015, Mexico, Mexico. pp.1-6, ⟨10.1109/ReConFig.2015.7393363⟩
Conference papers
lirmm-01354318v1
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Collision for Estimating SCA Measurement Quality and Related ApplicationsCARDIS: Smart Card Research and Advanced Applications, Nov 2015, Bochum, Germany. pp.143-157, ⟨10.1007/978-3-319-31271-2_9⟩
Conference papers
lirmm-01319093v1
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Interest of MIA in frequency domain?CS2: Cryptography and Security in Computing Systems, Jan 2015, Amtersdam, Netherlands. pp.35-38, ⟨10.1145/2694805.2694812⟩
Conference papers
lirmm-01111693v1
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Collision Based Attacks in PracticeDSD: Digital System Design, Aug 2015, Madeire, Portugal. pp.367-374, ⟨10.1109/DSD.2015.24⟩
Conference papers
lirmm-01269809v1
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EM Injection: Fault Model and LocalityFDTC: Fault Diagnosis and Tolerance in Cryptography, Sep 2015, Saint Malo, France. pp.3-13, ⟨10.1109/FDTC.2015.9⟩
Conference papers
lirmm-01319078v1
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Electromagnetic analysis, deciphering and reverse engineering of integrated circuits (E-MATA HARI)VLSI-SoC: Very Large Scale Integration - System-on-Chip, Oct 2014, Playa del Carmen, Mexico. pp.1-6, ⟨10.1109/VLSI-SoC.2014.7004189⟩
Conference papers
lirmm-01434592v1
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Efficiency of a glitch detector against electromagnetic fault injectionDATE 2014 - 17th Design, Automation and Test in Europe Conference and Exhibition, Mar 2014, Dresden, Germany. ⟨10.7873/DATE.2014.216⟩
Conference papers
lirmm-01096047v1
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On Adaptive Bandwidth Selection for Efficient MIACOSADE: Constructive Side-Channel Analysis and Secure Design, Apr 2014, Paris, France. pp.82-97, ⟨10.1007/978-3-319-10175-0_7⟩
Conference papers
lirmm-01096033v1
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ElectroMagnetic Analysis and Fault Injection onto Secure CircuitsVLSI-SoC: Very Large Scale Integration - System-on-Chip, Oct 2014, Mexico, Mexico. ⟨10.1109/VLSI-SoC.2014.7004182⟩
Conference papers
emse-01099025v1
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Evidence of a larger EM-induced fault modelCARDIS: Smart Card Research and Advanced Applications, Nov 2014, Paris, France. pp.245-259, ⟨10.1007/978-3-319-16763-3_15⟩
Conference papers
emse-01099037v1
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A frequency leakage model for SCAHOST 2014 - IEEE International Symposium on Hardware-Oriented Security and Trust, May 2014, Arlington, VA, United States. pp.97-100, ⟨10.1109/HST.2014.6855577⟩
Conference papers
lirmm-01096058v1
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Attacking Randomized Exponentiations Using Unsupervised LearningCOSADE: Constructive Side-Channel Analysis and Secure Design, Apr 2014, Paris, France. pp.144-160, ⟨10.1007/978-3-319-10175-0_11⟩
Conference papers
lirmm-01096039v1
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Electromagnetic Analysis on RSA Algorithm Based on RNSDSD: Digital System Design, Sep 2013, Santander, Spain. pp.345-352, ⟨10.1109/DSD.2013.44⟩
Conference papers
lirmm-00861215v1
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Voltage Spikes on the Substrate to Obtain Timing FaultsDSD: Digital System Design, Sep 2013, Santander, Spain. pp.483-486, ⟨10.1109/DSD.2013.146⟩
Conference papers
lirmm-01096076v1
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Temperature and Fast Voltage On-Chip Monitoring using Low-Cost Digital SensorsVARI: Workshop on CMOS Variability, Sep 2013, Karlsruhe, Germany
Conference papers
hal-01067982v1
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An evaluation of an AES implementation protected against EM analysisGLSVLSI: Great Lakes Symposium on VLSI, May 2013, Paris, France. pp.317-318, ⟨10.1145/2483028.2483120⟩
Conference papers
hal-00862787v1
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Practical Analysis of RSA Countermeasures Against Side-Channel Electromagnetic AttacksCARDIS: Smart Card Research and Advanced Applications, Nov 2013, Berlin, Germany. pp.200-215, ⟨10.1007/978-3-319-08302-5_14⟩
Conference papers
lirmm-01096070v1
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Magnetic Microprobe design for EM fault attackEMC EUROPE: Electromagnetic Compatibility, Sep 2013, Bruges, Belgium
Conference papers
hal-01893856v1
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Countermeasures against EM analysis for a secured FPGA-based AES implementationReConFig'13: International Conference on ReConFigurable Computing and FPGAs, Dec 2013, Cancun, Mexico. pp.1-6, ⟨10.1109/ReConFig.2013.6732274⟩
Conference papers
hal-00963133v1
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Yet Another Fault Injection Technique : by Forward Body Biasing InjectionYACC'2012: Yet Another Conference on Cryptography, Sep 2012, Porquerolles Island, France
Conference papers
lirmm-00762035v1
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Amplitude Demodulation-Based EM Analysis of Different RSA ImplementationsDATE: Design, Automation and Test in Europe, Mar 2012, Dresden, Germany. pp.1167-1172, ⟨10.1109/DATE.2012.6176670⟩
Conference papers
lirmm-00762023v1
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Electromagnetic Attacks on Ring Oscillator-Based True Random Number GeneratorCryptArchi: Cryptographic Architectures, Jun 2012, Saint-Etienne, France
Conference papers
ujm-00712545v1
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Local Condition Monitoring in Integrated Circuits Using a Set of Kolmogorov-Smirnov TestsMSC'2012: Multi-conference on Systems and Control, Oct 2012, Dubrovnik, Croatia. pp.001-010
Conference papers
lirmm-00762045v1
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SCA with Magnitude Squared CoherenceCARDIS: Smart Card Research and Advanced Applications, Nov 2012, Graz, Austria. pp.234-247, ⟨10.1007/978-3-642-37288-9_16⟩
Conference papers
lirmm-00762038v1
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Contactless Electromagnetic Active Attack on Ring Oscillator Based True Random Number GeneratorCOSADE: Constructive Side-Channel Analysis and Secure Design, May 2012, Darmstadt, Germany. pp.151-166, ⟨10.1007/978-3-642-29912-4_12⟩
Conference papers
ujm-00699618v1
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Embedding Statistical Tests for On-Chip Dynamic Voltage and Temperature MonitoringDAC: Design Automation Conference, Jun 2012, San Francisco, CA, United States. pp.994-999
Conference papers
lirmm-00762020v1
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SECNUM: an Open Characterizing Platform for Integrated CircuitsEuropean Workshop on Microelectronics Education (EWME), May 2012, Grenoble, France
Conference papers
hal-01139176v1
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Techniques for EM Fault Injection: Equipments and Experimental ResultsFDTC'2012: Fault Diagnosis and Tolerance in Cryptography, Sep 2012, Lewen, Belgium. pp.003-004
Conference papers
lirmm-00761778v1
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Countermeasures against EM Analysis10th CryptArchi Workshop - St-Etienne Goutelas 2012, Jun 2012, Saint-Etienne, France
Conference papers
emse-01130646v1
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Statistical Cells Timing Metrics CharacterizationFTFC: Faible Tension - Faible Consommation, Jun 2012, Paris, France
Conference papers
lirmm-00762131v1
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On the use of the EM medium as a fault injection meansCryptArchi: Cryptographic Architectures, Jun 2012, St-Etienne, France
Conference papers
emse-00742707v1
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Local EM perturbations into CMOS ring oscillator5th International Conference on Electromagnetic Near-Field Characterization and Imaging (ICONIC), Nov 2011, Rouen, France
Conference papers
hal-01904164v1
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Local and Direct Power Injection on CMOS Integrated CircuitsFDTC'2011: Fault Diagnosis and Tolerance in Cryptography, Sep 2011, Nara, Japan. pp.100-104, ⟨10.1109/FDTC.2011.18⟩
Conference papers
lirmm-00607868v1
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A Fully Integrated 32 nm MultiProbe for Dynamic PVT Measurements within Complex Digital SoCVARI: International Workshop on CMOS Variability, May 2011, Grenoble, France
Conference papers
hal-01067989v1
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A Secure D Flip-Flop against Side Channel AttacksPATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 2011, Madrid, Spain. pp.331-340, ⟨10.1007/978-3-642-24154-3_33⟩
Conference papers
lirmm-00762027v1
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Statistical Timing Characterization of Standard Cells with Semi-Monte-Carlo MethodVARI: Workshop on CMOS Variaility, May 2011, Grenoble, France
Conference papers
lirmm-00617593v1
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Sondes de champ proche pour l'injection de fautesJournée "Antenne de Champ Proche'' du GDR Ondes, 2011, Paris, France
Conference papers
hal-01904165v1
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Local ElectroMagnetic Coupling with CMOS Integrated Circuits8th International Workshop on Electromagnetic Compatibility of Integrated Circuits (EMC COMPO), 2011, Dubrovnik, Croatia. pp.137-141
Conference papers
hal-01904161v1
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Characterizing Statistical Cells Timing Metrics with Semi-Monte-Carlo MethodVLSI-SoC: Very Large Scale Integration - System-on-Chip, Oct 2011, Hong-Kong, China
Conference papers
lirmm-00617606v1
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SSTA with Cell-to-Cell Delay CorrelationsVARI: Workshop on CMOS Variability, May 2010, Montpellier, France
Conference papers
lirmm-00546322v1
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Differential Power Analysis Enhancement with Statistical PreprocessingDATE: Design, Automation and Test in Europe, 2010, Dresden, Germany. pp.1301-1304, ⟨10.1109/DATE.2010.5457007⟩
Conference papers
lirmm-00548738v1
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SSTA with Delay CorrelationsNEWCAS: New Circuits and Systems, Jun 2010, Montreal, QC, Canada. pp.261-266, ⟨10.1109/NEWCAS.2010.5603930⟩
Conference papers
lirmm-00504882v1
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Incoherence Analysis and its Application to Time Domain EM Analysis of Secure CircuitsAPEMC 2010 - Asia-Pacific Symposium on Electromagnetic Compatibility, Apr 2010, Beijing, China. pp.1039-1042, ⟨10.1109/APEMC.2010.5475481⟩
Conference papers
lirmm-00607894v1
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Voltage Scaling and Body Biasing Methodology for High Performance Hardwired LDPCICICDT: International Conference on Integrated Circuit Design & Technology, Jun 2010, Grenoble, France. pp.82-85, ⟨10.1109/ICICDT.2010.5510289⟩
Conference papers
lirmm-00546316v1
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Modeling Time Domain Magnetic Emissions of ICsPATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 2010, Grenoble, France. pp.238-249, ⟨10.1007/978-3-642-17752-1_24⟩
Conference papers
lirmm-00762033v1
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On-Chip Process Variability MonitoringVARI: Workshop on CMOS Variability, May 2010, Montpellier, France
Conference papers
lirmm-00546337v1
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Computing Delay Correlations in SSTAICICDT: International Conference on Integrated Circuit Design & Technology, Jun 2010, Grenoble, France. pp.130-133, ⟨10.1109/ICICDT.2010.5510277⟩
Conference papers
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Technological countermeasures for IC protection against EM AnalysisPAca Security Trends In embedded Security, Gardanne, France
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Digital Timing Slack Monitors and their Specific Insertion Flow for Adaptive Compensation of VariabilitiesPATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 2009, Delft, Netherlands. pp.266-275, ⟨10.1007/978-3-642-11802-9_31⟩
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Un nouveau système d'instrumentation en ligne pour la caractérisation et l'adaptation dynamique aux variationsFTFC: Faible Tension - Faible Consommation, Jun 2009, Neuchâtel, Suisse
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On-Chip Timing Slack MonitoringVLSI-SoC: Very Large Scale Integration - System-on-Chip, Oct 2009, Florianopolis, Brazil. pp.89-94, ⟨10.1109/VLSISOC.2009.6041336⟩
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Enhancing Electromagnetic Attacks using Spectral Coherence based CartographyVLSI-SoC 2009 - 17th IFIP International Conference on Very Large Scale Integration, Oct 2009, Florianopolis, Brazil. pp.11-16, ⟨10.1109/VLSISOC.2009.6041323⟩
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Fingerprinting Hardware Security Module Using ICs RadiationsEMC Compo 2009 - 7th International Workshop on Electromagnetic Compatibility of Integrated Circuits, Nov 2009, Toulouse, France
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Product On-Chip Process Compensation for Low Power and Yield EnhancementPATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 2009, Delft, Netherlands. pp.247-255, ⟨10.1007/978-3-642-11802-9_29⟩
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Etude de l'effet du boîtier sur l'immunité en champ proche des circuits intégrésTelecom 2009 & 6èmes JFMMA, Mar 2009, Agadir, Maroc. 4 p
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Evaluation on FPGA of Triple Rail Logic Robustness Against DPA and DEMADATE: Design, Automation and Test in Europe, 2009, Nice, France. pp.634-639, ⟨10.1109/DATE.2009.5090744⟩
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Interpreting SSTA Results with CorrelationPATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 2009, Delft, Netherlands. pp.16-25, ⟨10.1007/978-3-642-11802-9_6⟩
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Interpretation of SSTA ResultsFTFC: Faible Tension - Faible Consommation, Jun 2009, Neuchâtel, Switzerland
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Evaluation of Countermeasures against Electromagnetic AnalysisEMC Europe: Electromagnetic Compatibility, Jun 2009, Athens, Greece. ⟨10.1109/EMCEUROPE.2009.5189724⟩
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An Innovative Timing Slack Monitor for Variation Tolerant CircuitsICICDT: International Conference on IC Design & Technology, May 2009, Austin, TX, United States. pp.215-218, ⟨10.1109/ICICDT.2009.5166299⟩
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On-Chip Process Variability MonitoringDATE: Design, Automation and Test in Europe, Apr 2009, Nice, France
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Assessment of the Immunity of Unshielded Multicore Integrated Circuits to Near Field InjectionInternational Zurich Symposium on Electromagnetic Compatibility, France. pp.361-364
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Electromagnetic analyses of secure circuits: Results on FPGA & ASICMARITE : Centre d'ELectronique de l'Armement (CELAR), France
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Statistical Sizing of an eSRAM Dummy Bitline Driver for Read Margin Improvement in the Presence of Variability AspectsISVLSI'08: IEEE Computer Society Annual Symposium on VLSI, Apr 2008, Montpellier, France, pp.310-315
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Setup and Hold Timing Violations Induced by Process Variations, in a Digital MultiplierISVLSI: International Symposium on Very Large Scale Integration, Apr 2008, Montpellier, France. pp.316-321, ⟨10.1109/ISVLSI.2008.70⟩
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SSTA Considering Switching Process Induced CorrelationsAPCCAS: Asia Pacific Conference on Circuits and System, Nov 2008, Macao, China. pp.562-565, ⟨10.1109/APCCAS.2008.4746085⟩
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SSTA with Structure Correlations Considering input Slope and Output Load VariationsGDR SOC-SIP, Jun 2008, Paris, France. pp.3
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Impact de la variabilité des caractéristiques temporelles des cellules combinatoires et séquentielles sur un opérateur numériqueFTFC: Faible Tension - Faible Consommation, May 2008, Louvain-La-Neuve, Belgique
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A Novel Dummy Bitline Driver for Read Margin Improvement in an eSRAMDELTA 2008 - 4th IEEE International Symposium on Electronic Design, Test and Applications, Jan 2008, Hong Kong, China. pp.107-110, ⟨10.1109/DELTA.2008.72⟩
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SSTA Considering Effects of Structure Correlations, Input Slope and Output Load VariationsFTFC: Faible Tension - Faible Consommation, May 2008, Louvain-la-Neuve, Belgium. pp.39-43
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Conditional Moments based SSTA Considering Switching Process Induced CorrelationsDCIS: Design of Circuits and Integrated Systems, Nov 2008, Grenoble, France. pp.70-77
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Étude des violations de temps d'établissement et de maintien dues aux variations du processus de fabrication dans un opérateur arithmétiqueJNRDM 2008 - 11e Journées Nationales du Réseau Doctoral de Microélectronique, May 2008, Bordeaux, France
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Near-field Mapping System to Scan in Time Domain the Magnetic Emissions of Integrated CircuitsPATMOS: Power and Timing Modeling Optimization and Simulation, Sep 2008, Lisbon, Portugal. pp.229-236, ⟨10.1007/978-3-540-95948-9_23⟩
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Evaluating the Robustness of Secure Triple Track Logic Through PrototypingSBCCI'08: Symposium on Integrated Circuits and Systems Design, Sep 2008, Gramado, Brazil, France. pp.193-198, ⟨10.1145/1404371.1404425⟩
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SSTA with Correlations Considering input Slope and Output Load VariationsVLSI-SoC: Very Large Scale Integration - System-on-Chip, Oct 2008, Rhodes Island, Greece. pp.164-167
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Prototyping Secure Triple Track Logic (STTL) Robustness Against DPA & DEMA on FPGACryptArchi: Cryptographic Architectures, Jun 2008, Tregastel, France
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Triple Rail Logic Robustness against DPAReConFig 2008 - International Conference on Reconfigurable Computing and FPGAs, Dec 2008, Cancun, Mexico. pp.415-420, ⟨10.1109/ReConFig.2008.75⟩
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Variabilité de Process et Performances des Mémoires SRAM EmbarquéesFTFC'07: 6èmes Journées d'Etudes Faible Tension Faible Consommation, May 2007, Paris, France, pp.7-11
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Analysis and Improvement of Dual Rail Logic as a Countermeasure Against DPAPATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 2007, Gothenburg, Sweden. pp.340-351, ⟨10.1007/978-3-540-74442-9_33⟩
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A Simple Statistical Timing Analysis Flow and Its Application to Timing Margin EvaluationFTFC: Faible Tension - Faible Consommation, May 2007, Paris, France. pp.19-25
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Improvement of Dual Rail Logic as a Countermeasure Against DPAVLSI-SoC 2007 - IFIP International Conference on Very Large Scale Integration, Oct 2007, Atlanta, GA, United States. pp.270-275, ⟨10.1109/VLSISOC.2007.4402510⟩
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Temperature and Voltage Aware Timing Analysis: Application to Voltage DropsDATE: Design, Automation and Test in Europe, Mar 2007, Nice, France. ⟨10.1109/DATE.2007.364426⟩
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A Simple Statistical Timing Analysis Flow and its Application to Timing Margin EvaluationPATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 2007, Gothenburg, Sweden. pp.138-147, ⟨10.1007/978-3-540-74442-9_14⟩
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Process Variabilities and Performances in a 90nm embedded SRAMIEEE International Integrated Reliability Workshop, Oct 2007, pp.050-055
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A Model of DPA Syndrome and Its Application to the Identification of Leaking GatesPATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 2007, Gothenburg, Sweden. pp.394-403, ⟨10.1007/978-3-540-74442-9_38⟩
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Méthodologie d'estimation de l'influence de la variabilité sur un opérateur numériqueFTFC 2007 - 6e journées d'Etudes Faible Tension Faible Consommation, May 2007, Paris, France
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Une Famille d'Additionneurs Asynchrones CMOS Bundled Data à Temps de Calcul Dépendant aux DonnéesFTFC: Faible Tension - Faible Consommation, May 2007, Paris, France. pp.75-80
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Process Variability Considerations in the Design of an eSRAMMTDT 2007 - IEEE International Workshop on Memory Technology, Design and Testing, Dec 2007, Taipei, Taiwan. pp.23-26, ⟨10.1109/MTDT.2007.4547609⟩
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Circuit Performance Optimization under Delay ConstraintsDCIS: Design of Circuits and Integrated Systems, Nov 2006, Barcelona, Spain
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Security Evaluation of Dual Rail Logic Against DPA AttacksVLSI-SoC 2006 - 14th IFIP International Conference on Very Large Scale Integration, Oct 2006, Nice, France. pp.181-186, ⟨10.1109/VLSISOC.2006.313230⟩
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Request-Skip Adders: CMOS Standard Cell Data Dependent AddersICECS: International Conference on Electronics, Circuits and Systems, Dec 2006, Nice, France. pp.510-513, ⟨10.1109/ICECS.2006.379837⟩
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Circuit Sizing Method under Delay ConstraintISCAS: International Symposium on Circuits and Systems, May 2006, Island of Kos, Greece. pp.5123-5126, ⟨10.1109/ISCAS.2006.1693785⟩
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Statistical Characterization of Library Timing PerformancePATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 2006, Montpellier, France. pp.468-476, ⟨10.1007/11847083_45⟩
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Timing Analysis in Presence of Voltage Drops and Temperature GradientsTAU: Timing Issues in the Specification and Synthesis of Digital Systems, Feb 2006, San Jose, CA, United States. pp.28-34
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Timing Analysis in Presence of Supply Voltage and Temperature VariationsISPD: International Symposium on Physical Design, Apr 2006, San Jose, CA, United States. pp.10-16, ⟨10.1145/1123008.1123012⟩
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Exploration of the Area-Latency Tradeoff of Asynchronous CMOS data Dependent AddersDCIS: Design of Circuits and Integrated Systems, Nov 2006, Barcelona, Spain
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Une Famille d'Additionneur Asynchrones CMOS à Temps de Calcul Dépendant de DonnéesJNRDM: Journées Nationales du Réseau Doctoral de Microélectronique, May 2006, Rennes, France. pp.469-472
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Low Power Oriented CMOS Circuit Optimization ProtocolDATE 2005 - 8th Design, Automation and Test in Europe Conference and Exhibition, Mar 2005, Munich, Germany. pp.640-645, ⟨10.1109/DATE.2005.202⟩
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Additionneurs RCA Data Dependent MicropipelinesFTFC: Faible Tension - Faible Consommation, May 2005, Paris, France. pp.183-188
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Synthèse Physique et Optimisation des Performances au Niveau TransistorFTFC: Faible Tension - Faible Consommation, May 2005, Paris, France. pp.91-95
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Ripple Carry Adder for Micropipeline CircuitsDCIS 2005 - 20th Conference on Design of Circuits and Integrated Systems, Nov 2005, Lisbonne, Portugal
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La Technologie Asynchrone QDI pour la Sécurité des CryptosystèmesJNRDM 2005 - 8e Journées Nationales du Réseau Doctoral de Microélectronique, May 2005, Paris, France. pp.461-463
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A Method to Design Compact Dual-rail Asynchronous PrimitivesPATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 2005, Leuven, Belgium. pp.571-580, ⟨10.1007/11556930_58⟩
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Circuit Optimization Based on Speed IndicatorsICECS: International Conference on Electronics, Circuits and Systems, Dec 2005, Gammarth, Tunisia. pp.167-170, ⟨10.1109/icecs.2005.4633585⟩
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Design of Compact Dual Rail Asynchronous PrimitivesDCIS 2005 - 20th Conference on Design of Circuits and Integrated Systems, 2005, Lisbonne, Portugal
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Temperature Dependency in UDSM ProcessPATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 2005, Leuven, Belgium. pp.693-703, ⟨10.1007/11556930_71⟩
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Path Optimization Protocol Based on Speed Low Power MetricsEUROCON: International Conference on "Computer as a Tool", Nov 2005, Belgrade, Serbia. pp.523-526, ⟨10.1109/EURCON.2005.1629980⟩
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lirmm-00106428v1
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Asynchronous Dual rail Cells to Secure Cryptosystem Against Side Channel AttacksSAME'05: Sophia-Antipolis Forum on MicroElectronics, Oct 2005, Sophia-Antipolis
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Méthode de Conception de Primitives Asynchrones Double RailFTFC'05 : 5èmes Journées d'Etudes Francophones Faible Tension - Faible Consommation, May 2005, Paris, France, pp.23-27
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lirmm-00106003v1
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Protocole d'Optimisation de Circuit CMOS Orienté Basse PuissanceFTFC: Faible Tension - Faible Consommation, May 2005, Paris, France. pp.17-22
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Speed Indicators for Circuit OptimizationPATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 2005, Leuven, Belgium. pp.618-628, ⟨10.1007/11556930_63⟩
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Optimization Protocol Based on Low Power MetricsIWLS: International Workshop on Logic Synthesis, Jun 2005, Lake Arrowhead Resort, CA, United States. pp.288-293
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lirmm-00106018v1
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Definition of P/N Width Ratio for CMOS Standard Cell LibraryDCIS: Design of Circuits and Integrated Systems, Nov 2004, Bordeaux, France. pp.769-773
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RC on-chip interconnect Performance revisitedDCIS: Design of Circuits and Integrated Systems, Nov 2004, Bordeaux, France. pp.809-814
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Physical Extension of the Logical Effort ModelPATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 2004, Santorini, Greece. pp.838-848, ⟨10.1007/978-3-540-30205-6_86⟩
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Optimization Protocol Based on Performance Metric |