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Sophie Dupuis
Associate Professor,
LIRMM (Montpellier University/CNRS) microelectronics department,
IUT of Montpellier department of Electrical Engineering and Industrial IT
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Documents
Current affiliations
- 1100642
Researcher identifiers
sophie-dupuis-
0000-0002-4876-2982
- Google Scholar : https://scholar.google.fr/citations?user=BIC4uX8AAAAJ
Presentation
Je suis maîtresse de Conférences au LIRMM (Montpellier, France) depuis 2011.
J'ai obtenu un DEA en Architecture des Systèmes Intégrés et Microélectronique puis une thèse de doctorat en microélectronique (intitulée Optimisation automatique des chemins de données arithmétiques par l’utilisation des systèmes de numérations redondants) à l'Université Pierre et Marie Curie (Paris, France) en 2004 et 2009 respectivement.
Mes intérêts de recherche actuels incluent plusieurs facettes de la conception de circuits numériques, en mettant l'accent sur la confiance matérielle.
Je suis responsable des études 2ème et 3ème année du BUT GEII, en formation initiale et enseigne principalement l'électronique numérique et la programmation/algorithmique.
I have been aa associate professor at LIRMM (Montpellier, France) since 2011.
I obtained a Master in Integrated Systems Architecture and Microelectronics, and then a PhD in microelectronics (entitled: Automatic optimization of arithmetic data paths through the use of redundant arithmetic) at Pierre and Marie Curie University (Paris, France) in 2004 and 2009 respectively.
My current research interests include several facets of digital circuit design, with an emphasis on hardware trust.
I am responsible for 2nd and 3rd year studies at BUT GEII, in initial training and mainly teach digital electronics and programming/algorithmic.
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Power Analysis Attack Against post-SAT Logic Locking schemesETS 2024 - 29th IEEE European Test Symposium, May 2024, The Hague, Netherlands. pp.1-6, ⟨10.1109/ETS61313.2024.10567311⟩
Conference papers
lirmm-04628663v1
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Logic Locking: Exploration of a new key-gate based on tristate logicLATS 2024 - 25th IEEE Latin American Test Symposium, Apr 2024, Maceio, Brazil
Conference papers
lirmm-04564164v1
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Resynthesis-based Attacks Against Logic LockingISQED 2023 - 24th International Symposium on Quality Electronic Design, Apr 2023, San Fransisco, CA, United States
Conference papers
lirmm-04053224v1
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A new key-gate insertion strategy for logic locking with high output corruptionTHCon 2022 - Toulouse Hacking Convention, ENAC, Apr 2022, Toulouse, France
Conference papers
lirmm-04048983v1
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On Preventing SAT Attack with Decoy Key-InputsISVLSI 2021 - IEEE Computer Society Annual Symposium on VLSI, Jul 2021, Tampa, United States. pp.114-119, ⟨10.1109/ISVLSI51109.2021.00031⟩
Conference papers
lirmm-03359458v1
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High-level Intellectual Property Obfuscation via Decoy ConstantsIOLTS 2021 - 27th IEEE International Symposium on On-Line Testing and Robust System Design, Jun 2021, Torino, Italy. pp.1-7, ⟨10.1109/IOLTS52814.2021.9486714⟩
Conference papers
lirmm-03359476v1
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Development and Application of Embedded Test Instruments to Digital, Analog/RFs and Secure ICsIOLTS 2020 - 26th IEEE International Symposium on On-Line Testing and Robust System Design, Jul 2020, Napoli, Italy. pp.1-4, ⟨10.1109/IOLTS50870.2020.9159723⟩
Conference papers
lirmm-02993384v1
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A Secure Scan Controller for Protecting Logic LockingIOLTS 2020 - 26th IEEE International Symposium on On-Line Testing and Robust System Design, Jul 2020, Napoli, Italy. pp.1-6, ⟨10.1109/IOLTS50870.2020.9159730⟩
Conference papers
lirmm-02995199v1
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A Comprehensive Approach to a Trusted Test InfrastructureIVSW 2019 - 4th IEEE International Verification and Security Workshop, Jul 2019, Rhodes, Greece. pp.43-48, ⟨10.1109/IVSW.2019.8854428⟩
Conference papers
lirmm-02306980v1
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Providing Confidentiality and Integrity in Ultra Low Power IoT DevicesDTIS 2019 - 14th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, Apr 2019, Mykonos, Greece. ⟨10.1109/DTIS.2019.8735090⟩
Conference papers
hal-02166920v1
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Encryption of test data: which cipher is better?PRIME: PhD Research in Microelectronics and Electronics, Jul 2018, Prague, Czech Republic. pp.85-88, ⟨10.1109/PRIME.2018.8430366⟩
Conference papers
lirmm-01867249v1
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SI ECCS: SECure context saving for IoT devicesDTIS 2018 - 13th International Conference on Design and Technology of Integrated Systems in Nanoscale Era, Apr 2018, Taormina, Italy. ⟨10.1109/DTIS.2018.8368561⟩
Conference papers
hal-01740173v1
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A Novel Use of Approximate Circuits to Thwart Hardware Trojan Insertion and Provide ObfuscationIOLTS: International Symposium on On-Line Testing And Robust System Design, Jul 2018, Platja d'Aro, Spain. pp.41-42, ⟨10.1109/IOLTS.2018.8474077⟩
Conference papers
lirmm-02095736v1
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A new secure stream cipher for scan chain encryption3rd IEEE International Verification and Security Workshop (IVSW 2018), Jul 2018, Platja d’Aro, Spain. pp.68-73, ⟨10.1109/IVSW.2018.8494852⟩
Conference papers
lirmm-01867256v1
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Hacking the Control Flow error detection mechanismIVSW: International Verification and Security Workshop, Jul 2017, Thessaloniki, Greece. pp.51-56, ⟨10.1109/IVSW.2017.8031544⟩
Conference papers
lirmm-01700739v1
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Duplication-based Concurrent Detection of Hardware Trojans in Integrated CircuitsTRUDEVICE, Nov 2016, Barcelona, Spain
Conference papers
lirmm-01385551v1
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Hardware Trust through Layout Filling: a Hardware Trojan Prevention TechniqueISVLSI: International Symposium on Very Large Scale Integration, Jul 2016, Pittsburgh, United States. pp.254-259, ⟨10.1109/ISVLSI.2016.22⟩
Conference papers
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Using Outliers to Detect Stealthy Hardware Trojan Triggering?IVSW: International Verification and Security Workshop, Jul 2016, Sant Feliu de Guixols, France
Conference papers
lirmm-01347119v1
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Hardware Trojan Prevention using Layout-Level Design ApproachECCTD: European Conference on Circuit Theory and Design, Aug 2015, Trondheim, Norway. ⟨10.1109/ECCTD.2015.7300093⟩
Conference papers
lirmm-01234072v1
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New Testing Procedure for Finding Insertion Sites of Stealthy Hardware TrojansDATE 2015 - 18th Design, Automation and Test in Europe Conference and Exhibition, Mar 2015, Grenoble, France. pp.776-781, ⟨10.7873/DATE.2015.1102⟩
Conference papers
lirmm-01141619v1
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On the limitations of logic testing for detecting Hardware Trojans HorsesDTIS: Design and Technology of Integrated Systems in Nanoscale Era, Apr 2015, Naples, Italy. ⟨10.1109/DTIS.2015.7127362⟩
Conference papers
lirmm-01257837v1
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A Novel Hardware Logic Encryption Technique for thwarting Illegal Overproduction and Hardware TrojansIOLTS: International On-Line Testing Symposium, Jul 2014, Platja d'Aro, Girona, Spain. pp.49-54, ⟨10.1109/IOLTS.2014.6873671⟩
Conference papers
lirmm-01025275v1
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Identification of Hardware Trojans triggering signalsFirst Workshop on Trustworthy Manufacturing and Utilization of Secure Devices, May 2013, Avignon, France
Conference papers
lirmm-00991360v1
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Is Side-Channel Analysis really reliable for detecting Hardware Trojans?DCIS 2012 - 27th Conference on Design of Circuits and Integrated Systems, Nov 2012, Avignon, France. pp.238-242
Conference papers
lirmm-00823477v1
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Stratus: Free design of highly parametrized VLSI modules interoperable with commercial toolsISQED 2011 - 12th International Symposium on Quality Electronic Design, Mar 2011, Santa Clara, CA, United States. pp.502-507, ⟨10.1109/ISQED.2011.5770774⟩
Conference papers
hal-01265627v1
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Arithmetic Data path Optimization using Borrow-Save RepresentationISVLSI IEEE Computer Society Annual Symposium on Emerging VLSI, Apr 2008, Montpellier, France. pp.4-9, ⟨10.1109/ISVLSI.2008.29⟩
Conference papers
hal-01265632v1
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Automatic Allocation of Redundant Operators in Arithmetic Data path OptimizationDASIP IEEE International Conference on Design and Architectures for Signal and Image Processing, Nov 2008, Bruxelles, Belgium. pp.176-183
Conference papers
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Stratus: A procedural circuit description language based upon PythonICM International Conference on Microelectronics, Dec 2007, Cairo, Egypt. pp.275-278, ⟨10.1109/ICM.2007.4497707⟩
Conference papers
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Data Path Optimization using Redundant Arithmetic and Pattern MatchingWorkshop on Design and Architectures for Signal and Image Processing (DASIP'2007), Nov 2007, Grenoble, France. pp.281-288
Conference papers
hal-01265633v1
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Stratus : Un environnement de développement de circuitsJP CNFM Journées pédagogiques du CNFM, 2006, Saint-Malo, France. pp.57-61
Conference papers
hal-01265634v1
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Optimisation de chemins de données par l'utilisation de l'arithmétique redondanteJNRDM 2005 - 8èmes Journées Nationales du Réseau Doctoral en Microélectronique, May 2005, Paris, France. pp.268-270
Conference papers
hal-01418345v1
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Full key recovery for advanced Logic Locking SchemesConference poster lirmm-04689311v1 |
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Logic-Locking schemes and side channel attacks resilienceSAFEST Workshop, Jun 2023, Tallinn (Virtual), Estonia
Conference poster
lirmm-04526269v1
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SECCS: SECure Context Saving for IoT Devices12e Colloque National du GDR SoC/SiP, Jun 2018, Paris, France. 2018
Conference poster
hal-02042659v1
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Des jeux vidéo pour l'enseignement du langage CCETSIS: Colloque sur l'Enseignement des Technologies et des Sciences de l'Information et des Systèmes, May 2017, Le Mans, France. 2017
Conference poster
lirmm-01522447v1
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« Pong » en VHDLJournées pédagogiques du CNFM, Nov 2016, Montpellier, France. 2016
Conference poster
lirmm-01430000v1
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Detection and Prevention of Hardware Trojan through Logic TestingTRUDEVICE, Nov 2016, Barcelona, Spain. , 4th Workshop on Trustworthy Manufacturing and Utilization of Secure Devices, Manufacturing test of secure devices / Reverse engineering countermeasures / Other topics, pp.#33, 2016, Posters IV
Conference poster
lirmm-01430007v1
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Mise en œuvre d'un capteur de température par bus I2CCETSIS: Colloque sur l'Enseignement des Technologies et des Sciences de l'Information et des Systèmes, Oct 2014, Besançon, France. , 11ème Colloque sur l'Enseignement des Technologies et des Sciences de l'Information et des Systèmes, pp.001-007, 2014
Conference poster
lirmm-01056402v1
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Optimisation des chemins de données arithmétiques par l'utilisation des systèmes de numération redondantsArithmétique des ordinateurs. Université Pierre et Marie Curie Paris VI, 2009. Français. ⟨NNT : ⟩
Theses
tel-01348675v1
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