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Logic Locking: Exploration of a new key-gate based on tristate logic
Sophie Dupuis
,
Nassim Riadi
,
Clémy Moroukian
,
Florence Azaïs
,
Marie-Lise Flottes
Conference papers
lirmm-04564164
v1
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Power Analysis Attack Against post-SAT Logic Locking schemes
Nassim Riadi
,
Florent Bruguier
,
Pascal Benoit
,
Sophie Dupuis
,
Marie-Lise Flottes
Conference papers
lirmm-04628663
v1
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Resynthesis-based Attacks Against Logic Locking
Felipe Almeida
,
Levent Aksoy
,
Quang-Linh Nguyen
,
Sophie Dupuis
,
Marie-Lise Flottes
et al.
Conference papers
lirmm-04053224
v1
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A new key-gate insertion strategy for logic locking with high output corruption
Quang-Linh Nguyen
,
Sophie Dupuis
,
Marie-Lise Flottes
THCon 2022 - Toulouse Hacking Convention, ENAC, Apr 2022, Toulouse, France
Conference papers
lirmm-04048983
v1
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High-level Intellectual Property Obfuscation via Decoy Constants
Levent Aksoy
,
Quang-Linh Nguyen
,
Felipe Almeida
,
Jaan Raik
,
Marie-Lise Flottes
et al.
Conference papers
lirmm-03359476
v1
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On Preventing SAT Attack with Decoy Key-Inputs
Quang-Linh Nguyen
,
Marie-Lise Flottes
,
Sophie Dupuis
,
Bruno Rouzeyre
Conference papers
lirmm-03359458
v1
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A Secure Scan Controller for Protecting Logic Locking
Quang-Linh Nguyen
,
Emanuele Valea
,
Marie-Lise Flottes
,
Sophie Dupuis
,
Bruno Rouzeyre
Conference papers
lirmm-02995199
v1
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Development and Application of Embedded Test Instruments to Digital, Analog/RFs and Secure ICs
Florence Azaïs
,
Serge Bernard
,
Mariane Comte
,
Bastien Deveautour
,
Sophie Dupuis
et al.
Conference papers
lirmm-02993384
v1
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A Comprehensive Approach to a Trusted Test Infrastructure
Marc Merandat
,
Vincent Reynaud
,
Emanuele Valea
,
Jerome Quevremont
,
Nicolas Valette
et al.
Conference papers
lirmm-02306980
v1
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Providing Confidentiality and Integrity in Ultra Low Power IoT Devices
Emanuele Valea
,
Mathieu da Silva
,
Marie-Lise Flottes
,
Giorgio Di Natale
,
Sophie Dupuis
et al.
DTIS 2019 - 14th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, Apr 2019, Mykonos, Greece. ⟨10.1109/DTIS.2019.8735090⟩
Conference papers
hal-02166920
v1
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A new secure stream cipher for scan chain encryption
Mathieu da Silva
,
Emanuele Valea
,
Marie-Lise Flottes
,
Sophie Dupuis
,
Giorgio Di Natale
et al.
3rd IEEE International Verification and Security Workshop (IVSW 2018), Jul 2018, Platja d’Aro, Spain. pp.68-73, ⟨10.1109/IVSW.2018.8494852⟩
Conference papers
lirmm-01867256
v1
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A Novel Use of Approximate Circuits to Thwart Hardware Trojan Insertion and Provide Obfuscation
Honorio Martin
,
Luis Entrena
,
Sophie Dupuis
,
Giorgio Di Natale
IOLTS: International Symposium on On-Line Testing And Robust System Design, Jul 2018, Platja d'Aro, Spain. pp.41-42, ⟨10.1109/IOLTS.2018.8474077⟩
Conference papers
lirmm-02095736
v1
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Encryption of test data: which cipher is better?
Mathieu da Silva
,
Emanuele Valea
,
Marie-Lise Flottes
,
Sophie Dupuis
,
Giorgio Di Natale
et al.
Conference papers
lirmm-01867249
v1
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SI ECCS: SECure context saving for IoT devices
Emanuele Valea
,
Mathieu da Silva
,
Giorgio Di Natale
,
Marie-Lise Flottes
,
Sophie Dupuis
et al.
DTIS 2018 - 13th International Conference on Design and Technology of Integrated Systems in Nanoscale Era, Apr 2018, Taormina, Italy. ⟨10.1109/DTIS.2018.8368561⟩
Conference papers
hal-01740173
v1
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Hacking the Control Flow error detection mechanism
Giorgio Di Natale
,
Marie-Lise Flottes
,
Sophie Dupuis
,
Bruno Rouzeyre
Conference papers
lirmm-01700739
v1
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Using Outliers to Detect Stealthy Hardware Trojan Triggering?
Papa-Sidy Ba
,
Sophie Dupuis
,
Marie-Lise Flottes
,
Giorgio Di Natale
,
Bruno Rouzeyre
IVSW: International Verification and Security Workshop, Jul 2016, Sant Feliu de Guixols, France
Conference papers
lirmm-01347119
v1
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Duplication-based Concurrent Detection of Hardware Trojans in Integrated Circuits
Manikandan Palanichamy
,
Papa-Sidy Ba
,
Sophie Dupuis
,
Marie-Lise Flottes
,
Giorgio Di Natale
et al.
TRUDEVICE, Nov 2016, Barcelona, Spain
Conference papers
lirmm-01385551
v1
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Hardware Trust through Layout Filling: a Hardware Trojan Prevention Technique
Papa-Sidy Ba
,
Sophie Dupuis
,
Manikandan Palanichamy
,
Marie-Lise Flottes
,
Giorgio Di Natale
et al.
ISVLSI: International Symposium on Very Large Scale Integration, Jul 2016, Pittsburgh, United States. pp.254-259, ⟨10.1109/ISVLSI.2016.22⟩
Conference papers
lirmm-01346529
v1
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Hardware Trojan Prevention using Layout-Level Design Approach
Papa-Sidy Ba
,
Manikandan Palanichamy
,
Sophie Dupuis
,
Marie-Lise Flottes
,
Giorgio Di Natale
et al.
Conference papers
lirmm-01234072
v1
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New Testing Procedure for Finding Insertion Sites of Stealthy Hardware Trojans
Sophie Dupuis
,
Bruno Rouzeyre
,
Marie-Lise Flottes
,
Giorgio Di Natale
,
Papa-Sidy Ba
DATE 2015 - 18th Design, Automation and Test in Europe Conference and Exhibition, Mar 2015, Grenoble, France. pp.776-781, ⟨10.7873/DATE.2015.1102⟩
Conference papers
lirmm-01141619
v1
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On the limitations of logic testing for detecting Hardware Trojans Horses
Marie-Lise Flottes
,
Sophie Dupuis
,
Papa-Sidy Ba
,
Bruno Rouzeyre
Conference papers
lirmm-01257837
v1
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A Novel Hardware Logic Encryption Technique for thwarting Illegal Overproduction and Hardware Trojans
Sophie Dupuis
,
Papa-Sidy Ba
,
Giorgio Di Natale
,
Marie-Lise Flottes
,
Bruno Rouzeyre
Conference papers
lirmm-01025275
v1
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Identification of Hardware Trojans triggering signals
Sophie Dupuis
,
Giorgio Di Natale
,
Marie-Lise Flottes
,
Bruno Rouzeyre
First Workshop on Trustworthy Manufacturing and Utilization of Secure Devices, May 2013, Avignon, France
Conference papers
lirmm-00991360
v1
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Is Side-Channel Analysis really reliable for detecting Hardware Trojans?
Giorgio Di Natale
,
Sophie Dupuis
,
Bruno Rouzeyre
DCIS 2012 - 27th Conference on Design of Circuits and Integrated Systems, Nov 2012, Avignon, France. pp.238-242
Conference papers
lirmm-00823477
v1
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Stratus: Free design of highly parametrized VLSI modules interoperable with commercial tools
Sophie Belloeil
,
Roselyne Chotin-Avot
,
Habib Mehrez
ISQED 2011 - 12th International Symposium on Quality Electronic Design, Mar 2011, Santa Clara, CA, United States. pp.502-507, ⟨10.1109/ISQED.2011.5770774⟩
Conference papers
hal-01265627
v1
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Automatic Allocation of Redundant Operators in Arithmetic Data path Optimization
Sophie Belloeil
,
Roselyne Chotin-Avot
,
Habib Mehrez
,
Alix Munier-Kordon
DASIP IEEE International Conference on Design and Architectures for Signal and Image Processing, Nov 2008, Bruxelles, Belgium. pp.176-183
Conference papers
hal-01265631
v1
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Arithmetic Data path Optimization using Borrow-Save Representation
Sophie Belloeil
,
Roselyne Chotin-Avot
,
Habib Mehrez
ISVLSI IEEE Computer Society Annual Symposium on Emerging VLSI, Apr 2008, Montpellier, France. pp.4-9, ⟨10.1109/ISVLSI.2008.29⟩
Conference papers
hal-01265632
v1
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Data Path Optimization using Redundant Arithmetic and Pattern Matching
Sophie Belloeil
,
Roselyne Chotin-Avot
,
Habib Mehrez
Workshop on Design and Architectures for Signal and Image Processing (DASIP'2007), Nov 2007, Grenoble, France. pp.281-288
Conference papers
hal-01265633
v1
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Stratus: A procedural circuit description language based upon Python
Sophie Belloeil
,
Damien Dupuis
,
Christian Masson
,
Jean-Paul Chaput
,
Habib Mehrez
Conference papers
hal-01305970
v1
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Stratus : Un environnement de développement de circuits
Sophie Belloeil
,
Jean-Paul Chaput
,
Roselyne Chotin-Avot
,
Christian Masson
,
Habib Mehrez
JP CNFM Journées pédagogiques du CNFM, 2006, Saint-Malo, France. pp.57-61
Conference papers
hal-01265634
v1
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Optimisation de chemins de données par l'utilisation de l'arithmétique redondante
Sophie Belloeil
,
Habib Mehrez
JNRDM 2005 - 8èmes Journées Nationales du Réseau Doctoral en Microélectronique, May 2005, Paris, France. pp.268-270
Conference papers
hal-01418345
v1
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