Alessandro Palumbo

16
Documents

Publications

Publications

Image document

The First Hardware Circuit Emulating Italian Road Homicides Legal Logic, DAJE!

Grazia Garzo , Alessandro Palumbo
IS 2025 - 18th IADIS International Conference Information Systems, Mar 2025, Madeira island, Portugal. pp.1-8
Communication dans un congrès hal-04990194 v1
Image document

Detecting Hardware Trojans in Microprocessors via Hardware Error Correction Code-based Modules

Alessandro Palumbo , Ruben Salvador
The 31st IEEE International Symposium on On-Line Testing and Robust System Design (IOLTS 2025), Jul 2025, Naples, Italy
Communication dans un congrès hal-05055204 v1
Image document

Leveraging gem5 for Hardware Trojan Research: Simulation for Machine-Learning-Based Detection

Alessandro Palumbo , Ruben Salvador
10th International Workshop on Malicious Software and Hardware in the Internet of Things (MAL-IoT 2025), May 2025, Cagliari, Italy. ⟨10.1145/3706594.3728869⟩
Communication dans un congrès hal-05044677 v1
Image document

Legal & Ethical Implications of Predictive Digital Techniques in the Judicial Criminal Proceedings

Grazia Garzo , Alessandro Palumbo
ISDFS 2025 - 13th International Symposium on Digital Forensics and Security, Apr 2025, Boston, United States
Communication dans un congrès hal-05021547 v1
Image document

Human-in-the-Loop: Legal Knowledge Formalization in Attempto Controlled English

Grazia Garzo , Alessandro Palumbo
ISDFS - 13th International Symposium on Digital Forensics and Security, Apr 2025, Boston, United States
Communication dans un congrès hal-05021540 v1
Image document

Machine Learning-Based Classification of Hardware Trojans in FPGAs Implementing RISC-V Cores

Stefano Ribes , Fabio Malatesta , Grazia Garzo , Alessandro Palumbo
ICISSP 2024 - 10th International Conference on Information Systems Security and Privacy, Feb 2024, Rome, Italy. pp.1-8, ⟨10.5220/0012324200003648⟩
Communication dans un congrès hal-04685628 v1
Image document

Opening the Black Box: How Boolean AI can Support Legal Analysis

Grazia Garzo , Stefano Ribes , Alessandro Palumbo
CCAI 2024 - 4th International Conference on Computer Communication and Artificial Intelligence, May 2024, Xi'an, China. pp.269 - 272, ⟨10.1109/ccai61966.2024.10603017⟩
Communication dans un congrès hal-04685601 v1
Image document

Built-in Software Obfuscation for Protecting Microprocessors against Hardware Trojan Horses

Alessandro Palumbo , Marco Ottavi , Luca Cassano
2023 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), Oct 2023, Juan-Les-Pins, France. ⟨10.1109/dft59622.2023.10313534⟩
Communication dans un congrès hal-04685515 v1
Image document

Towards Dependable RISC-V Cores for Edge Computing Devices

Pegdwende Romaric Nikiema , Alessandro Palumbo , Allan Aasma , Luca Cassano , Angeliki Kritikakou et al.
IOLTS 2023 – IEEE 29th International Symposium on On-Line Testing and Robust System Design, Jul 2023, Crete, Greece. ⟨10.1109/iolts59296.2023.10224862⟩
Communication dans un congrès hal-04685617 v1
Image document

Improving the Detection of Hardware Trojan Horses in Microprocessors via Hamming Codes

Alessandro Palumbo , Luca Cassano , Pedro Reviriego , Marco Ottavi
2023 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), Oct 2023, Juan-Les-Pins, France. ⟨10.1109/dft59622.2023.10313563⟩
Communication dans un congrès hal-04685537 v1
Image document

Is RISC-V ready for Space? A Security Perspective

Luca Cassano , Stefano Di Mascio , Alessandro Palumbo , Alessandra Menicucci , Gianluca Furano et al.
2022 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), Oct 2022, Austin, United States. ⟨10.1109/dft56152.2022.9962352⟩
Communication dans un congrès hal-04685569 v1
Image document

A Lightweight Security Checking Module to Protect Microprocessors against Hardware Trojan Horses

Alessandro Palumbo , Luca Cassano , Pedro Reviriego , Giuseppe Bianchi , Marco Ottavi
2021 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, Oct 2021, Remote, France. ⟨10.1109/dft52944.2021.9568291⟩
Communication dans un congrès hal-04685483 v1