Alexandre Honorat
- Laboratoire Jean Kuntzmann (LJK)
- Sustainability transition, environment, economy and local policy (STEEP)
- Centre Inria de l'Université Grenoble Alpes
Domaines de recherche
Publications
Publications
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Graph Transformations for Memory Peak Minimization by SchedulingACM Transactions on Embedded Computing Systems (TECS), 2025, pp.1-36. ⟨10.1145/3707206⟩ |
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Real-Time Fixed Priority Scheduling Synthesis using Affine DataFlow Graphs: from Theory to PracticeACM Transactions on Embedded Computing Systems (TECS), 2025, 24 (3), pp.45. ⟨10.1145/3615586⟩ |
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Automated Buffer Sizing of Dataflow Applications in a High-Level Synthesis WorkflowACM Transactions on Reconfigurable Technology and Systems (TRETS), 2024, 17 (1), pp.1-26. ⟨10.1145/3626103⟩ |
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Polychronous automata and their use for formal validation of AADL modelsFrontiers of Computer Science, 2019, 13 (4), pp.677-697. ⟨10.1007/s11704-017-6134-5⟩ |
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Parallel scheduling of task graphs with minimal memory requirementsIPDPS 2025 - 39th IEEE International Parallel and Distributed Processing Symposium, Jun 2025, Milano, Italy. pp.1-12 |
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Sequential Scheduling of Dataflow Graphs for Memory Peak MinimizationLCTES 2023 - 24th ACM SIGPLAN/SIGBED International Conference on Languages, Compilers, and Tools for Embedded Systems, Jun 2023, Orlando (FL), United States. pp.76-86, ⟨10.1145/3589610.3596280⟩ |
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Influence of Dataflow Graph Moldable Parameters on Optimization CriteriaDASIP 2022 - Workshop on Design and Architectures for Signal and Image Processing, Jun 2022, Budapest, Hungary. pp.83-95, ⟨10.1007/978-3-031-12748-9_7⟩ |
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A Framework for Fixed Priority Periodic Scheduling Synthesis from Synchronous Data-flow GraphsSAMOS XXI 2021 - 21st International Conference on embedded computer Systems: Architectures, MOdeling and Simulation, Jul 2021, Virtual, France. pp.1-12 |
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A Fast Heuristic to Pipeline SDF GraphsEmbedded Computer Systems: Architectures, Modeling, and Simulation, Jul 2020, Pythagorion, Samos Island, Greece. pp.139-151, ⟨10.1007/978-3-030-60939-9_10⟩ |
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Scheduling of Synchronous Dataflow Graphs with Partially Periodic Real-Time ConstraintsReal-Time Networks and Systems, Jun 2020, Paris, France. ⟨10.1145/3394810.3394820⟩ |
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Modeling Nested for Loops with Explicit Parallelism in Synchronous DataFlow GraphsEmbedded Computer Systems: Architectures, Modeling, and Simulation, Jul 2019, Pythagorion, Samos Island, Greece. pp.269-280, ⟨10.1007/978-3-030-27562-4_19⟩ |
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Efficient Contention-Aware Scheduling of SDF Graphs on Shared Multi-bank MemoryICECCS 2019 - 24th International Conference on Engineering of Complex Computer Systems, Nov 2019, Hong Kong, China. pp.114-123, ⟨10.1109/ICECCS.2019.00020⟩ |
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ADFG: a scheduling synthesis tool for dataflow graphs in real-time systemsInternational Conference on Real-Time Networks and Systems , Oct 2017, Grenoble, France. pp.1-10, ⟨10.1145/3139258.3139267⟩ |
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A Stencil DSEL for Single Code Accelerated Computing with SYCLSYCL 2016 1st SYCL Programming Workshop during the 21st ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, Mar 2016, Barcelone, Spain |
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Graph Transformations for Memory Peak Minimization by SchedulingRR-9554, Inria - Research Centre Grenoble – Rhône-Alpes. 2024, pp.1-42 |
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Modeling, Scheduling, Pipelining and Configuration of Synchronous Dataflow Graphs with Throughput ConstraintsSignal and Image processing. INSA de Rennes, 2020. English. ⟨NNT : 2020ISAR0010⟩ |