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Amer BAGHDADI
166
Documents
Researcher identifiers
amer-baghdadi
-
0000-0002-6181-6500
- IdRef : 067318398
Presentation
**Amer Baghdadi** is a Professor at IMT Atlantique. He received his Engineering degree in 1998, Master of Science degree in the same year and PhD degree in 2002, all from Grenoble INP (Institut National Polytechnique), France. Furthermore, he received the accreditation to supervise research (HDR) in Sciences and Technologies of Information and Communication in 2012 from the University of Southern Brittany, France.
His general technical area concerns both theoretical and practical aspects, and both algorithm development for digital baseband components and corresponding hardware/software implementations and digital circuit design. His research activities target mainly digital communication applications, in addition to other application domains, and more particularly the design of flexible digital physical layer for future wireless communication standards and terminals. Prof. Baghdadi is IEEE Senior Member. He serves on the technical program committee for several international conferences. He co-authored more than 100 papers on scientific journals and proceedings of international conferences.
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Proof-of-concept for post-OFDM waveforms as candidates for 5GSIPS 2017: IEEE International Workshop on Signal Processing Systems, Oct 2017, Lorient, France
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NoC-MRAM Architecture for Memory-Based Computing: database-search case studyNEWCAS 2017 : 15th IEEE International New Circuits and Systems Conference, Jun 2017, Strasbourg, France. ⟨10.1109/NEWCAS.2017.8010167⟩
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Hardware demonstration of post-OFDM waveformsEuCNC 2017: European Conference on Networks and Communications, Jun 2017, Oulu, Finland
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Towards Memristor-based Reconfigurable FFT ArchitectureICM 2017 : 29th IEEE International Conference on Microelectronics, Dec 2017, Beirut, Lebanon. ⟨10.1109/ICM.2017.8268885⟩
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Flexible PoC for Post-OFDM waveformsG5-PPP 2016 : 2nd Global 5G Infrastructure public private partnership event, Nov 2016, Rome, Italy
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CAASPER: Providing Accessible FPGA-acceleration over the NetworkRSP 2015 : 26th IEEE International Symposium on Rapid System Prototyping, Oct 2015, Amsterdam, Netherlands. pp.68 - 75, ⟨10.1109/RSP.2015.7416549⟩
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FBMC/OQAM-related new waveformEuCNC 2015 : 24th European Conference on Networks and Communications, Jun 2014, Bologna, Italy
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Energy-Efficient FPGA Implementation for Binomial Option Pricing Using OpenCLDATE 2014 : Design, Automation and Test in Europe, Mar 2014, Dresden, Germany
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Hardware Implementation of a Non-Coherent IR-UWB Receiver Synchronization Algorithm Targeting IEEE 802.15.6 Wireless BANICUWB 2014 : International Conference on Ultra-WideBand, Sep 2014, Paris, France. pp.444 - 449, ⟨10.1109/ICUWB.2014.6959023⟩
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Stopping-free dynamic configuration of a multi-ASIP turbo decoderDSD 2013 : 16th Euromicro Conference on Digital System Design, Sep 2013, Santander, Spain. pp.155 - 162
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Rapid Design and Prototyping of a Reconfigurable Decoder Architecture for QC-LDPC CodesRSP 2013 : 24th IEEE International Symposium on Rapid System Prototyping, Oct 2013, Montreal, Canada
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Quantization and fixed-point arithmetic for MIMO MMSE-IC linear turbo-equalizationICM 2013 : 25th IEEE International Conference on MicroelectronicsMicroelectronics, Dec 2013, Beirut, Lebanon. pp.1 - 4, ⟨10.1109/ICM.2013.6735008⟩
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A joint communication and application simulator for NoC-based custom SoCs: LDPC and turbo codes parallel decoding case studyDSD 2013 : 16th Euromicro Conference on Digital System Design, Sep 2013, Santander, Spain. pp.168 - 174
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Optimizations for an efficient reconfiguration of an ASIP-based turbo decoderISCAS 2013 : IEEE International Symposium on Circuits and Systems, May 2013, Beijing, Chine. pp.493 - 496, ⟨10.1109/ISCAS.2013.6571888⟩
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Flexible Multi-ASIP SoC for Turbo/LDPC DecoderSOC-SIP : colloque national du groupe de recherches System On Chip - System In Package, Jun 2012, Paris, France
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Management of reconfigurable multi-standards ASIP-based receiverSOC-SIP : colloque national du groupe de recherches System On Chip - System In Package, Jun 2011, Lyon, France
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Area and throughput optimized ASIP for multi-standard turbo decodingRSP 2011: 22nd IEEE International Symposium on Rapid System Prototyping, May 2011, Karlsruhe, Allemagne. pp.79 - 84, ⟨10.1109/RSP.2011.5929979⟩
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A flexible high throughput multi-ASIP architecture for LDPC and turbo decodingDATE'11: IEEE/ACM Design, Automation and Test in Europe Conference & Exhibition, Mar 2011, Grenoble, France
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Reducing the number of iterations in iterative demodulation with turbo decodingSoftCOM : International Conference on Software, Telecommunications and Computer Networks, Sep 2011, Split, Croatia
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Rapid design and prototyping of universal soft demapperISCAS : IEEE International Symposium on Circuits and Systems, May 2010, Paris, France
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Exploring parallel processing levels in turbo demodulationInternational Symposium on Turbo Codes and Iterative Information Processing, Sep 2010, Brest, France. pp.359 - 363, ⟨10.1109/ISTC.2010.5613904⟩
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TurbASIP power consumption analysis and optimizationColloque national du groupe de recherches System On Chip - System In Package (SOC-SIP), Jun 2010, Paris, France
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Power consumption analysis and energy efficient optimization for turbo decoder implementationInternational Symposium on System-on-Chip, Sep 2010, Tampere, Finland. pp.12 - 17, ⟨10.1109/ISSOC.2010.5625565⟩
Conference papers
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Iterative MIMO detection: flexibility and convergence analysis of soft-input soft-output list sphere decoding and linear MMSE detectionSoftCOM 2010 : International Conference on Software, Telecommunications and Computer Networks, Sep 2010, Split, Dubrovnik, Croatia. pp.175 - 179
Conference papers
hal-00876106v1
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DemASIP : universal demapper for multiwireless standardsColloque national du groupe de recherches "System On Chip - System In Package" (SOC-SIP), Jun 2010, Paris, France
Conference papers
hal-00632787v1
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ASIP-based flexible MMSE-IC linear equalizer for MIMO turbo-equalization applicationsDATE09 : Design, Automation & Test in Europe Conference & Exhibition, Apr 2009, Nice, France
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hal-00423920v1
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Flexible architectures for LDPC decoders based on network on chip paradigmDSD 2009 : 12th Euromicro Conference on Digital System Design, Sep 2009, Patras, Greece
Conference papers
hal-00423917v1
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FPGA prototypes for turbo communication applicationsUniversity Booth of DATE 09 : Design, Automation & Test in Europe Conference & Exhibition, Apr 2009, Nice, France
Conference papers
hal-01841144v1
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Rapid prototyping of ASIP-based flexible MMSE-IC linear equalizerRSP09 : IEEE International Symposium on Rapid System Prototyping, Jun 2009, Paris, France. pp.130-133, ⟨10.1109/RSP.2009.17⟩
Conference papers
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Shared resources high-level modeling in embedded systems using virtual nodesJoint IEEE North-East Workshop on Circuits and Systems and TAISA Conference 2009, Jun 2009, Toulouse, France. ⟨10.1109/NEWCAS.2009.5290506⟩
Conference papers
hal-00423997v1
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High-level system modeling for rapid HW/SW architecture explorationIEEE/IFIP International Symposium on Rapid System Prototyping (RSP '09), Jun 2009, Paris, France. pp.88-94, ⟨10.1109/RSP.2009.27⟩
Conference papers
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FPGA-based radar signal processing for automotive driver assistance systemRSP09 : IEEE/IFIP International Symposium on Rapid System Prototyping,, Jun 2009, Paris, France. pp.196-199, ⟨10.1109/RSP.2009.26⟩
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hal-00424189v1
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Binary de Bruijn on-chip network for a flexible multiprocessor LDPC decoderDAC 2008 : 45th ACM/IEEE design automation conference, Jun 2008, Anaheim, United States. pp.429 - 434, ⟨10.1109/DAC.2008.4555856⟩
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From application to ASIP-based FPGA prototype : a case study on turbo decodingRSP'2008 : the 19th IEEE/IFIP international symposium on rapid system prototyping, Jun 2008, Monterey, United States. pp.128 - 134, ⟨10.1109/RSP.2008.16⟩
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On-chip communication network for flexible multiprocessor turbo decodingICTTA '08 : 3d International Conference on Information and Communication Technologies : From Theory to Applications, Apr 2008, Damas, Syria. pp.1 - 6
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Binary de Bruijn interconnection network for a flexible LDPC/turbo decoderIEEE International Symposium on Circuits and Systems (ISCAS 2008), May 2008, Seattle, WA, United States. pp.97-100, ⟨10.1109/ISCAS.2008.4541363⟩
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hal-02194923v1
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Architectures des systèmes numériques de traitement : de l'électronique à l'informatique10èmes journées pédagogiques du CNFM (Coordination nationale de la formation en micro et nanoélectronique), Nov 2008, Saint Malo, France
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Flexible and scalable on-chip communication network for multiprocessor turbo decodingPremier Colloque National du GDR SOC-SIP, Jun 2007, Paris, France
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Butterfly and benes-based on-chip communication networks for multiprocessor turbo decodingDATEC 2007 : Design, Automation & Test in Europe Conference & Exhibition, Apr 2007, Nice, France. pp.654 - 659
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Flexible Multi-ASIP SoC for High-Throughput Turbo DecodersPremier Colloque National du GDR SOC-SIP, Jun 2007, Paris, France
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Millimetre communication system for IVCITST 2007 : 7th International Conference on ITS (Intelligent Transport Systems), Jun 2007, Sophia-Antipolis, France. ⟨10.1109/ITST.2007.4295879⟩
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Exploring parallel processing levels for convolutional turbo decodingICCTA'06 : IEEE International Conference on Information and Communication Technologies : from theory to applications, April 24-28, Damas, Syria, Apr 2006, Damas, Syria. pp.2353 - 2358
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On the parallelism of convolutional turbo decoding and interleaving interferenceGLOBECOM 2006 : 49th annual Global telecommunications conference, Nov 2006, San Francisco, United States. pp.1 - 5, ⟨10.1109/GLOCOM.2006.558⟩
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ASIP-based multiprocessor SoC design for simple and double binary turbo decodingDATE 06 : Design, Automation and Test in Europe, Mar 2006, Munich, Germany. pp.1 - 6, ⟨10.1109/DATE.2006.244126⟩
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Parallélisme et turbocodes convolutifsMajecSTIC 2006 : MAnifestation des JEunes Cherchercheurs STIC, Nov 2006, Lorient, France
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On the Flexibility and Scalability of Multiprocessor Embedded System Design for Emerging In-Vehicle Applications5th International Conference on ITS Telecommunications, Jun 2005, Brest, France
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An efficient scalable and flexible data transfer architecture for multiprocessor SoC with massive distributed memorySan Diego, CA, 2004, San Diego, United States. pp.250-5, ⟨10.1145/996566.996636⟩
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An Efficient Architecture for the Implementation of Message Passing Programming Model on Massive Multiprocessor SoC15th IEEE International Workshop on Rapid System Prototyping, Jun 2004, Genève, Suisse
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An efficient architecture for the implementation of message passing programming model on massive multiprocessorRSP 2004 : 15th IEEE International Workshop on Rapid System Prototyping, Jun 2004, Genève, Switzerland. pp.80-7
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Embedded application prototyping on a communication-restricted reconfigurable platformIWRSP 2003 : 14th IEEE International Workshop on Rapid Systems Prototyping, Jun 2003, San Diego, United States. pp.33-9, ⟨10.1109/IWRSP.2003.1207027⟩
Conference papers
hal-00008052v1
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Exploration et conception systématique d'architectures multiprocesseurs monopuces dédiées à des applications spécifiques3ème Colloque CAO de circuits et systèmes intégrés, May 2002, Paris, France
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Component-based design approach for multicore SoCs2002 Design Automation Conference, Jun 2002, New Orleans, United States. pp.789-94, ⟨10.1109/DAC.2002.1012730⟩
Conference papers
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HW/SW interfaces design of a VDSL modem using automatic refinement of a virtual architecture specification into a multiprocessor SoC: a case studyDesign, Automation and Test in Europe (DATE'02), Mar 2002, Paris, France
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Application-specific multiprocessor systems-on-chipThe Tenth Workshop on Synthesis And System Integration of Mixed Technologies (SASIMI'01), Oct 2001, Nara, Japan
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An efficient architecture model for systematic design of application-specific multiprocessor SoCDATE 2001 : Design, Automation and Test in Europe. Conference and Exhibition., Mar 2001, Munich, Germany. pp.55-62, ⟨10.1109/DATE.2001.915001⟩
Conference papers
hal-00008086v1
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Automatic generation of application-specific architectures for heterogeneous multiprocessor system-on-chipDAC '01 : 38th annual Design Automation Conference, 2001, Las Vegas, United States. pp.518-23, ⟨10.1145/378239.379015⟩
Conference papers
hal-00008074v1
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A generic wrapper architecture for multi-processor SoC cosimulation and designCODES '01 : Ninth international symposium on Hardware/software codesign, 2001, Copenhague, Denmark. pp.195-200, ⟨10.1145/371636.371722⟩
Conference papers
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Framework for system design, validation and fast prototyping of multiprocessor system-on-chip: applied to telecommunication systemsInternational Workshop on Distributed and Parallel Embedded Systems (DIPES'00), Jan 2000, Paderborn, Allemagne
Conference papers
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Generic architecture platform for multiprocessor embedded system-on-chip designInternational Workshop on Distributed and Parallel Embedded Systems (DIPES'00), Oct 2000, Paderborn, Allemagne. pp.53-64
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hal-01381242v1
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Generic architecture platform for multiprocessor system-on-chip designDIPES 2000: Architecture and Design of Distributed Embedded Systems, Oct 2000, Schloß Eringerfeld, Germany. pp.53-63
Conference papers
hal-00008077v1
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Design space exploration for hardware/software codesign of multiprocessor systemsRSP 2000 : 11th International Workshop on Rapid System Prototyping, Jun 2000, Paris, France. pp.8-13, ⟨10.1109/IWRSP.2000.854975⟩
Conference papers
hal-00008096v1
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Key Attack Strategies Against Black-Box DNNsConference poster hal-03690454v1 |
Flexible FBMC air interface for 5GMWC 2015 : Mobile World Congress, Mar 2015, Barcelona, Spain. 2015
Conference poster
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Designing a NISC-based flexible architecture for MIMO MMSE-IC turbo-equalizationJNRDM 2013 : 16èmes Journées Nationales du Réseau Doctoral en Micro-Nanoélectronique, Jun 2013, Grenoble, France. 2013
Conference poster
hal-00876046v1
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Application-Specific Processor Design: a Case-Study on MMSE MIMO equalizationGDR SoC-SiP 2013 : Colloque National du Groupe de Recherche System on Chip -System in Package, Jun 2013, Lyon, France. 2013
Conference poster
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Efficient dynamic configuration of a multi-ASIP turbo decoderGDR SoC-SiP 2013 : Colloque National du Groupe de Recherche System on Chip -System in Package, Jun 2013, Lyon, France
Conference poster
hal-00876017v1
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ASIP Design for Multi-Standard Channel DecodersAdvanced Hardware Design for Error Correcting Codes, Springer, pp.151 - 175, 2014, 978-3-319-10568-0. ⟨10.1007/978-3-319-10569-7⟩
Book sections
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ASIP design and prototyping for wireless communication applicationsAdvanced Applications of Rapid Prototyping Technology in Modern Engineering, InTech - Open Access Publisher, 2011
Book sections
hal-00699677v1
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Hardware/Software CodesignReis Ricardo, Lubaszewski Marcelo, Jess Jochen A.G. Design of Systems on Chip, Design and test, Springer, pp.133-158, 2007
Book sections
hal-00265185v1
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Hardware/Software Co-designDesign of Systems on a Chip : Design and Test, Springer, pp.133 - 158, 2007, 978-0-387-32499-9. ⟨10.1007/0-387-32500-X_7⟩
Book sections
hal-02124753v1
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Generic architecture platform for multiprocessor system-on-chip designArchitecture and Design of Distributed Embedded Systems, kluwer academic publishers, pp.53-63, 2001, 978-0-387-35409-5
Book sections
hal-01467243v1
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Framework for system design, validation and fast prototyping of multiprocessor SoCsArchitecture and Design of Distributed Embedded Systems Series: IFIP International Federation for Information Processing,, Kluwer Academic Publishers, 2001, Vol. 61
Book sections
hal-00016207v1
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Models for the control of the test and of the reconfiguration of a computerTrappl,-R.; Hanika,-F.; Pichler,-F.-R. Progress-in-cybernetics-and-systems-research,, Wiley, Chichester, UK, xv+683 p., pp.410-8, 1979, vol.V
Book sections
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Enabling 5G new services – Post-OFDM waveforms2016
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Flexible FBMC air interface for 5G2015
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FBMC-OQAM, a candidate waveform for 5G2015
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hal-01874482v1
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New candidate waveform for 5G2015
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hal-01873285v1
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Exploration et conception systématique d'architectures multiprocesseurs monopuces dédiées à des applications spécifiques = methods and tools for multiprocessor systems on chip, hardware/software co-designExploration and Systematic Design of Application-Specific Heterogeneous Multiprocessor SoCAutre [cs.OH]. Institut National Polytechnique de Grenoble - INPG, 2002. Français. ⟨NNT : ⟩
Theses
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