
Amer BAGHDADI
Présentation
Amer Baghdadi is a Professor at IMT Atlantique. He received his Engineering degree in 1998, Master of Science degree in the same year and PhD degree in 2002, all from Grenoble INP (Institut National Polytechnique), France. Furthermore, he received the accreditation to supervise research (HDR) in Sciences and Technologies of Information and Communication in 2012 from the University of Southern Brittany, France.
His general technical area concerns both theoretical and practical aspects, and both algorithm development for digital baseband components and corresponding hardware/software implementations and digital circuit design. His research activities target mainly digital communication applications, in addition to other application domains, and more particularly the design of flexible digital physical layer for future wireless communication standards and terminals. Prof. Baghdadi is IEEE Senior Member. He serves on the technical program committee for several international conferences. He co-authored more than 100 papers on scientific journals and proceedings of international conferences.
Publications
Publications
|
Enhancing Autonomous Space Exploration with Distributed Case-Based Reasoning and Learning (DCBRL) in Multi-Agent SystemsInternational Symposium on Artificial Intelligence, Robotics and Automation in Space (i-SAIRAS), Nov 2024, Brisbane, Australia
Communication dans un congrès
hal-04803823
v1
|
|
Novel transmission technique based on intentional overlapping to improve spectral efficiency of multicarrier systemsPIMRC 2023: IEEE 32nd Annual International Symposium on Personal, Indoor and Mobile Radio Communications, Sep 2023, Toronto, Canada. ⟨10.1109/PIMRC56721.2023.10293842⟩
Communication dans un congrès
hal-04168067
v1
|
|
Enhancing embedded AI-based object detection using multi-view approachRSP 2022: IEEE International Workshop on Rapid System Prototyping, part of Embedded Systems Week (ESWEEK), Oct 2022, Shanghai, China. ⟨10.1109/RSP57251.2022.10039026⟩
Communication dans un congrès
hal-03836472
v1
|
|
Low Latency Architecture Design for Decoding 5G NR Polar CodesDASIP 2022: Workshop on Design and Architectures for Signal and Image Processing, Jun 2022, Budapest, Hungary. pp.16-28, ⟨10.1007/978-3-031-12748-9_2⟩
Communication dans un congrès
hal-03707939
v1
|
|
Marine Object Detection Based on Top-View Scenes Using Deep Learning on Edge DevicesIC2SPM 2022: International Conference on Smart Systems and Power Management, Nov 2022, Beirut, Lebanon. pp.35-40, ⟨10.1109/IC2SPM56638.2022.9988928⟩
Communication dans un congrès
hal-04198386
v1
|
|
Overlap-Save FBMC receivers for massive MIMO systems under channel impairmentsVTC2022-Spring: IEEE 95th Vehicular Technology Conference, Jun 2022, helsinki, Finland. ⟨10.1109/VTC2022-Spring54318.2022.9860538⟩
Communication dans un congrès
hal-03608993
v2
|
|
Real-Time Human Detection in Marine Environment Using Deep Learning on Edge DevicesGDR SoC2: Groupe de recherche System on Chip – Systèmes embarqués et Objets Connectés, Colloque National, Jun 2022, Strasbourg, France
Communication dans un congrès
hal-03698760
v1
|
|
On the Latency and Complexity of Semi-Parallel Decoding Architectures for 5G NR Polar CodesISIVC 2022: 11th International Symposium on Signal, Image, Video and Communications, May 2022, El Jadida, Morocco. ⟨10.1109/ISIVC54825.2022.9800721⟩
Communication dans un congrès
hal-03608938
v1
|
|
Optimization of Deep-Learning Detection of Humans in Marine Environment on Edge DevicesICECS 2022: IEEE International Conference on Electronics Circuits and Systems, Oct 2022, Glasgow, United Kingdom. ⟨10.1109/ICECS202256217.2022.9970780⟩
Communication dans un congrès
hal-03789216
v1
|
|
Marine Objects Detection Using Deep Learning on Embedded Edge DevicesRSP 2022: IEEE International Workshop on Rapid System Prototyping, part of Embedded Systems Week (ESWEEK), Oct 2022, Shanghai (virtual), China. ⟨10.1109/RSP57251.2022.10039025⟩
Communication dans un congrès
hal-03836444
v1
|
|
Rapid design and verification experience using flexible cycle-accurate NoC simulatorIMCET 2021: IEEE 3rd International Multidisciplinary Conference on Engineering Technology, Dec 2020, Beirut, Lebanon. pp.77-83, ⟨10.1109/imcet53404.2021.9665518⟩
Communication dans un congrès
hal-03668066
v1
|
|
Low Complexity Non-binary Turbo Decoding based on the Local-SOVA AlgorithmISTC 2021: 11th International Symposium on Topics in Coding, Aug 2021, Montreal, Canada. ⟨10.1109/ISTC49272.2021.9594236⟩
Communication dans un congrès
hal-03279861
v1
|
|
Memristor Overwrite Logic (MOL) for In-Memory DNNISCAS 2020 : IEEE International Symposium on Circuits and Systems, Oct 2020, Seville, Spain. ⟨10.1109/ISCAS45731.2020.9180549⟩
Communication dans un congrès
hal-02513024
v1
|
MRL Crossbar-Based Full Adder Design2019 26th IEEE International Conference on Electronics, Circuits and Systems (ICECS), Nov 2019, Genoa, Italy. pp.674-677, ⟨10.1109/ICECS46596.2019.8964702⟩
Communication dans un congrès
hal-02502450
v1
|
|
Crossbar Memory Architecture Performing Memristor Overwrite Logic2019 26th IEEE International Conference on Electronics, Circuits and Systems (ICECS), Nov 2019, Genoa, Italy. pp.723-726, ⟨10.1109/ICECS46596.2019.8964910⟩
Communication dans un congrès
hal-02502460
v1
|
|
Rapid Prototyping of Parameterized Rotated and Cyclic Q Delayed Constellations DemapperRSP 2018 : International Symposium on Rapid System Prototyping, Oct 2018, Torino, Italy. pp.29-35, ⟨10.1109/RSP.2018.8631988⟩
Communication dans un congrès
hal-02276291
v1
|
|
A Block FBMC Receiver Designed For Short FiltersICC 2018 : IEEE International Conference on Communications, May 2018, Kansas City, United States. ⟨10.1109/ICC.2018.8422215⟩
Communication dans un congrès
hal-01814194
v1
|
|
NISC Design Experience of Flexible Architectures for Digital Communication ApplicationsICCA 2018 : International Conference on Computer and Applications, Aug 2018, Beirut, Lebanon. pp.123-129, ⟨10.1109/COMAPP.2018.8460355⟩
Communication dans un congrès
hal-02276298
v1
|
|
Hardware demonstration of post-OFDM waveformsEuCNC 2017: European Conference on Networks and Communications, Jun 2017, Oulu, Finland
Communication dans un congrès
hal-01614064
v1
|
|
Flexible hardware platform for demonstrating new 5G waveform candidatesICM 2017 : 29th IEEE International Conference on Microelectronics, Dec 2017, Beirut, Lebanon. ⟨10.1109/ICM.2017.8268851⟩
Communication dans un congrès
hal-01759087
v1
|
|
Proof-of-concept for post-OFDM waveforms as candidates for 5GSIPS 2017: IEEE International Workshop on Signal Processing Systems, Oct 2017, Lorient, France
Communication dans un congrès
hal-01759088
v1
|
|
Reduced Complexity FPGA Implementation for UF-OFDM Frequency Domain TransmitterSIPS 2017: IEEE Workshop on Signal Processing Systems, Oct 2017, Lorient, France. pp.1 - 6, ⟨10.1109/SiPS.2017.8110013⟩
Communication dans un congrès
hal-01656134
v1
|
|
Towards Memristor-based Reconfigurable FFT ArchitectureICM 2017 : 29th IEEE International Conference on Microelectronics, Dec 2017, Beirut, Lebanon. ⟨10.1109/ICM.2017.8268885⟩
Communication dans un congrès
hal-01761355
v1
|
|
NoC-MRAM Architecture for Memory-Based Computing: database-search case studyNEWCAS 2017 : 15th IEEE International New Circuits and Systems Conference, Jun 2017, Strasbourg, France. ⟨10.1109/NEWCAS.2017.8010167⟩
Communication dans un congrès
hal-01528137
v1
|
|
Flexible PoC for Post-OFDM waveformsG5-PPP 2016 : 2nd Global 5G Infrastructure public private partnership event, Nov 2016, Rome, Italy
Communication dans un congrès
hal-01444260
v1
|
|
CAASPER: Providing Accessible FPGA-acceleration over the NetworkRSP 2015 : 26th IEEE International Symposium on Rapid System Prototyping, Oct 2015, Amsterdam, Netherlands. pp.68 - 75, ⟨10.1109/RSP.2015.7416549⟩
Communication dans un congrès
hal-01292792
v1
|
|
|
Hardware Implementation of a Non-Coherent IR-UWB Receiver Synchronization Algorithm Targeting IEEE 802.15.6 Wireless BANICUWB 2014 : International Conference on Ultra-WideBand, Sep 2014, Paris, France. pp.444 - 449, ⟨10.1109/ICUWB.2014.6959023⟩
Communication dans un congrès
hal-01185867
v1
|
UWB-IR digital baseband architecture for IEEE 802.15.6 wireless BANICESS : 21st IEEE International Conference on Electronics, Circuits and Systems, Dec 2014, Marseille, France. pp.866 - 869, ⟨10.1109/ICECS.2014.7050123⟩
Communication dans un congrès
hal-01217830
v1
|
|
Design and prototyping flow of NISC-based flexible MIMO turbo-equalizerRSP 2014 : IEEE International Symposium on Rapid System Prototyping, Oct 2014, New Delhi, India. pp.16 - 21, ⟨10.1109/RSP.2014.6966687⟩
Communication dans un congrès
hal-01170238
v1
|
|
|
Implementation of NISC-based flexible architecture for MIMO MMSE-IC turbo-equalizationJNRDM 2014 : 17èmes Journées Nationales du Réseau Doctoral en Micro-Nanoélectronique,, May 2014, Lille, France
Communication dans un congrès
hal-01864517
v1
|
Hardware prototyping of FBMC/OQAM baseband for 5G mobile communication systemsRSP 2014 : IEEE International Symposium on Rapid System Prototyping, Oct 2014, New Delhi, India. pp.135 - 141, ⟨10.1109/RSP.2014.6966904⟩
Communication dans un congrès
hal-01170362
v1
|
|
FBMC/OQAM-related new waveformEuCNC 2015 : 24th European Conference on Networks and Communications, Jun 2014, Bologna, Italy
Communication dans un congrès
hal-01170370
v1
|
|
|
Energy-Efficient FPGA Implementation for Binomial Option Pricing Using OpenCLDATE 2014 : Design, Automation and Test in Europe, Mar 2014, Dresden, Germany
Communication dans un congrès
hal-00979390
v1
|
FBMC/OQAM baseband for 5G mobile communication systems: hardware design and on-board prototypingGDR ISIS workshop 2014: 5G & Beyond: Promises and Challenges, Oct 2014, Paris, France
Communication dans un congrès
hal-01170367
v1
|
|
Efficient synchronization technique for non-coherent IR-UWB receiver targeting IEEE 802.15.6 wireless BANBODYNETS 2013 : 8th International Conference on Body Area Networks, Sep 2013, Boston, United States. pp.181 - 184
Communication dans un congrès
hal-00933591
v1
|
|
|
An efficient on-chip configuration infrastructure for a flexible multi-ASIP turbo decoder architectureReCoSoC 2013 : 8th IEEE International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip, Jul 2013, Darmstadt, Germany. ⟨10.1109/ReCoSoC.2013.6581518⟩
Communication dans un congrès
hal-00873978
v1
|
Parameterized area-efficient multi-standard turbo decoderDATE 2013 : IEEE/ACM Design, Automation & Test in Europe Conference & Exhibition, Mar 2013, Grenoble, France. pp.109 - 114
Communication dans un congrès
hal-00876086
v1
|
|
|
Plateforme multi-ASIP reconfigurable dynamiquement pour le turbo décodage dans un contexte multi-standardGRETSI 2013 : 24ème colloque du Groupement de Recherche en Traitement du Signal et des Images, Sep 2013, Brest, France
Communication dans un congrès
hal-00876009
v1
|
Rapid Design and Prototyping of a Reconfigurable Decoder Architecture for QC-LDPC CodesRSP 2013 : 24th IEEE International Symposium on Rapid System Prototyping, Oct 2013, Montreal, Canada
Communication dans un congrès
hal-00876088
v1
|
|
Statically-scheduled application-specific processor design: A case-study on MMSE MIMO equalizationDATE 2013 : IEEE/ACM Design, Automation & Test in Europe Conference & Exhibition, Mar 2013, Grenoble, France. pp.677 - 680
Communication dans un congrès
hal-00876068
v1
|
|
|
A reconfigurable multi-standard ASIP-based turbo decoder for an efficient dynamic reconfiguration in a multi-ASIPISVLSI 2013 : IEEE Computer Society Annual Symposium on VLSI, Aug 2013, Natal, Brazil. ⟨10.1109/ISVLSI.2013.6654620⟩
Communication dans un congrès
hal-01002828
v1
|
A joint communication and application simulator for NoC-based custom SoCs: LDPC and turbo codes parallel decoding case studyDSD 2013 : 16th Euromicro Conference on Digital System Design, Sep 2013, Santander, Spain. pp.168 - 174
Communication dans un congrès
hal-00876080
v1
|
|
Quantization and fixed-point arithmetic for MIMO MMSE-IC linear turbo-equalizationICM 2013 : 25th IEEE International Conference on MicroelectronicsMicroelectronics, Dec 2013, Beirut, Lebanon. pp.1 - 4, ⟨10.1109/ICM.2013.6735008⟩
Communication dans un congrès
hal-01058011
v1
|
|
|
Optimizations for an efficient reconfiguration of an ASIP-based turbo decoderISCAS 2013 : IEEE International Symposium on Circuits and Systems, May 2013, Beijing, Chine. pp.493 - 496, ⟨10.1109/ISCAS.2013.6571888⟩
Communication dans un congrès
hal-00873979
v1
|
Flexible and efficient architecture design for MIMO MMSE-IC linear turbo-equalizationICCIT 2013 : 3rd IEEE International Conference on Communications and Information Technology, Jun 2013, Beirut, Lebanon. pp.340 - 344, ⟨10.1109/ICCITechnology.2013.6579576⟩
Communication dans un congrès
hal-00876051
v1
|
|
Designing a NISC-based flexible architecture for MIMO MMSE-IC turbo-equalizationJNRDM 2013 : 16èmes Journées Nationales du Réseau Doctoral en Micro-Nanoélectronique, Jun 2013, Grenoble, France
Communication dans un congrès
hal-00876045
v1
|
|
|
Stopping-free dynamic configuration of a multi-ASIP turbo decoderDSD 2013 : 16th Euromicro Conference on Digital System Design, Sep 2013, Santander, Spain. pp.155 - 162
Communication dans un congrès
hal-00876005
v1
|
|
Convergence and Complexity Analysis of Turbo Demodulation with Turbo DecodingColloque national du groupe de recherches System On Chip - System In Package (SOC-SIP), Jun 2012, Paris, France
Communication dans un congrès
hal-00725058
v1
|
|
Flexible Multi-ASIP SoC for Turbo/LDPC DecoderSOC-SIP : colloque national du groupe de recherches System On Chip - System In Package, Jun 2012, Paris, France
Communication dans un congrès
hal-00725184
v1
|
Architecture Efficiency of Application-Specific Processors: a 170Mbit/s 0.644mm2 Multi-standard Turbo DecoderSOC 2012 IEEE International Symposium on System-on-Chip, Oct 2012, Tampere, Finland
Communication dans un congrès
hal-00797562
v1
|
|
FPGA Prototyping and Performance Evaluation of Multi-standard Turbo/LDPC Encoding and DecodingRSP 2012: IEEE International Symposium on Rapid System Prototyping, Oct 2012, Tampere, Finland
Communication dans un congrès
hal-00797561
v1
|
|
Complexity reduction of shuffled parallel iterative demodulation with turbo decodingICT 2012: 19th International Conference on Telecommunications, Apr 2012, Jounieh, Lebanon. ⟨10.1109/ICTEL.2012.6221298⟩
Communication dans un congrès
hal-00725057
v1
|
|
Adaptive Complexity MIMO Turbo Receiver Applying Turbo DemodulationISTC 2012: 7th International Symposium on International Symposium onTurbo Codes and Iterative Information Processing, Aug 2012, Gothenburg, Sweden. pp.235 - 239
Communication dans un congrès
hal-00786473
v1
|
|
|
An analytical approach for sizing of heterogeneous multiprocessor flexible platform for iterative demapping and channel decodingInternational Conference on ReConFigurable Computing and FPGAs (Reconfig), Dec 2012, Cancun, Mexico. ⟨10.1109/ReConFig.2012.6416728⟩
Communication dans un congrès
hal-00747714
v1
|
Area and throughput optimized ASIP for multi-standard turbo decodingRSP 2011: 22nd IEEE International Symposium on Rapid System Prototyping, May 2011, Karlsruhe, Allemagne. pp.79 - 84, ⟨10.1109/RSP.2011.5929979⟩
Communication dans un congrès
hal-00725134
v1
|
|
A low complexity stopping criterion for reducing power consumption in turbo decodersDATE'11: IEEE/ACM Design, Automation and Test in Europe Conference & Exhibition, Mar 2011, Grenoble, France. pp.1530 - 1591
Communication dans un congrès
hal-00725610
v1
|
|
Reducing the number of iterations in iterative demodulation with turbo decodingSoftCOM : International Conference on Software, Telecommunications and Computer Networks, Sep 2011, Split, Croatia
Communication dans un congrès
hal-00725133
v1
|
|
A flexible high throughput multi-ASIP architecture for LDPC and turbo decodingDATE'11: IEEE/ACM Design, Automation and Test in Europe Conference & Exhibition, Mar 2011, Grenoble, France
Communication dans un congrès
hal-00632764
v1
|
|
|
Management of reconfigurable multi-standards ASIP-based receiverSOC-SIP : colloque national du groupe de recherches System On Chip - System In Package, Jun 2011, Lyon, France
Communication dans un congrès
hal-00724998
v1
|
FPGA Prototype of Flexible Heterogeneous multi-ASIP NoC-based Unified Turbo ReceiverDATE 2011: Demonstration at the University Booth of the Design, Automation and Test in Europe Conference & Exhibition, Mar 2011, Grenoble, France
Communication dans un congrès
hal-00797560
v1
|
|
TurbASIP power consumption analysis and optimizationColloque national du groupe de recherches System On Chip - System In Package (SOC-SIP), Jun 2010, Paris, France
Communication dans un congrès
hal-00632784
v1
|
|
Power consumption analysis and energy efficient optimization for turbo decoder implementationInternational Symposium on System-on-Chip, Sep 2010, Tampere, Finland. pp.12 - 17, ⟨10.1109/ISSOC.2010.5625565⟩
Communication dans un congrès
hal-00632782
v1
|
|
Iterative MIMO detection: flexibility and convergence analysis of soft-input soft-output list sphere decoding and linear MMSE detectionSoftCOM 2010 : International Conference on Software, Telecommunications and Computer Networks, Sep 2010, Split, Dubrovnik, Croatia. pp.175 - 179
Communication dans un congrès
hal-00876106
v1
|
|
DemASIP : universal demapper for multiwireless standardsColloque national du groupe de recherches "System On Chip - System In Package" (SOC-SIP), Jun 2010, Paris, France
Communication dans un congrès
hal-00632787
v1
|
|
Rapid design and prototyping of universal soft demapperISCAS : IEEE International Symposium on Circuits and Systems, May 2010, Paris, France
Communication dans un congrès
hal-00488694
v1
|
|
Exploring parallel processing levels in turbo demodulationInternational Symposium on Turbo Codes and Iterative Information Processing, Sep 2010, Brest, France. pp.359 - 363, ⟨10.1109/ISTC.2010.5613904⟩
Communication dans un congrès
hal-00632781
v1
|
|
|
High-level system modeling for rapid HW/SW architecture explorationIEEE/IFIP International Symposium on Rapid System Prototyping (RSP '09), Jun 2009, Paris, France. pp.88-94, ⟨10.1109/RSP.2009.27⟩
Communication dans un congrès
hal-02124754
v1
|
ASIP-based flexible MMSE-IC linear equalizer for MIMO turbo-equalization applicationsDATE09 : Design, Automation & Test in Europe Conference & Exhibition, Apr 2009, Nice, France
Communication dans un congrès
hal-00423920
v1
|
|
FPGA-based radar signal processing for automotive driver assistance systemRSP09 : IEEE/IFIP International Symposium on Rapid System Prototyping,, Jun 2009, Paris, France. pp.196-199, ⟨10.1109/RSP.2009.26⟩
Communication dans un congrès
hal-00424189
v1
|
|
Flexible architectures for LDPC decoders based on network on chip paradigmDSD 2009 : 12th Euromicro Conference on Digital System Design, Sep 2009, Patras, Greece
Communication dans un congrès
hal-00423917
v1
|
|
|
Shared resources high-level modeling in embedded systems using virtual nodesJoint IEEE North-East Workshop on Circuits and Systems and TAISA Conference 2009, Jun 2009, Toulouse, France. ⟨10.1109/NEWCAS.2009.5290506⟩
Communication dans un congrès
hal-00423997
v1
|
Rapid prototyping of ASIP-based flexible MMSE-IC linear equalizerRSP09 : IEEE International Symposium on Rapid System Prototyping, Jun 2009, Paris, France. pp.130-133, ⟨10.1109/RSP.2009.17⟩
Communication dans un congrès
hal-00424960
v1
|
|
FPGA prototypes for turbo communication applicationsUniversity Booth of DATE 09 : Design, Automation & Test in Europe Conference & Exhibition, Apr 2009, Nice, France
Communication dans un congrès
hal-01841144
v1
|
|
Binary de Bruijn on-chip network for a flexible multiprocessor LDPC decoderDAC 2008 : 45th ACM/IEEE design automation conference, Jun 2008, Anaheim, United States. pp.429 - 434, ⟨10.1109/DAC.2008.4555856⟩
Communication dans un congrès
hal-02194802
v1
|
|
|
Binary de Bruijn interconnection network for a flexible LDPC/turbo decoderIEEE International Symposium on Circuits and Systems (ISCAS 2008), May 2008, Seattle, WA, United States. pp.97-100, ⟨10.1109/ISCAS.2008.4541363⟩
Communication dans un congrès
hal-02194923
v1
|
Architectures des systèmes numériques de traitement : de l'électronique à l'informatique10èmes journées pédagogiques du CNFM (Coordination nationale de la formation en micro et nanoélectronique), Nov 2008, Saint Malo, France
Communication dans un congrès
hal-00424199
v1
|
|
On-chip communication network for flexible multiprocessor turbo decodingICTTA '08 : 3d International Conference on Information and Communication Technologies : From Theory to Applications, Apr 2008, Damas, Syria. pp.1 - 6
Communication dans un congrès
hal-02194798
v1
|
|
|
From application to ASIP-based FPGA prototype : a case study on turbo decodingRSP'2008 : the 19th IEEE/IFIP international symposium on rapid system prototyping, Jun 2008, Monterey, United States. pp.128 - 134, ⟨10.1109/RSP.2008.16⟩
Communication dans un congrès
hal-02194910
v1
|
Flexible and scalable on-chip communication network for multiprocessor turbo decodingPremier Colloque National du GDR SOC-SIP, Jun 2007, Paris, France
Communication dans un congrès
hal-02280094
v1
|
|
Butterfly and benes-based on-chip communication networks for multiprocessor turbo decodingDATEC 2007 : Design, Automation & Test in Europe Conference & Exhibition, Apr 2007, Nice, France. pp.654 - 659
Communication dans un congrès
hal-02194929
v1
|
|
Millimetre communication system for IVCITST 2007 : 7th International Conference on ITS (Intelligent Transport Systems), Jun 2007, Sophia-Antipolis, France. ⟨10.1109/ITST.2007.4295879⟩
Communication dans un congrès
hal-02136649
v1
|
|
Flexible Multi-ASIP SoC for High-Throughput Turbo DecodersPremier Colloque National du GDR SOC-SIP, Jun 2007, Paris, France
Communication dans un congrès
hal-02280092
v1
|
|
|
ASIP-based multiprocessor SoC design for simple and double binary turbo decodingDATE 06 : Design, Automation and Test in Europe, Mar 2006, Munich, Germany. pp.1 - 6, ⟨10.1109/DATE.2006.244126⟩
Communication dans un congrès
hal-02194947
v1
|
Exploring parallel processing levels for convolutional turbo decodingICCTA'06 : IEEE International Conference on Information and Communication Technologies : from theory to applications, April 24-28, Damas, Syria, Apr 2006, Damas, Syria. pp.2353 - 2358
Communication dans un congrès
hal-02279574
v1
|
|
|
Parallélisme et turbocodes convolutifsMajecSTIC 2006 : MAnifestation des JEunes Cherchercheurs STIC, Nov 2006, Lorient, France
Communication dans un congrès
hal-02280103
v1
|
On the parallelism of convolutional turbo decoding and interleaving interferenceGLOBECOM 2006 : 49th annual Global telecommunications conference, Nov 2006, San Francisco, United States. pp.1 - 5, ⟨10.1109/GLOCOM.2006.558⟩
Communication dans un congrès
hal-02194954
v1
|
|
On the Flexibility and Scalability of Multiprocessor Embedded System Design for Emerging In-Vehicle Applications5th International Conference on ITS Telecommunications, Jun 2005, Brest, France
Communication dans un congrès
hal-02137868
v1
|
|
An Efficient Architecture for the Implementation of Message Passing Programming Model on Massive Multiprocessor SoC15th IEEE International Workshop on Rapid System Prototyping, Jun 2004, Genève, Suisse
Communication dans un congrès
hal-02138091
v1
|
|
|
An efficient scalable and flexible data transfer architecture for multiprocessor SoC with massive distributed memorySan Diego, CA, 2004, San Diego, United States. pp.250-5, ⟨10.1145/996566.996636⟩
Communication dans un congrès
hal-00008046
v1
|
An efficient architecture for the implementation of message passing programming model on massive multiprocessorRSP 2004 : 15th IEEE International Workshop on Rapid System Prototyping, Jun 2004, Genève, Switzerland. pp.80-7
Communication dans un congrès
hal-00008037
v1
|
|
Embedded application prototyping on a communication-restricted reconfigurable platformIWRSP 2003 : 14th IEEE International Workshop on Rapid Systems Prototyping, Jun 2003, San Diego, United States. pp.33-9, ⟨10.1109/IWRSP.2003.1207027⟩
Communication dans un congrès
hal-00008052
v1
|
|
HW/SW interfaces design of a VDSL modem using automatic refinement of a virtual architecture specification into a multiprocessor SoC: a case studyDesign, Automation and Test in Europe (DATE'02), Mar 2002, Paris, France
Communication dans un congrès
hal-01380859
v1
|
|
Exploration et conception systématique d'architectures multiprocesseurs monopuces dédiées à des applications spécifiques3ème Colloque CAO de circuits et systèmes intégrés, May 2002, Paris, France
Communication dans un congrès
hal-01393248
v1
|
|
Component-based design approach for multicore SoCs2002 Design Automation Conference, Jun 2002, New Orleans, United States. pp.789-94, ⟨10.1109/DAC.2002.1012730⟩
Communication dans un congrès
hal-00008062
v1
|
|
A generic wrapper architecture for multi-processor SoC cosimulation and designCODES '01 : Ninth international symposium on Hardware/software codesign, 2001, Copenhague, Denmark. pp.195-200, ⟨10.1145/371636.371722⟩
Communication dans un congrès
hal-00008087
v1
|
|
Generic architecture platform for multiprocessor system-on-chip designDIPES 2000: Architecture and Design of Distributed Embedded Systems, Oct 2000, Schloß Eringerfeld, Germany. pp.53-63
Communication dans un congrès
hal-00008077
v1
|
|
Automatic generation of application-specific architectures for heterogeneous multiprocessor system-on-chipDAC '01 : 38th annual Design Automation Conference, 2001, Las Vegas, United States. pp.518-23, ⟨10.1145/378239.379015⟩
Communication dans un congrès
hal-00008074
v1
|
|
Application-specific multiprocessor systems-on-chipThe Tenth Workshop on Synthesis And System Integration of Mixed Technologies (SASIMI'01), Oct 2001, Nara, Japan
Communication dans un congrès
hal-01391627
v1
|
|
An efficient architecture model for systematic design of application-specific multiprocessor SoCDATE 2001 : Design, Automation and Test in Europe. Conference and Exhibition., Mar 2001, Munich, Germany. pp.55-62, ⟨10.1109/DATE.2001.915001⟩
Communication dans un congrès
hal-00008086
v1
|
|
Generic architecture platform for multiprocessor embedded system-on-chip designInternational Workshop on Distributed and Parallel Embedded Systems (DIPES'00), Oct 2000, Paderborn, Allemagne. pp.53-64
Communication dans un congrès
hal-01381242
v1
|
|
Design space exploration for hardware/software codesign of multiprocessor systemsRSP 2000 : 11th International Workshop on Rapid System Prototyping, Jun 2000, Paris, France. pp.8-13, ⟨10.1109/IWRSP.2000.854975⟩
Communication dans un congrès
hal-00008096
v1
|
|
Framework for system design, validation and fast prototyping of multiprocessor system-on-chip: applied to telecommunication systemsInternational Workshop on Distributed and Parallel Embedded Systems (DIPES'00), Jan 2000, Paderborn, Allemagne
Communication dans un congrès
hal-01384189
v1
|
|
Key Attack Strategies Against Black-Box DNNsGDR-SOC2, Jun 2022, Strasbourg, France. , GDR SOC2
Poster de conférence
hal-03690454
v1
|
Flexible FBMC air interface for 5GMWC 2015 : Mobile World Congress, Mar 2015, Barcelona, Spain. 2015
Poster de conférence
hal-01170210
v1
|
|
Application-Specific Processor Design: a Case-Study on MMSE MIMO equalizationGDR SoC-SiP 2013 : Colloque National du Groupe de Recherche System on Chip -System in Package, Jun 2013, Lyon, France. 2013
Poster de conférence
hal-00876041
v1
|
|
|
Efficient dynamic configuration of a multi-ASIP turbo decoderGDR SoC-SiP 2013 : Colloque National du Groupe de Recherche System on Chip -System in Package, Jun 2013, Lyon, France
Poster de conférence
hal-00876017
v1
|
Designing a NISC-based flexible architecture for MIMO MMSE-IC turbo-equalizationJNRDM 2013 : 16èmes Journées Nationales du Réseau Doctoral en Micro-Nanoélectronique, Jun 2013, Grenoble, France. 2013
Poster de conférence
hal-00876046
v1
|
|
ASIP Design for Multi-Standard Channel DecodersAdvanced Hardware Design for Error Correcting Codes, Springer, pp.151 - 175, 2014, 978-3-319-10568-0. ⟨10.1007/978-3-319-10569-7⟩
Chapitre d'ouvrage
hal-01170472
v1
|
ASIP design and prototyping for wireless communication applicationsAdvanced Applications of Rapid Prototyping Technology in Modern Engineering, InTech - Open Access Publisher, 2011
Chapitre d'ouvrage
hal-00699677
v1
|
|
Hardware/Software CodesignReis Ricardo, Lubaszewski Marcelo, Jess Jochen A.G. Design of Systems on Chip, Design and test, Springer, pp.133-158, 2007
Chapitre d'ouvrage
hal-00265185
v1
|
|
Hardware/Software Co-designDesign of Systems on a Chip : Design and Test, Springer, pp.133 - 158, 2007, 978-0-387-32499-9. ⟨10.1007/0-387-32500-X_7⟩
Chapitre d'ouvrage
istex
hal-02124753
v1
|
|
Framework for system design, validation and fast prototyping of multiprocessor SoCsArchitecture and Design of Distributed Embedded Systems Series: IFIP International Federation for Information Processing,, Kluwer Academic Publishers, 2001, Vol. 61
Chapitre d'ouvrage
hal-00016207
v1
|
|
Generic architecture platform for multiprocessor system-on-chip designArchitecture and Design of Distributed Embedded Systems, kluwer academic publishers, pp.53-63, 2001, 978-0-387-35409-5
Chapitre d'ouvrage
hal-01467243
v1
|
|
Models for the control of the test and of the reconfiguration of a computerTrappl,-R.; Hanika,-F.; Pichler,-F.-R. Progress-in-cybernetics-and-systems-research,, Wiley, Chichester, UK, xv+683 p., pp.410-8, 1979, vol.V
Chapitre d'ouvrage
hal-00016206
v1
|
Enabling 5G new services – Post-OFDM waveforms2016
Autre publication scientifique
hal-01874477
v1
|
|
New candidate waveform for 5G2015
Autre publication scientifique
hal-01873285
v1
|
|
Flexible FBMC air interface for 5G2015
Autre publication scientifique
hal-01873296
v1
|
|
FBMC-OQAM, a candidate waveform for 5G2015
Autre publication scientifique
hal-01874482
v1
|
|
Exploration et conception systématique d'architectures multiprocesseurs monopuces dédiées à des applications spécifiques = methods and tools for multiprocessor systems on chip, hardware/software co-designExploration and Systematic Design of Application-Specific Heterogeneous Multiprocessor SoCAutre [cs.OH]. Institut National Polytechnique de Grenoble - INPG, 2002. Français. ⟨NNT : ⟩
Thèse
tel-00002932
v1
|