Arief Wicaksana
12
Documents
Présentation
This page lists some publications of my research. My research interests are in Reconfigurable Platform, System-on-Chip and Embedded System.
Publications
Hardware Context Switch-based Cryptographic Accelerator for Handling Multiple StreamsACM Transactions on Reconfigurable Technology and Systems (TRETS), 2021
Article dans une revue
hal-03352889v1
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Hybrid Prototyping Methodology for Rapid System Validation in HW/SW Co-DesignThe Conference on Design and Architectures for Signal and Image Processing 2019 (DASIP 2019), Oct 2019, Montreal, Canada
Communication dans un congrès
cea-02494007v1
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Prototyping Dynamic Task Migration on Heterogeneous Reconfigurable Systems28th International Symposium on Rapid System Prototyping: Shortening the Path from Specification to Prototype (RSP 2017), Oct 2017, Seoul, North Korea. pp.16-22
Communication dans un congrès
hal-01744701v1
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Prototyping dynamic task migration on heterogeneous reconfigurable systemsInternational Symposium on Rapid System Prototyping: Shortening the Path from Specification to Prototype, Oct 2017, Seoul, South Korea
Communication dans un congrès
hal-01971312v1
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Demonstration of a context-switch method for heterogeneous reconfigurable systems2016 26th International Conference on Field Programmable Logic and Applications (FPL), Aug 2016, Lausanne, Switzerland. pp.1 - 1, ⟨10.1109/FPL.2016.7577384⟩
Communication dans un congrès
hal-01398560v1
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On-board non-regression test of HLS tools targeting FPGA2016 International Symposium On Rapid System Prototyping (RSP 2016), Oct 2016, Pittsburgh, PA, United States. pp.41-47, ⟨10.1145/2990299.2990307⟩
Communication dans un congrès
hal-01540944v1
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Automated Non-Regression Testing for Accelerator Prototyping on FPGAInternational symposium on Rapid System Prototyping (RSP'16), Oct 2016, Pittsbrugh, United States. pp.45-51
Communication dans un congrès
hal-01523887v1
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Validation automatique d’une méthode de migration des tâches sur la plateforme ZynqJournées Nationales du Réseau Doctoral en Micro-nanoélectronique (JNRD'16), May 2016, Toulouse, France
Communication dans un congrès
hal-01445859v1
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Fast and reconfigurable packet classification engine in FPGA-based firewall2011 International Conference on Electrical Engineering and Informatics (ICEEI), Jul 2011, Bandung, Indonesia. ⟨10.1109/ICEEI.2011.6021782⟩
Communication dans un congrès
hal-01398569v1
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Cohérence des communications lors de la migration de tâches matériellesISTE. Systèmes multiprocesseurs sur puce 1 - Architectures, ISTE - International Scientific and Technical Encyclopedia, pp.309-343, 2023, ⟨10.51926/ISTE.9021.ch11⟩
Chapitre d'ouvrage
hal-04131346v1
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Maintaining Communication Consistency during Task Migrations in Heterogeneous Reconfigurable DevicesMulti-Processor System-on-Chip 1: Architectures, wiley, chichester, uk, pp.255-285, 2021, 978-1-789-45021-7
Chapitre d'ouvrage
hal-03194391v1
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Portable infrastructure for heterogeneous reconfigurable devices in a cloud-FPGA environmentMicro and nanotechnologies/Microelectronics. Université Grenoble Alpes, 2018. English. ⟨NNT : 2018GREAT088⟩
Thèse
tel-02103303v1
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