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César Fuguet

18
Documents

Publications

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HPDcache: Open-source high-performance L1 data cache for RISC-V cores

César Fuguet
20th ACM International Conference on Computing Frontiers, May 2023, Bologne, Italy. pp.385, ⟨10.1145/3587135.3591413⟩
Communication dans un congrès cea-04110679v1

Accelerating Variants of the Conjugate Gradient with the Variable Precision Processor

Yves Durand , Eric Guthmuller , Cesar Fuguet , Jerome Fereyre , Andrea Bocco
2022 IEEE 29th Symposium on Computer Arithmetic (ARITH), Sep 2022, Lyon, France. pp.51-57, ⟨10.1109/ARITH54963.2022.00017⟩
Communication dans un congrès hal-04392747v1
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POPSTAR: a robust modular optical NoC architecture for chiplet-based 3D integrated systems

Yvain Thonnart , Stephane Bernabe , Jean Charbonnier , Christian Bernard , David Coriat
DATE 2020 - Design, Automation & Test in Europe Conference & Exhibition, Mar 2020, Grenoble, France. pp.1456-1461, ⟨10.23919/DATE48585.2020.9116214⟩
Communication dans un congrès cea-03471376v1

A 220GOPS 96-Core Processor with 6 Chiplets 3D-Stacked on an Active Interposer Offering 0.6ns/mm Latency, 3Tb/s/mm 2 Inter-Chiplet Interconnects and 156mW/mm 2 @ 82%-Peak-Efficiency DC-DC Converters

Pascal Vivet , Eric Guthmuller , Yvain Thonnart , Gaël Pillonnet , Guillaume Moritz
2020 IEEE International Solid- State Circuits Conference - (ISSCC), Feb 2020, San Francisco, United States. pp.46-48, ⟨10.1109/ISSCC19947.2020.9062927⟩
Communication dans un congrès hal-02985945v1

WAVES: Wavelength Selection for Power-Efficient 2.5D-Integrated Photonic NoCs

Aditya Narayan , Yvain Thonnart , Pascal Vivet , Cesar Fuguet Tortolero , Ayse Coskun
2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), Mar 2019, Florence, France. pp.516-521, ⟨10.23919/DATE.2019.8715036⟩
Communication dans un congrès hal-04392763v1

Active Interposer Technology for Chiplet-Based Advanced 3D System Architectures

Perceval Coudrain , P. Chausse , L. Arnaud , D. Lattard , E. Guthmuller
2019 IEEE 69th Electronic Components and Technology Conference (ECTC), May 2019, Las Vegas, France. pp.569-578, ⟨10.1109/ECTC.2019.00092⟩
Communication dans un congrès hal-04392754v1

A 29 Gops/Watt 3D-Ready 16-Core Computing Fabric with Scalable Cache Coherent Architecture Using Distributed L2 and Adaptive L3 Caches

E. Guthmuller , C. Fuguet , P. Vivet , C. Bernard , I. Miro-Panades
ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC), Sep 2018, Dresden, Germany. pp.318-321, ⟨10.1109/ESSCIRC.2018.8494275⟩
Communication dans un congrès hal-02985969v1

A Method for Fast Evaluation of Sharing Set Management Strategies in Cache Coherence Protocols

J. Dumas , E. Guthmuller , C. Fuguet Tortolero , Frédéric Pétrot
30th International Conference on Architecture of Computing Systems (ARCS 2017), Apr 2017, Vienna, Austria. pp.111-123
Communication dans un congrès hal-01523232v1

A Programmable Inbound Transfer Processor for Active Messages in Embedded Multicore Systems

Yves Durand , Christian Bernard , Romain Lemaire , Cesar Fuguet Tortolero , Emilie Garat
2017 Euromicro Conference on Digital System Design (DSD), Aug 2017, Vienna, France. pp.192-197, ⟨10.1109/DSD.2017.38⟩
Communication dans un congrès hal-04392776v1

Trace-driven exploration of sharing set management strategies for cache coherence in manycores

J. Dumas , E. Guthmuller , C. Fuguet Tortolero , Frédéric Pétrot
15th IEEE International New Circuits and Systems Conference (NEWCAS'17), Jun 2017, Strasbourg, France. pp.77-80
Communication dans un congrès hal-01701046v1
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Introduction of Fault-Tolerance Mechanisms for Permanent Failures in Coherent Shared-Memory Many-Core Architectures

César Fuguet Tortolero
Distributed, Parallel, and Cluster Computing [cs.DC]. Université Pierre et Marie Curie - Paris VI, 2015. English. ⟨NNT : 2015PA066462⟩
Thèse tel-01292995v1