Bruno FERRES
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Documents
Publications
Publications
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Modeling Techniques for the Formal Verification of Integrated Circuits at Transistor-Level: Performance vs. Precision Trade-offsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2025, ⟨10.1109/TCAD.2025.3608647⟩
Article dans une revue
hal-05290989
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A Survey on Transistor-Level Electrical Rule Checking of Integrated CircuitsACM Transactions on Design Automation of Electronic Systems, 2025, ⟨10.1145/3748327⟩
Article dans une revue
hal-05185119
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A Chisel Framework for Flexible Design Space Exploration through a Functional ApproachACM Transactions on Design Automation of Electronic Systems, 2023, 28 (4), pp.1-31. ⟨10.1145/3590769⟩
Article dans une revue
hal-04298227
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Electrical Rule Checking of Integrated Circuits using Satisfiability Modulo TheoryColloque du GDR SoC2, Jun 2023, Lyon, France
Poster de conférence
hal-04750092
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Chisel Usecase: Designing General Matrix Multiply for FPGAFernando Rincón, Jesús Barba, Hayden K. H. So, Pedro Diniz, Julián Caba. Applied Reconfigurable Computing. Architectures, Tools, and Applications (ARC 2020), Apr 2020, Toledo, Spain. Springer, Applied Reconfigurable Computing. Architectures, Tools, and Applications 16th International Symposium, ARC 2020, Toledo, Spain, April 1–3, 2020, Proceedings, pp.61-72, Lecture Notes in Computer Science. ⟨10.1007/978-3-030-44534-8_5⟩
Poster de conférence
hal-03082750
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Leveraging Hardware Construction Languages for Flexible Design Space Exploration on FPGAMicro and nanotechnologies/Microelectronics. Université Grenoble Alpes [2020-..], 2022. English. ⟨NNT : 2022GRALT025⟩
Thèse
tel-03709710
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