
Habib MEHREZ
164
Documents
Publications
Publications
The effect of interconnect depopulation on FPGA performances in terms of power, area and delayHPCS 2016 - International Conference on High Performance Computing & Simulation, Jul 2016, Innsbruck, Austria. pp.104--111, ⟨10.1109/HPCSim.2016.7568322⟩
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hal-01372560
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Inter-FPGA Routing Environment for Performance Exploration of Multi-FPGA SystemsRapid System Prototyping (RSP), Oct 2016, Pittsburgh, United States. pp.1-6
Communication dans un congrès
hal-01406803
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Using Timing-Driven Inter-FPGA Routing for Multi-FPGA Prototyping ExplorationEuromicro Conference on Digital System Design (DSD), Aug 2016, Limassol, Cyprus. pp.641-645, ⟨10.1109/DSD.2016.93⟩
Communication dans un congrès
hal-01406787
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Exploration of Mesh-Based FPGA Architecture: Comparison of 2D and 3D Technologies in Terms of Power, Area and PerformancePDP 2016 - 24th Euromicro International Conference on Parallel, Distributed, and Network-Based Processing, Feb 2016, Heraklion, Crete, Greece. pp.635--642, ⟨10.1109/PDP.2016.77⟩
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hal-01372557
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AEGIS-Based Efficient Solution for Secure Reconfiguration of FPGAsCryptography and Security in Computing Systems, Jan 2016, Prague, Czech Republic. pp.37-40, ⟨10.1145/2858930.2858937⟩
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hal-01259069
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Multiple FPGAs based prototyping and debugging with complete design flowIDT 2016 - 11th International Design & Test Symposium, Dec 2016, Hammamet, Tunisia. pp.171-176, ⟨10.1109/IDT.2016.7843035⟩
Communication dans un congrès
hal-01657908
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Mesh of Clusters FPGA Architectures: Exploration Methodology and Interconnect OptimizationARC 2015 - 11th International Symposium on Applied Reconfigurable Computing, Apr 2015, Bochum, Germany. pp.411-418, ⟨10.1007/978-3-319-16214-0_37⟩
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hal-01369176
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Exploration and optimization of heterogeneous interconnect fabric of 3D tree-based FPGADTIS 2014 - 9th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, May 2014, Santorini, Greece. pp.1--6, ⟨10.1109/DTIS.2014.6850673⟩
Communication dans un congrès
hal-01372619
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Improve defect tolerance in a cluster of a SRAM-based Mesh of Cluster FPGA using hardware redundancyFPL 2014 - 24th International Conference on Field Programmable Logic and Applications, Sep 2014, Munich, Germany. pp.1-4, ⟨10.1109/FPL.2014.6927389⟩
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hal-01162011
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Performance Comparison between Multi-FPGA Prototyping Platforms: Hardwired Off-the-Shelf, Cabling and CustomInternational Symposium on Field-Programmable Custom Computing Machines, May 2014, Boston, MA, United States. pp.125-132, ⟨10.1109/FCCM.2014.44⟩
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hal-01073939
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A reference-based specification tool for creating reliable library development specifications12th International New Circuits and Systems Conference, NEWCAS 2014, Jun 2014, Trois-Rivieres, QC, Canada. pp.133-136, ⟨10.1109/NEWCAS.2014.6934001⟩
Communication dans un congrès
hal-01217236
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A formalism of the specifications for library developmentIEEE International System-on-Chip Conference, Sep 2013, Erlangen, Germany. pp.307-312, ⟨10.1109/SOCC.2013.6749706⟩
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hal-00953500
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Low-power comb decimation filter for RF Sigma-Delta ADCsISCAS 2014 - IEEE International Symposium on Circuits and Systems, Jun 2014, Melbourne, Victoria, Australia. pp.1596--1599, ⟨10.1109/ISCAS.2014.6865455⟩
Communication dans un congrès
hal-01372612
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Flexible reconfigurable architecture for DSP applicationsSOCC 2014 - 27th IEEE International System-on-Chip Conference, Sep 2014, Las Vegas, NV, United States. pp.204--209, ⟨10.1109/SOCC.2014.6948927⟩
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hal-01372614
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Impact of Cluster Size on Routability, Testability and Robustness of a Cluster in a Mesh FPGAIEEE Computer Society Annual Symposium on VLSI (ISVLSI'14), Jul 2014, Tampa, FL, United States. pp.553-558, ⟨10.1109/ISVLSI.2014.66⟩
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hal-01400630
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Three-dimensional Mesh of Clusters: An alternative unified high performance interconnect architecture for 3D-FPGA implementation3DIC 2014 - 2014 International 3D Systems Integration Conference, Dec 2014, Kinsdale, Ireland. pp.1--7, ⟨10.1109/3DIC.2014.7152149⟩
Communication dans un congrès
hal-01372618
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On wiring delays reduction of tree-based FPGA using 3-D fabricSOCC 2014 - 27th IEEE International System-on-Chip Conference, Sep 2014, Las Vegas, NV, United States. pp.64--69, ⟨10.1109/SOCC.2014.6948901⟩
Communication dans un congrès
hal-01372615
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FPGA-Based High Performance AES-GCM Using Efficient Karatsuba Ofman Algorithm10th International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications, ARC 2014, Apr 2014, Vilamoura, Portugal. pp.13-24, ⟨10.1007/978-3-319-05960-0_2⟩
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hal-01219833
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Multi-FPGA Prototyping Board Issue : the FPGA I/O BottleneckInternational Conference on Embedded Computer Systems : Architectures, Modeling, and Simulation, Jul 2014, Agios Konstantinos, Greece. pp.207-214, ⟨10.1109/SAMOS.2014.6893213⟩
Communication dans un congrès
hal-01073937
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Power consumption analysis for mesh based FPGADTIS 2014 - 9th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, May 2014, Santorini, Greece. pp.1--5, ⟨10.1109/DTIS.2014.6850671⟩
Communication dans un congrès
hal-01372620
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Balancing WDDL dual-rail logic in a tree-based FPGA to enhance physical securityFPL 2014 - 24th International Conference on Field Programmable Logic and Applications, Sep 2014, Munich, Germany. pp.1--4, ⟨10.1109/FPL.2014.6927422⟩
Communication dans un congrès
hal-01372613
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Impact of defect tolerance techniques on the criticality of a SRAM-based Mesh of Cluster FPGAReConFig 2014 - International Conference on ReConFigurable Computing and FPGAs, Dec 2014, Cancun, Mexico. pp.1-6, ⟨10.1109/ReConFig.2014.7032508⟩
Communication dans un congrès
hal-01162066
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Future Inter-FPGA Communication Architecture for Multi-FPGA Based PrototypingACM/SIGDA International Symposium on Field-Programmable Gate Arrays, FPGA '14, Feb 2014, Monterey, CA, United States. pp.251-251, ⟨10.1145/2554688.2554747⟩
Communication dans un congrès
hal-00969240
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Data level parallelism for H264/AVC baseline intra-prediction chain on MPSoC2013 10th International Multi-Conference on Systems, Signals & Devices (SSD), Mar 2013, Hammamet, Tunisia. ⟨10.1109/SSD.2013.6564040⟩
Communication dans un congrès
hal-01797203
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A defect-tolerant area-efficient multiplexer for basic blocks in SRAM-based FPGAsEuropean Symposium on Reliability of Electron Devices, Failure Physics and Analysis (ESREF), Oct 2013, Arcachon, France. pp.1189-1193
Communication dans un congrès
hal-01062075
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Designing a 3D tree-based FPGA: Optimization of butterfly programmable interconnect topology using 3D technologyIEEE International 3D Systems Integration Conference (3DIC), 2013, Oct 2013, San Francisco, CA, United States. pp.1-8, ⟨10.1109/3DIC.2013.6702342⟩
Communication dans un congrès
hal-00944767
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Efficient State-Dependent Power Model for Multi-bit Flip-Flop BanksIEEE International Midwest Symposium on Circuits and Systems, Aug 2013, Columbus, United States. pp.461-464, ⟨10.1109/MWSCAS.2013.6674685⟩
Communication dans un congrès
hal-00913885
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Automatic Design Flow for Creating a Custom Multi-FPGA Board NetlistThe 9th International Symposium on Applied Reconfigurable Computing, ARC 2013, Mar 2013, Los Angeles, United States. pp.221, ⟨10.1007/978-3-642-36812-7_24⟩
Communication dans un congrès
istex
hal-00818279
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Partitioning constraints and signal routing approach for multi-FPGA prototyping platformISSoC 2013 - International Symposium on System on Chip, Oct 2013, Tampere, Finland. pp.1--4, ⟨10.1109/ISSoC.2013.6675273⟩
Communication dans un congrès
hal-01372830
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TSV count minimization and thermal analysis for 3D Tree-based FPGAICICDT 2013 - International Conference on IC Design & Technology, May 2013, Pavia, Italy. pp.223--226, ⟨10.1109/ICICDT.2013.6563341⟩
Communication dans un congrès
hal-01372828
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Efficient Multilevel Interconnect Topology for Cluster-based Mesh FPGA ArchitectureReConFig 2013 - International Conference on Reconfigurable Computing and FPGAs, Dec 2013, Cancun, Mexico. pp.1-6, ⟨10.1109/ReConFig.2013.6732282⟩
Communication dans un congrès
hal-00987368
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Exploration environment for 3D heterogeneous tree-based FPGA architectures (3D HT-FPGA)ReConFig 2013 - International Conference on Reconfigurable Computing and FPGAs, Dec 2013, Cancun, Mexico. pp.1--6, ⟨10.1109/ReConFig.2013.6732288⟩
Communication dans un congrès
hal-01372829
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Improved Method for Parallel AES-GCM Cores Using FPGAsReConFig 2013 - International Conference on Reconfigurable Computing and FPGAs, Dec 2013, Cancun, Mexico. pp.1-4, ⟨10.1109/ReConFig.2013.6732299⟩
Communication dans un congrès
hal-01160904
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Design and optimization of heterogeneous tree-based FPGA using 3D technologyFPT 2013 - International Conference on Field-Programmable Technology, Dec 2013, Kyoto, Japan. pp.334--337, ⟨10.1109/FPT.2013.6718380⟩
Communication dans un congrès
hal-01372833
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Formalisme de la spécification de la plateforme de conception pour le développement de la bibliothèqueJournees Nationales du Reseau Doctoral de Micro-electronique, 2013, Grenoble, France. pp.1-4
Communication dans un congrès
hal-01215668
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High Performance 3-Dimensional Heterogeneous Tree-based FPGA Architectures (HT-FPGA)FPGAworld'13 - The 10th FPGAworld Conference, Sep 2013, Stockholm, Sweden. pp.3:1-3:6, ⟨10.1145/2513683.2513686⟩
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hal-00873151
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High Speed Authenticated Encryption for Slow Changing Key Applications Using Reconfigurable DevicesWireless Days (WD), 2013 IFIP, Nov 2013, Valencia, Spain. pp.1 - 6, ⟨10.1109/WD.2013.6686460⟩
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hal-01017858
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A Defect-tolerant Cluster in a Mesh SRAM-based FPGAInternational Conference on Field-Programmable Technology (FPT), Dec 2013, Kyoto, Japan. pp.434-437, ⟨10.1109/FPT.2013.6718407⟩
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hal-00987365
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Iterative Routing Algorithm of Inter-FPGA Signals for Multi-FPGA Prototyping PlatformARC 2013 - 9th International Symposium on Reconfigurable Computing: Architectures, Tools and Applications, Mar 2013, Los Angeles, CA, United States. pp.210--217, ⟨10.1007/978-3-642-36812-7_20⟩
Communication dans un congrès
istex
hal-01372832
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Architecture Level TSV Count Minimization Methodology for 3D Tree-based FPGACool Chips XVI, Apr 2013, Yokohama, Japan. pp.1-3, ⟨10.1109/CoolChips.2013.6547925⟩
Communication dans un congrès
hal-00873268
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Designing 3D tree-based FPGA: Interconnect Optimization and Thermal AnalysisNEWCAS'13 - IEEE 11th International Conference on New Circuits and Systems, Jun 2013, Paris, France. pp.1-4, ⟨10.1109/NEWCAS.2013.6573575⟩
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hal-00873274
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Lightweight and Compact Solutions for Secure Reconfiguration of FPGAsInternational Conference on Reconfigurable Computing and FPGAs, Dec 2013, Cancun, Mexico. pp.1-4, ⟨10.1109/ReConFig.2013.6732304⟩
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hal-01216543
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Redundancy Method to assess Electromigration Lifetime in power grid designIEEE International Interconnect Technology Conference (IITC),, Jun 2013, Kyoto, Japan. pp.81-83, ⟨10.1109/IITC.2013.6615570⟩
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hal-00915971
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Physical Design Exploration of 3D Tree-based FPGA ArchitectureGLSVLSI'13 - The 23rd ACM international conference on Great lakes symposium on VLSI, May 2013, Paris, France. pp.335-336, ⟨10.1145/2483028.2483130⟩
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hal-00873292
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Protecting FPGA Bitstreams Using Authenticated Encryption11th IEEE International Conference of New Circuits and Systems (NEWCAS), Jun 2013, Paris, France. pp.1-4, ⟨10.1109/NEWCAS.2013.6573635⟩
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hal-01017823
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Routing algorithm for multi-FPGA based systems using multi-point physical tracksRSP 2013 - 24th IEEE International Symposium on Rapid System Prototyping, Oct 2013, Montreal, Canada. pp.2-8, ⟨10.1109/RSP.2013.6683951⟩
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hal-00934833
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Performance analysis and optimization of high density tree-based 3d multilevel FPGAReconfigurable Computing: Architectures, Tools and Applications, Mar 2013, Los Angeles, CA, United States. pp.197-209, ⟨10.1007/978-3-642-36812-7_19⟩
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hal-00872757
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Synthesis and Optimization of Quantum Boolean Circuit Using the Truth Table MethodInternational Workshop on Number Theory, Codes, Cryptography and Communication Systems (NTCCCS), Apr 2012, Oujda, Morocco. pp.192-197
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hal-01265626
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Générateur d'Architecture de FPGAColloque GDR SOC-SIP, Jun 2012, Paris, France. pp.1-3
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hal-00987369
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Design for prototyping of a parameterizable cluster-based Multi-Core System-on-Chip on a multi-FPGA boardRSP 2012 - 23rd IEEE International Symposium on Rapid System Prototyping, Oct 2012, Tampere, Finland. pp.71-77, ⟨10.1109/RSP.2012.6380693⟩
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hal-00818231
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A Logic Sharing Synthesis Tool for Mutually Exclusive ApplicationsDesign & Technology of Integrated Systems in Nanoscale Era (DTIS), 2012 7th International Conference on, May 2012, Gammarth, Tunisia. pp.1 - 6, ⟨10.1109/DTIS.2012.6232984⟩
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hal-00827442
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Efficient Parallel-Pipelined GHASH for Message AuthenticationInternational Conference on Reconfigurable Computing and FPGAs (ReConFig 2012), Dec 2012, Cancun, Mexico. pp.1 - 6, ⟨10.1109/ReConFig.2012.6416742⟩
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hal-01017807
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The Effect of S-box Design on Pipelined AES Using FPGAsColloque GDR SOC-SIP, Jun 2012, Paris, France. pp.1-4
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hal-01265624
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Multi-FPGA Prototyping Environment: Large Benchmark Generation and Signals Routing2014 International Conference on Reconfigurable computing and FPGA, Dec 2012, Cancun, Mexico. ⟨10.1109/ReConFig.2012.6416765⟩
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hal-01058039
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Differential pair routing to balance dual signals of WDDL designs in cluster-based Mesh FPGA6th International Workshop on Reconfigurable Communication-centric Systems-on-Chip, ReCoSoC 2011, Jun 2011, Montpellier, France. pp.1-4, ⟨10.1109/ReCoSoC.2011.5981528⟩
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hal-01286036
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Quantum circuits design and simulationThe First International Conference on "Research to Applications & Markets" (RAM 2011), Jun 2011, Monastir, Tunisia. pp.115-115
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hal-01265628
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Stratus: Free design of highly parametrized VLSI modules interoperable with commercial toolsISQED 2011 - 12th International Symposium on Quality Electronic Design, Mar 2011, Santa Clara, CA, United States. pp.502-507, ⟨10.1109/ISQED.2011.5770774⟩
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hal-01265627
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Comparison between Heterogeneous Mesh-Based and Tree-Based Application Specific FPGAThe 7th International Symposium on Applied Reconfigurable Computing, Mar 2011, Belfast, United Kingdom. pp.218-229, ⟨10.1007/978-3-642-19475-7_23⟩
Communication dans un congrès
istex
hal-01286069
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Exploring the Effect of LUT and Arity Size on a Tree-based Application Specific Inflexible FPGAInternational conference on Design & Technology of Integrated Systems (DTIS), Apr 2011, Athens, Greece. pp.1-6, ⟨10.1109/DTIS.2011.5941426⟩
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hal-01284605
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Application Specific FPGA Using Heterogeneous Logic BlocksARC International Symposium on Applied Reconfigurable Computing, Mar 2010, Bangkok, Thailand. pp.92-109, ⟨10.1007/978-3-642-12133-3_11⟩
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istex
hal-01290708
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Heterogeneous-ASIF: An Application Specific Inflexible FPGA using Heterogeneous logic blocksFPGA ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Feb 2010, Monterey, California, United States. pp.290-290, ⟨10.1145/1723112.1723181⟩
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hal-01290706
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Controlled placement and routing techniques to improve timing balance of WDDL designs in Mesh-based FPGAAPCCAS 2010 - IEEE Asia Pacific Conference on Circuits and Systems, Dec 2010, Kuala Lumpur, Malaysia. pp.296--299, ⟨10.1109/APCCAS.2010.5774878⟩
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hal-01372837
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A flexible realtime system for broadband time-frequency analysis in 130 NM CMOSICECS 2010 - 17th IEEE International Conference on Electronics, Circuits and Systems, Dec 2010, Athens, Greece. pp.251--254, ⟨10.1109/ICECS.2010.5724501⟩
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hal-01372835
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On the optimization of FPGA area depending on target applicationsAPCCAS 2010 - IEEE Asia Pacific Conference on Circuits and Systems, Dec 2010, Kuala Lumpur, Malaysia. pp.308--311, ⟨10.1109/APCCAS.2010.5774849⟩
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hal-01372836
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A New Datapath-Oriented Tree-based FPGA ArchitectureIEEE International Conference on Microelectronics (ICM), Dec 2010, Cairo, Egypt. pp.403-406, ⟨10.1109/ICM.2010.5696172⟩
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hal-01292069
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Modélisation et simplification de circuits quantiquesMateriaux 2010, Nov 2010, Mahdia, Tunisia. pp.2-2
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hal-01265629
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Design and FPGA Implementation of Modular Multiplication Methods Using Cellular AutomataDTIS IEEE International Conference on Design & Test of Integrated Systems in Nanoscale Technology, Mar 2010, Hammamet, Tunisia. pp.1-5, ⟨10.1109/DTIS.2010.5487586⟩
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hal-01265630
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Routability driven placement for mesh-based FPGA architectureIDT 2010 - 5th International Design and Test Workshop, Dec 2010, Abu Dhabi, United Arab Emirates. pp.85--90, ⟨10.1109/IDT.2010.5724414⟩
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hal-01372834
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Improving the Security of Dual Rail Logic in FPGA Using Controlled Placement and RoutingReConFig International Conference on Reconfigurable Computing and FPGAs 2009, Dec 2009, Cancun, Mexico. pp.201-206, ⟨10.1109/ReConFig.2009.44⟩
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hal-01295098
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ASIF: Application Specific Inflexible FPGAICFPT International Conference on Field-Programmable Technology, Dec 2009, Sydney, Australia. pp.112-119, ⟨10.1109/FPT.2009.5377657⟩
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hal-01295122
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A New Tree-based coarse-grained FPGA ArchitectureIEEE International Conference on PhD. Research in MicroElectronics, PRIME'09, Jul 2009, Cork, Ireland. pp.48-51, ⟨10.1109/RME.2009.5201347⟩
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hal-01298010
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Placement and Routing Techniques to Improve Delay Balance of WDDL Netlist in MFPGAIEEE International Conference on Electronics, Circuits, and Systems - ICECS 2009, Dec 2009, Hammamet, Tunisia. pp.791-794, ⟨10.1109/ICECS.2009.5410774⟩
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hal-01294427
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Comparison of Tree-Based and Mesh-Based Coarse-Grained FPGA ArchitecturesICM International Conference on Microelectronics, Dec 2009, Marrakech, Morocco. pp.248-251, ⟨10.1109/ICM.2009.5418640⟩
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hal-01295097
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Generic Techniques and CAD tools for automated generation of FPGA LayoutPRIME IEEE Conference on Ph.D. Research in MicroElectronics and Electronics, Jun 2008, Istanbul, Turkey. pp.141-144, ⟨10.1109/RME.2008.4595745⟩
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hal-01301526
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Efficient Tree Topology for FPGA Interconnect NetworkGLSVLSI ACM Great Lakes Symposium on VLSI, May 2008, Orlando, Florida, United States. pp.321-326, ⟨10.1145/1366110.1366186⟩
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hal-01301523
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Automatic Allocation of Redundant Operators in Arithmetic Data path OptimizationDASIP IEEE International Conference on Design and Architectures for Signal and Image Processing, Nov 2008, Bruxelles, Belgium. pp.176-183
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hal-01265631
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Arithmetic Data path Optimization using Borrow-Save RepresentationISVLSI IEEE Computer Society Annual Symposium on Emerging VLSI, Apr 2008, Montpellier, France. pp.4-9, ⟨10.1109/ISVLSI.2008.29⟩
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hal-01265632
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Enhanced Methodology and Tools for Exploring Domain-Specific Coarse-grained FPGAsReConFig International Conference on Reconfigurable Computing and FPGAs, Dec 2008, Cancun, Mexico. pp.121-126, ⟨10.1109/ReConFig.2008.53⟩
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hal-01301529
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Automatic Layout Generator of Domain Specific FPGA:ICM International Conference on Microelectronics, Dec 2008, Sharjah, United Arab Emirates. pp.183-186, ⟨10.1109/ICM.2008.5393493⟩
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hal-01299216
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The Effect of LUT and Cluster Size on a Tree based FPGA ArchitectureReConFig International Conference on Reconfigurable Computing and FPGAs, Dec 2008, Cancun, Mexico. pp.115-120, ⟨10.1109/ReConFig.2008.28⟩
Communication dans un congrès
hal-01299218
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A New Coarse-grained FPGA Architecture Exploration EnvironmentICFPT International Conference on Field-Programmable Technology, Dec 2008, Taipei, Taiwan. pp.285-288, ⟨10.1109/FPT.2008.4762399⟩
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hal-01301527
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Data Path Optimization using Redundant Arithmetic and Pattern MatchingWorkshop on Design and Architectures for Signal and Image Processing (DASIP'2007), Nov 2007, Grenoble, France. pp.281-288
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hal-01265633
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A Cascadable ASIC Prototype for Real Time Time-Frequency AnalysisMWSCAS Midwest Symposium on Circuits and Systems, Aug 2007, Montreal, Canada. pp.690-693, ⟨10.1109/MWSCAS.2007.4488673⟩
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hal-01311484
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A Routability Driven Partitioning and Detailed Placement Approach for Multilevel Hierarchical FPGAFPGA ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Feb 2007, Monterey, Californie, United States. pp.225-225
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hal-01311525
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Efficient Mesh of Tree Interconnect for FPGA ArchitectureICFPT International Conference on Field-Programmable Technology, Dec 2007, Kitakyushu, Japan. pp.269-272, ⟨10.1109/FPT.2007.4439263⟩
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hal-01305972
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Mesh of Tree: Unifying Mesh and MFPGA for Better Device PerformancesNoC ACM/IEEE International Symposium on Networks-on-Chip, May 2007, Princeton, United States. pp.243-252, ⟨10.1109/NOCS.2007.27⟩
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hal-01305788
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Stratus: A procedural circuit description language based upon PythonICM International Conference on Microelectronics, Dec 2007, Cairo, Egypt. pp.275-278, ⟨10.1109/ICM.2007.4497707⟩
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hal-01305970
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A Generic ASIC Architecture for Real Time Time-Frequency Analysis of Non-stationary Large Bandwidth SignalsIMTC IEEE Instrumentation and Measurement Technology Conference, May 2007, Warsaw, Poland. pp.1-5, ⟨10.1109/IMTC.2007.379468⟩
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hal-01311481
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A new Multilevel Hierarchical MFPGA and its suitable configuration toolsISVLSI IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures, Mar 2006, Karlsruhe, Germany. pp.263-268, ⟨10.1109/ISVLSI.2006.6⟩
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hal-01338233
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Evaluation of Hierarchical FPGA partitioning methodologies based on architecture Rent ParameterPRIME IEEE Conference on Ph.D. Research in MicroElectronics and Electronics, Jun 2006, Otranto, Italy. pp.85-88, ⟨10.1109/RME.2006.1689902⟩
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Stratus : Un environnement de développement de circuitsJP CNFM Journées pédagogiques du CNFM, 2006, Saint-Malo, France. pp.57-61
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Configuration tools for a new multilevel hierarchical FPGAFPGA ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Feb 2006, Monterey, California, United States. pp.229-229, ⟨10.1145/1117201.1117248⟩
Communication dans un congrès
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Implementation of Scalable Embedded FPGA for SOCDTIS IEEE International Conference on Design & Test of Integrated Systems in Nanoscale Technology, Sep 2006, Tunis, Tunisia. pp.74-77, ⟨10.1109/DTIS.2006.1708687⟩
Communication dans un congrès
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Performances Improvement of FPGA using Novel Multilevel Hierarchical Interconnection StructureICCAD IEEE/ACM International Conference on Computer-Aided Design, Nov 2006, San Jose, California, United States. pp.675-679, ⟨10.1109/ICCAD.2006.320012⟩
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A multilevel hierarchical interconnection structure for FPGAFPGA ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Feb 2006, Monterey, California, United States. pp.225-225, ⟨10.1145/1117201.1117239⟩
Communication dans un congrès
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Performance Improvement of FPGA Using Novel Multilevel Hierarchical Interconnection StructureReCoSoC 2006 - 2nd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, Jul 2006, Montpellier, France. pp.117--123
Communication dans un congrès
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Performances comparison between Multilevel hierarchical and Mesh FPGADTIS IEEE International Conference on Design & Test of Integrated Systems in Nanoscale Technology, Sep 2006, Tunis, Tunisia. pp.166-171, ⟨10.1109/DTIS.2006.1708712⟩
Communication dans un congrès
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A High Level SoC Energy Analysis Method with Good Accuracy Using Cycle Accurate SimulationIEEE Symposium on low power and high-speed chips (COOL Chips VIII), Apr 2005, Yokohama, Japan. pp.195
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Energy estimation and optimization in architectural descriptions of complex embedded systemsMicrotechnologies for the New Millennium 2005 : VLSI Circuits and Systems, May 2005, Sevilla, Spain. pp.456-466, ⟨10.1117/12.608256⟩
Communication dans un congrès
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Implementation of Scalable Embedded FPGA for SOCReCoSoC 2005 - 1st International Workshop on Reconfigurable Communication-centric Systems-on-Chip, Jun 2005, Montpellier, France. pp.74-77
Communication dans un congrès
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Hierarchical FPGA clustering to improve routabilityPRIME 2005 - IEEE Conference on Ph.D. Research in MicroElectronics and Electronics, Jul 2005, Lausanne, Switzerland. pp.165-168, ⟨10.1109/RME.2005.1543029⟩
Communication dans un congrès
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Energy Estimation and Optimisation of Embedded Systems using Cycle Accurate SimulationFTFC 2005 - 5èmes Journées d'études Faible Tension Faible Consommation, May 2005, Paris, France. pp.29-32
Communication dans un congrès
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Hierarchical FPGA clustering based on multilevel partitioning approach to improve routability and reduce power dissipationReConFig 2005 - International Conference on Reconfigurable Computing and FPGAs, Sep 2005, Puebla City, Mexico. pp.21-25, ⟨10.1109/RECONFIG.2005.23⟩
Communication dans un congrès
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Optimisation de chemins de données par l'utilisation de l'arithmétique redondanteJNRDM 2005 - 8èmes Journées Nationales du Réseau Doctoral en Microélectronique, May 2005, Paris, France. pp.268-270
Communication dans un congrès
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Automatic Layout of Scalable Embedded Field Programmable Gate ArrayICEEC 2004 - International Conference on Electrical Electronic and Computer Engineering, Sep 2004, Cairo, Egypt. pp.469-472, ⟨10.1109/ICEEC.2004.1374502⟩
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Use of multiple numeration systems for architecture and design of a high performance FIR filter netlist generatorICM 2004 - 16th International Conference on Microelectronics, Dec 2004, Tunis, Tunisia. pp.547-550, ⟨10.1109/ICM.2004.1434721⟩
Communication dans un congrès
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Générateur de netlist de filtres numériques RIF optimisésJNRDM 2004 - 7èmes Journées Nationales du Réseau Doctoral en Microélectronique, May 2004, Marseille, France. pp.451-453
Communication dans un congrès
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Hardware implementation of discrete stochastic arithmetic6th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS'03), 2003, Poznan, Poland. pp.57-64
Communication dans un congrès
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Hardware implementation of a method to control round-off errors6th WSEAS International Multiconference on Circuits Systems Communications and Computers (CSCC'2002), Jul 2002, Rethymnon, Greece. pp.157-162
Communication dans un congrès
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A Floating-Point Unit using stochastic arithmetic compliant with the IEEE-754 standard9th IEEE International Conference on Electronics Circuits and Systems (ICECS'2002), Sep 2002, Dubrovnik, Croatia. pp.603-606, ⟨10.1109/ICECS.2002.1046241⟩
Communication dans un congrès
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Implantation matérielle d'une méthode de contrôle des erreurs d'arrondi de calculTroisième colloque du GDR CAO de circuits et systèmes intégrés, 2002, Paris, France. pp.63-66
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Energy Estimations in High Level Cycle-Accurate Descriptions of Embedded SystemsThe 5th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS'2002), Apr 2002, Brno, Czech Republic. pp.228-235
Communication dans un congrès
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Hardware implementation of the CESTAC method10th GAMM - IMACS International Symposium on Scientific Computing Computer Arithmetic and Validated Numerics (SCAN'2002), Sep 2002, Paris, France. pp.162-162
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hal-01265638
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Une unité de calcul flottant utilisant l'arithmétique stochastiqueVèmes Journées Nationales du Réseau Doctoral de Micro-électronique (JNRDM'2002), 2002, Grenoble, France. pp.217-218
Communication dans un congrès
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A fast and low-power distance computation unit dedicated to neural networks, based on redundant arithmeticIEEE International Symposium on Circuits and Systems (ISCAS'2001), May 2001, Sydney, Australia. pp.878-881, ⟨10.1109/ISCAS.2001.922378⟩
Communication dans un congrès
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A family of redundant multipliers dedicated to fast computation for signal processingIEEE International Symposium on Circuits and Systems (ISCAS 2000), May 2000, Geneva, Switzerland. pp.325-328, ⟨10.1109/ISCAS.2000.857430⟩
Communication dans un congrès
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Low-power Comb Decimation Filter Using Polyphase Decomposition For Mono-bit Sigma-Delta Analog-to-Digital ConvertersInternational Conference On Signal Processing Applications and Technologies (ICSPAT 2000), Oct 2000, Dallas, Texas, United States. pp.432-435
Communication dans un congrès
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A System-On-A-Chip for Pattern Recognition Architecture and Design MethodologyCAMP 2000 - Fifth International Workshop on Computer Architectures for Machine Perception, Sep 2000, Padova, Italy. pp.155--162, ⟨10.1109/CAMP.2000.875973⟩
Communication dans un congrès
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GSM EFR Vocoder on a Configurable DSP Core, A Quantitative AnalysisInternational Conference On Signal Processing Applications and Technologies (ICSPAT 2000), Oct 2000, Dallas, Texas, United States. pp.1-6
Communication dans un congrès
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Use of Redundant Arithmetic on Architecture and Design of a High Performance DCT Macro-bloc Generator15th Design of Circuits and Integrated Systems Conference (DCIS), 2000, Montpellier, France. pp.428-433
Communication dans un congrès
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Efficient Polyphase Decomposition of Comb Decimation Filters in Sigma-Delta Analog-to-Digital Converters43rd IEEE Midwest Symposium on Circuits and Systems (MWSCAS 2000), Aug 2000, Lansing, MI, United States. pp.432-435, ⟨10.1109/MWSCAS.2000.951676⟩
Communication dans un congrès
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A Macro-Block Based Methodology for ASIP Core DesignInternational Conference On Signal Processing Applications and Technologies (ICSPAT'99), 1999, Orlando, FL, United States. pp.302-305
Communication dans un congrès
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Algorithms and VLSI Architectures for Pattern Recognition Based on the Gabor WaveletsInternational Conference on Signal Processing Applications and Technology (ICSPAT'98), Sep 1998, Toronto, Canada. pp.1455-1459
Communication dans un congrès
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Architecture and design Methodology of the RBF-DDA Neural NetworkIEEE International Symposium on Circuits and Systems (ISCAS'98), May 1998, Monterey, CA, United States. pp.199-202, ⟨10.1109/ISCAS.1998.703974⟩
Communication dans un congrès
hal-01618369
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System Level Design of a Pattern Recognition System Based on the Gabor WaveletsIEEE-SP Conference on Time-Frequency Time-Scale Analysis (TFTS'98), Oct 1998, Pittsburgh, PA, United States. pp.237-240, ⟨10.1109/TFSA.1998.721405⟩
Communication dans un congrès
hal-01618062
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Teaching the design of a chip under the Cadence Opus environment using the Alliance cell librariesMSE '97 - IEEE International Conference on Microelectronic Systems Education, Jul 1997, Arlington, VA, United States. pp.81--82, ⟨10.1109/MSE.1997.612556⟩
Communication dans un congrès
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Automatic Generation Of Self Testing ROM4th Mixed Design of Integrated Circuits and Systems (MIXDES'1997), Jun 1997, Poznan, Poland. pp.1-5
Communication dans un congrès
hal-01627800
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Modelling and synthesis of optimal adders under left-to-right input arrivalIFIP International Workshop on Logic and Architecture Synthesis (IWLAS'97), Dec 1997, Grenoble, France
Communication dans un congrès
hal-01398573
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A Hardware Implementation of an RBF Neural Network : Architecture and Design MethodologyInternational Conference on Signal Processing and Technology 97, Sep 1997, San Diego, CA, United States. pp.199 - 202
Communication dans un congrès
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A time driven adder generator architecture9th IFIP International Conference on Very Large Scale Integration (VLSI'97), Aug 1997, Gramado, RS, Brazil. pp.453-463, ⟨10.1007/978-0-387-35311-1_37⟩
Communication dans un congrès
hal-01396484
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Towards high performance GHASH for pipelined AES-GCM using FPGAsACM/SIGDA International Symposium on Field-Programmable Gate Arrays, FPGA '14, Feb 2014, Monterey, CA, United States. ACM, pp.242-242, 2014, ⟨10.1145/2554688.2554709⟩
Poster de conférence
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Three-Dimensional Design Methodologies for Tree-based FPGA ArchitectureSpringer, 350, 2015, Lecture Notes in Electrical Engineering, 978-3-319-19173-7. ⟨10.1007/978-3-319-19174-4⟩
Ouvrages
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Tree Based Heterogeneous FPGA Architectures, Application Specific Exploration and OptimizationSpringer, 2012, 978-1-4614-3593-8. ⟨10.1007/978-1-4614-3594-5⟩
Ouvrages
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Application-Specific Mesh-based Heterogeneous FPGA ArchitecturesSpringer, 202, 2011, 978-1-4419-7927-8. ⟨10.1007/978-1-4419-7928-5⟩
Ouvrages
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Les systèmes de traitement numérique du signal[Rapport de recherche] lip6.2001.021, LIP6. 2001
Rapport
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