Katell Morin-Allory

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Publications

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A Survey on Automatic Assertion Miners

Mohammad Reza Heidari Iman , Giorgio Di Natale , Katell Morin-Allory
IEEE 28th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2025), May 2025, Lyon, France. ⟨10.1109/DDECS63720.2025.11006673⟩
Communication dans un congrès hal-05085439 v1
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WIP: Building an Education Ecosystem for Next Generation Microelectronics Experts in Green and Circular Economy with Digitally-Supported Teaching Methods for Sustainable Chips and Applications (EU Project GreenChips-EDU)

Klaus Hofmann , Ferdinand Keil , David Riehl , Alicja Michalowska-Forsyth , Nikolaus Czepl et al.
2024 IEEE Frontiers in Education Conference (FIE), Oct 2024, Washington, France. pp.1-5, ⟨10.1109/FIE61694.2024.10893342⟩
Communication dans un congrès hal-04974462 v1

Formal Resilience Metric Characterization in Complex Digital Systems

Damiano Zuccalà , Jean-Marc Daveau , Philippe Roche , Katell Morin-Allory
2024 IEEE European Test Symposium (ETS), May 2024, The Hague, France. pp.1-4, ⟨10.1109/ETS61313.2024.10567525⟩
Communication dans un congrès hal-04861327 v1

Formal Fault Injection in Digital Blocks with Mined Assertions

Damiano Zuccalá , Paul Breuil , Jean-Marc Daveau , Philippe Roche , Katell Morin-Allory
2024 22nd ACM-IEEE International Symposium on Formal Methods and Models for System Design (MEMOCODE), ACM IEEE, Oct 2024, Raleigh, United States. pp.77-86, ⟨10.1109/MEMOCODE63347.2024.00014⟩
Communication dans un congrès hal-04861324 v1

A Generic CDC Modeling for Data Stability Verification

Diana Kalel , Jean-Christophe Brignone , Laurent Fesquet , Katell Morin-Allory
IEEE 30th International Conference on Electronics, Circuits and Systems (ICECS 2023), Dec 2023, Istanbul, Turkey
Communication dans un congrès hal-04331999 v1

Formal Temporal Characterization of Register Vulnerability in Digital Circuits

Damiano Zuccalà , Jean-Marc Daveau , Philippe Roche , Katell Morin-Allory
2023 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Jun 2023, Foz do Iguacu, Brazil. pp.1-6, ⟨10.1109/ISVLSI59464.2023.10238514⟩
Communication dans un congrès hal-04861320 v1

Data-driven Pruning for Bundled-data Circuits

Cristiano Merio , Xavier Lesage , Ali Naimi , Sylvain Engels , Katell Morin-Allory et al.
28th International Symposium on Asynchronous Circuits and Systems (ASYNC 2023, Jul 2023, Beijing, China
Communication dans un congrès hal-04331929 v1

Method for Data-Driven Pruning in Micropipeline Circuits

Cristiano Merio , Xavier Lesage , Ali Naimi , Sylvain Engels , Katell Morin-Allory et al.
31st IFIP/IEEE Conference on Very Large Scale Integration (VLSI-SoC 2023), Oct 2023, Sharjah, United Arab Emirates
Communication dans un congrès hal-04331953 v1

Cross-layer Approach to Assess FMEA on Critical Systems and Evaluate High-Level Model Realism

Julie Roux , Katell Morin-Allory , Vincent Beroulle , Régis Leveugle , Gilles Genévrier et al.
29th IFIP/IEEE International Conference on very Large Scale Integration, VLSI-SoC 2021, Oct 2021, Singapour, Singapore. ⟨10.1109/VLSI-SoC53125.2021.9607001⟩
Communication dans un congrès hal-03353865 v1
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A High-Level Design Flow for Locally Body-Biased Asynchronous Circuits

Yoan Decoudu , Katell Morin-Allory , Laurent Fesquet
29th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC 2021), Oct 2021, Singapore, Singapore. ⟨10.1109/VLSI-SoC53125.2021.9606977⟩
Communication dans un congrès hal-03662244 v1

FPU Reduced Variable Precision in Time: Application to the Jacobi Iterative Method

N. Ait Said , Mounir Benabdenbi , Katell Morin-Allory
IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2021), Jul 2021, Tampa (FL), United States. ⟨10.1109/ISVLSI51109.2021.00040⟩
Communication dans un congrès hal-03332203 v1

FPU Bit-Width Optimization for Approximate Computing: A Non-Intrusive Approach

N. Ait Said , Mounir Benabdenbi , Katell Morin-Allory
15th Design & Technology of Integrated Systems in Nanoscale Era (DTIS 2020), Apr 2020, Marrakech, Morocco. ⟨10.1109/DTIS48698.2020.9080931⟩
Communication dans un congrès hal-03331714 v1

Cross Layer Fault Simulations for Analyzing the Robustness of RTL Designs in Airborne Systems

Julie Roux , Vincent Beroulle , Katell Morin-Allory , Régis Leveugle , Lilian Bossuet et al.
23rd International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), Apr 2020, Novi Sad, Serbia. pp.1-4, ⟨10.1109/DDECS50862.2020.9095559⟩
Communication dans un congrès hal-02937868 v1

From High-Level Synthesis to Bundled-Data Circuits

Yoan Decoudu , Jean Simatic , Katell Morin-Allory , Laurent Fesquet
International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS 2020), Jul 2020, Samos, Greece
Communication dans un congrès hal-02956234 v1

High Level Fault Injection Method for Evaluating Critical System Parameter Ranges

Julie Roux , Vincent Beroulle , Katell Morin-Allory , Régis Leveugle , Lilian Bossuet et al.
2020 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS), Nov 2020, Glasgow, United Kingdom. pp.1-4, ⟨10.1109/ICECS49266.2020.9294821⟩
Communication dans un congrès hal-03136621 v1

Body-Bias Micro-Generators for Activity-Driven Power Management

Laurent Fesquet , Yoan Decoudu , Rodrigo Iga Jadue , Thiago Ferreira de Paiva Leite , O. Rolloff et al.
FDSOI workshop at DATE Conference 2020, Mar 2020, Grenoble, France
Communication dans un congrès hal-02956260 v1

Comparison of Synchronous and Asynchronous FIR Filter Architecture

Yoan Decoudu , Jean Simatic , Pauline Alexandre , Katell Morin-Allory , Laurent Fesquet
5th International Conference on Event-Based Control, Communication, and Signal Processing, May 2019, Vienna, Austria
Communication dans un congrès hal-02157364 v1

A Distributed Body-Biasing Strategy for Asynchronous Circuits

Laurent Fesquet , Yoan Decoudu , Rodrigo Iga Jadue , Thiago Ferreira de Paiva Leite , O. Rolloff et al.
27th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC 2019), Oct 2019, Cuzco, Peru
Communication dans un congrès hal-02170157 v1

Desynchronizing Circuits Synthesized with CatapultC

Yoan Decoudu , Jean Simatic , Katell Morin-Allory , Laurent Fesquet
IPSoC 2019, Dec 2019, Grenoble, France
Communication dans un congrès hal-02956177 v1

Extraction of missing formal assumptions in under-constrained designs

G. Plassan , Katell Morin-Allory , D. Borrione
15th ACM-IEEE International Conference on Formal Methods and Models for System Design (MEMOCODE 2017), Sep 2017, Vienna, Austria. pp.94-103
Communication dans un congrès hal-01704634 v1
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Improving the Efficiency of Formal Verification: The Case of Clock-Domain Crossings

Guillaume Plassan , Hans-Jörg Peter , Katell Morin-Allory , Shaker Sarwary , Dominique Borrione
24th IFIP/IEEE International Conference on Very Large Scale Integration - System on a Chip (VLSISOC), Sep 2016, Tallinn, Estonia. pp.108-129, ⟨10.1007/978-3-319-67104-8_6⟩
Communication dans un congrès hal-01675192 v1

Conclusively Verifying Clock-Domain Crossings in Very Large Hardware Designs

G. Plassan , H.J. Peter , Katell Morin-Allory , F. Rahim , S. Sarwary et al.
IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC'16) , Sep 2016, Tallinn, Estonia. pp.1-6
Communication dans un congrès hal-01375436 v1

Verification and Synthesis of Digital Systems from Assertions

D. Borrione , Katell Morin-Allory , M. Liu , Y. Oddos , N. Javaheri
Ecole d'hiver Francophone sur les Technologies de Conception des Systèmes embarqués Hétérogènes (FETCH'16), Jan 2016, Villards de Lans, France
Communication dans un congrès hal-01342631 v1

Revisiting Regular Expressions in SyntHorus2: from PSL SEREs to Hardware

N. Javaheri , Katell Morin-Allory , D. Borrione
Forum on specification & Design Languages (FDL'15), Sep 2015, Barcelona, Spain
Communication dans un congrès hal-01393837 v1

Enabler-Based Synchronizer Model for Clock Domain Crossing static Verification

N. Kebaili , Katell Morin-Allory , J.C. Brignone , D. Borrione
Forum on specification & Design Languages (FDL'15), Sep 2015, Barcelona, Spain
Communication dans un congrès hal-01393835 v1

Design Understanding - At What Abstraction Level is the Pain Most Intense?

Z. Bel Hadj Amor , D. Borrione , N. Javaheri , Katell Morin-Allory , Laurence Pierre
Workshop on Design Automation for Understanding Hardware Designs (DUHDe Friday Workshop DATE 2015), Mar 2015, Grenoble, France
Communication dans un congrès hal-01393830 v1

Design Understanding with Fast Prototyping from Assertions

D. Borrione , N. Javaheri , Katell Morin-Allory
Workshop on Design Automation for Understanding Hardware Designs (Friday Workshop DATE'14), Mar 2014, Dresden, Germany
Communication dans un congrès hal-01060431 v1

Contrôle autonome d'un nano-drone par caméra externe

Laurent Fesquet , Katell Morin-Allory , R. Robin
Journées pédagogiques du CNFM (JPCNFM), Nov 2014, Saint-Malo, France
Communication dans un congrès hal-01166159 v1

SyntHorus-2: Automatic Prototyping from PSL

Katell Morin-Allory , F. Javaheri , D. Borrione
IFIP/IEEE International Conference On Very Large Scale Integration (VLSI-SoC'13), Oct 2013, Istanbul, Turkey. pp.75-80
Communication dans un congrès hal-00919892 v1

Automatic Prototyping of declarative properties on FPGA

D. Borrione , F. Javaheri , Katell Morin-Allory , A. Porcher
Electronic System Level Synthesis Conference (ESLsyn 2013), Jun 2013, Austin, Texas, United States
Communication dans un congrès hal-01060028 v1

Fast Prototyping from Assertions: a Pragmatic Approach

Katell Morin-Allory , F. Javaheri , D. Borrione
11th ACM-IEEE International Conference on "Formal Methods and Models for Codesign (MEMOCODE 2013), Oct 2013, Portland Oregon, United States
Communication dans un congrès hal-00919990 v1

Vérification formelle

Katell Morin-Allory , Laurent Fesquet
12èmes Journées Pédagogiques de la Coordination Nationale pour la Formation en Micro et nanoélectronique (JPCNFM’12), Nov 2012, Saint-Malo, France
Communication dans un congrès hal-01413187 v1

Model of a Simple yet effective Operational Amplifier

F. Paugnat , Laurent Fesquet , Katell Morin-Allory
International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD'12), Sep 2012, Seville, Spain. pp.165-168, ⟨10.1109/SMACD.2012.6339443⟩
Communication dans un congrès hal-00746450 v1

A Performance Comparison Between the SystemC-AMS Models of Computation

F. Paugnat , L. Bousquet , Katell Morin-Allory , Laurent Fesquet
edaWorkshop, May 2011, Dresden, Germany. pp.13-18
Communication dans un congrès hal-00652944 v1

Synthesis of Quasi Delay Insensitive Monitors

A. Porcher , Katell Morin-Allory , Laurent Fesquet
7th Conference on PhD Research in Microelectronics and Electronics (PRIME'11), Jul 2011, Madonna Di Campiglio (Trento), Italy. pp.225 - 228, ⟨10.1109/PRIME.2011.5966274⟩
Communication dans un congrès hal-00646662 v1

C-elements for hardened self-timed circuits

F. Ouchet , Katell Morin-Allory , Laurent Fesquet
21st International Workshop on Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation (PATMOS'11), Sep 2011, Madrid, Spain. pp.247-256, ⟨10.1007/978-3-642-24154-3_25⟩
Communication dans un congrès istex hal-00652365 v1

Does Asynchronous technology bring robustness in synchronous circuit monitoring?

A. Porcher , Katell Morin-Allory , Laurent Fesquet
Forum on specification & Design Languages (FDL'11), Sep 2011, Oldenburg, Germany
Communication dans un congrès hal-00646699 v1

Formal Verification of C-element Circuits

C. Yan , Laurent Fesquet , F. Ouchet , Katell Morin-Allory
IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'11), Apr 2011, Ithaca (NY), United States. pp.55 - 64, ⟨10.1109/ASYNC.2011.14⟩
Communication dans un congrès hal-00624249 v1

A refinement process for top-down mixed-signal designs thanks to SystemC-AMS

F. Paugnat , Katell Morin-Allory , Laurent Fesquet
IEEE 9th International New Circuits and Systems Conference (NEWCAS), Jun 2011, Bordeaux, France. pp.378 - 381, ⟨10.1109/NEWCAS.2011.5981249⟩
Communication dans un congrès hal-00646654 v1

Delay Insensitivity Does Not Mean Slope Insensitivity!

F. Ouchet , Katell Morin-Allory , Laurent Fesquet
IEEE Symposium on Asynchronous Circuits and Systems (ASYNC'10), May 2010, Grenoble, France. pp.176 - 184, ⟨10.1109/ASYNC.2010.27⟩
Communication dans un congrès hal-00492923 v1

Synthesis of asynchronous monitors for critical electronic systems

A. Porcher , Katell Morin-Allory , Laurent Fesquet
IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS'10), Apr 2010, Vienna, Austria. pp.329 - 334, ⟨10.1109/DDECS.2010.5491756⟩
Communication dans un congrès hal-00517676 v1

High-level symbolic simulation for automatic model extraction

F. Ouchet , D. Borrione , Katell Morin-Allory , Laurence Pierre
IEEE Symposium on Design and Diagnostics of Electronic Systems (DDECS'09), Apr 2009, Liberec, Czech Republic. pp.218-221, ⟨10.1109/DDECS.2009.5012132⟩
Communication dans un congrès hal-00417314 v1

MYGEN: Automata-based On-line Test Generator for Assertion-based Verification

Y. Oddos , M. Boulé , Katell Morin-Allory , D. Borrione , Z. Zilic
19th Great Lakes Symposium on VLSI (GLSVLSI'09),, May 2009, Boston (MA), United States. pp.75-80, ⟨10.1145/1531542.1531563⟩
Communication dans un congrès hal-00388359 v1

Synthorus: Highly Efficient Automatic Synthesis from PSL to HDL

Y. Oddos , Katell Morin-Allory , D. Borrione
International Conference On Very Large Scale Integration (VLSI-SoC'09), Oct 2009, Florianopolis, Brazil
Communication dans un congrès hal-00472107 v1

RAT-based formal verification of QDI asynchronous controllers

K. Alsayeg , Katell Morin-Allory , Laurent Fesquet
Forum on specifications and Design Languages (FDL'09), Sep 2009, Nice, Sophia Antipolis, France. pp.1-6
Communication dans un congrès hal-00471574 v1

Initiation à la conception de VLSI numériques

Lorena Anghel , Laurent Fesquet , Katell Morin-Allory
10èmes journées pédagogiques CNFM, Nov 2008, Saint-Malo, France
Communication dans un congrès hal-00385508 v1

Assertion-Based Design with Horus

Y. Oddos , Katell Morin-Allory , D. Borrione
International Conference on Formal Methods and Models for Codesign (MEMOCODE'2008), Jun 2008, Anaheim,CA, United States. pp.75-76, ⟨10.1109/MEMCOD.2008.4547691⟩
Communication dans un congrès hal-00321962 v1

Proving and Disproving Assertion Rewrite Rules by Automated Theorem Proving

Katell Morin-Allory , M. Boulé , D. Borrione , Z. Zilic
IEEE International High Level Design Validation and Test Workshop (HLDVT'2008), Lake Tahoe, Nov 2008, Lake Tahoe, Nevada, United States. pp.56-63, ⟨10.1109/HLDVT.2008.4695875⟩
Communication dans un congrès hal-00354229 v1

Assertion-Based Verification and On-line Testing in Horus

Y. Oddos , Katell Morin-Allory , D. Borrione
International Design and Test Workshop (IDT'08), Dec 2008, Monastir, Tunisia. pp.249 - 255
Communication dans un congrès hal-00354278 v1

Prototyping Generators for On-line Test Vector Generation Based on PSL Properties

Y. Oddos , Katell Morin-Allory , D. Borrione
Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS'07), Apr 2007, Krakow, Russia. pp.1-6, ⟨10.1109/DDECS.2007.4295317⟩
Communication dans un congrès hal-00222935 v1

Asynchronous online monitoring of logical and temporal assertions

Katell Morin-Allory , Laurent Fesquet , D. Borrione
10th Forum on Specification and Design Languages (FDL'07), Sep 2007, Barcelona, Spain
Communication dans un congrès hal-00222895 v1

On-line test vector generation from temporal regular expressions

Y. Oddos , Katell Morin-Allory , D. Borrione
Intensive Workshop on Service Oriented Computing (IWSOC'06), 2006, Le Caire, Egypt. pp.135—140
Communication dans un congrès hal-00156359 v1

On-line test vector generation from temporal constraints written in PSL

Y. Oddos , Katell Morin-Allory , D. Borrione
IFIP International Conference on Very Large Scale Integration (VLSI-SoC 2006), IFIP, 2006, Nice, France. pp.397-402
Communication dans un congrès hal-00134450 v1

Designing parallel programs and integrated circuits

Patrice Quinton , Tanguy Risset , Katell Morin-Allory , David Cachera
International Mathematica Symposium (IMS'06), 2006, Avignon, France. 13 p
Communication dans un congrès hal-00142674 v1

On-line monitoring of properties built on regular expressions

Katell Morin-Allory , D. Borrione
Forum on Specification and Design Languages (FDL'06), 2006, Darmstadt, Germany. pp.249-254
Communication dans un congrès hal-00134431 v1

Automatic generation of a provable circuit model: from VHDL to PVS

Katell Morin-Allory , D. Borrione
8ème International Mathematica Symposium (IMS'06), 2006, Avignon, France. 12 p
Communication dans un congrès hal-00142692 v1

Proven correct monitors from PSL specifications

D. Borrione , Katell Morin-Allory
Proceedings of the conference on Design, automation and test in Europe, 2006, Munich, Germany. pp.1246-1251
Communication dans un congrès hal-00079311 v1

Asynchronous on-line monitoring of PSL assertions

Katell Morin-Allory , Laurent Fesquet , D. Borrione
Seventeenth IEEE International Workshop on Rapid System Prototyping (RSP'06), IEEE, 2006, Chania, Crète, Greece. pp.98 102, ⟨10.1109/RSP.2006.9⟩
Communication dans un congrès hal-00130525 v1

Asynchronous Assertion Monitors for multi-Clock Domain System Verification

Katell Morin-Allory , Laurent Fesquet , D. Borrione
Seventeenth IEEE International Workshop on Rapid System Prototyping (RSP'06), IEEE, 2006, Chania, Crète, Greece. pp.98- 102, ⟨10.1109/RSP.2006.9⟩
Communication dans un congrès hal-00134475 v1

On-Line Assertion-Based Verification with Proven Correct Monitors

D. Borrione , Z.W. Liu , Katell Morin-Allory , P. Ostier , Laurent Fesquet
3rd IEEE International Conference on Information and Communication Technology (ICICT'05), December 5-6, 2005, 2005, cairo, Egypt. pp.123-143
Communication dans un congrès hal-00078798 v1

A proof of correctness for the construction of property monitors

Katell Morin-Allory , D. Borrione
High-Level Design Validation and Test Workshop, 2005. Tenth IEEE International, 2005, Nappa Valley, United States. pp.237- 244, ⟨10.1109/HLDVT.2005.1568843⟩
Communication dans un congrès hal-00079004 v1
Image document

From Assertion-based Verification to Assertion-based Synthesis

Y. Oddos , Katell Morin-Allory , D. Borrione
17th International Conference on Very Large Scale Integration (VLSISOC), Oct 2009, Florianópolis, Brazil. pp.94-117, ⟨10.1007/978-3-642-23120-9_6⟩
Communication dans un congrès hal-01478893 v1
Image document

FMEA on Critical Systems: A Cross-Layer Approach Based on High-Level Models

Julie Roux , Katell Morin-Allory , Vincent Beroulle , Lilian Bossuet , Frederic Cezilly et al.
Victor Grimblatt; Chip Hong Chang; Ricardo Reis; Anupam Chattopadhyay; Andrea Calimera. VLSI-SoC: Technology Advancement on SoC Design, AICT-661, Springer Nature Switzerland; Springer Nature Switzerland, pp.113-134, 2022, VLSI-SoC: Technology Advancement on SoC Design, 978-3-031-16817-8. ⟨10.1007/978-3-031-16818-5_6⟩
Chapitre d'ouvrage hal-04419787 v2

Property-Based Dynamic Verification and Test

D. Borrione , Katell Morin-Allory , Y. Oddos
G. Nicolescu, I. O'Connor, C. Piguet. Design Technology for Heterogeneous Embedded Systems, springer, pp.157-176, 2012, ⟨10.1007/978-94-007-1125-9_8⟩
Chapitre d'ouvrage istex hal-00688409 v1

Asynchronous on-line monitoring of logical and temporal assertions

Katell Morin-Allory , Laurent Fesquet , Benjamin Roustan , Dominique Borrione
Villar Eugenio. Embedded Systems Specification and Design Languages: Selected Contributions from FDL'07, 10, Springer, pp.243-253, 2008, Lecture Notes in Electrical Engineering, ⟨10.1007/978-1-4020-8297-9_17⟩
Chapitre d'ouvrage istex hal-00293779 v1

On-line monitoring of properties built on regular expressions sequences

Katell Morin-Allory , D. Borrione
Sorin A. Huss. Advances in Design and Specification Languages for Embedded Systems (Selected Contributions from FDL'06), Springer, pp.197-207, 2007, ISBN :978-1-4020-6147-9, ⟨10.1007/978-1-4020-6149-3_12⟩
Chapitre d'ouvrage istex hal-00229249 v1

Proving Parameterized Systems: the use of pseudo-pipelines in polyhedral logic

Katell Morin-Allory , David Cachera
Correct Hardware Design and Verification Methods, springer, pp.376-379, 2005, 978-3-540-29105-3. ⟨10.1007/11560548_35⟩
Chapitre d'ouvrage hal-00102816 v1
Image document

Arbitrary Reduced Precision for Fine-grained Accuracy and Energy Trade-offs

N. Ait Said , Mounir Benabdenbi , Katell Morin-Allory
Microelectronics Reliability, 2021, ⟨10.1016/j.microrel.2021.114099⟩
Article dans une revue hal-03332179 v1
Image document

Self-Adaptive Run-Time Variable Floating-Point Precision for Iterative Algorithms: A Joint HW/SW Approach

N. Ait Said , Mounir Benabdenbi , Katell Morin-Allory
Electronics, 2021, pp.2209. ⟨10.3390/electronics10182209⟩
Article dans une revue hal-03440948 v1
Image document

High-level fault injection to assess FMEA on critical systems

Julie Roux , Vincent Beroulle , Katell Morin-Allory , Régis Leveugle , Lilian Bossuet et al.
Microelectronics Reliability, 2021, 122, pp.114135. ⟨10.1016/j.microrel.2021.114135⟩
Article dans une revue hal-03271978 v1

Mining Missing Assumptions from Counter-Examples

G. Plassan , Katell Morin-Allory , D. Borrione
ACM Transactions on Embedded Computing Systems (TECS), 2019, 18 (1), ⟨10.1145/3288759⟩
Article dans une revue hal-02056298 v1

Synthesis of Regular Expressions Revisited: from PSL SEREs to Hardware

N. Javaheri , Katell Morin-Allory , D. Borrione
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2016, 36 (5), pp.869-882. ⟨10.1109/TCAD.2016.2600241⟩
Article dans une revue hal-01457085 v1

Efficient and Correct by Construction Assertion-Based Synthesis

Katell Morin-Allory , N. Javaheri , D. Borrione
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2015, PP (99), pp.1. ⟨10.1109/TVLSI.2014.2386212⟩
Article dans une revue hal-01142595 v1

Un projet de microélectronique numérique original : Contrôle autonome d'un micro-drone par caméras externes

Laurent Fesquet , Katell Morin-Allory , Robin Rolland-Girod
Journal sur l'enseignement des sciences et technologies de l'information et des systèmes, 2015, 14 (2009), pp.9. ⟨10.1051/j3ea/2015021⟩
Article dans une revue hal-01334687 v1

Validating Assertion Language Rewrite Rules and Semantics With Automated Theorem Provers

Katell Morin-Allory , M. Boulé , D. Borrione , Z. Zilic
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2010, 29 (9), pp.1436 - 1448. ⟨10.1109/TCAD.2010.2049150⟩
Article dans une revue hal-00518621 v1

Synthesis of property monitors for online fault detection

Katell Morin-Allory , E. Gascard , D. Borrione
Journal of Circuits, Systems, and Computers, 2007, 16 (6), pp.943 - 960. ⟨10.1142/S0218126607004088⟩
Article dans une revue hal-00419356 v1

Logiciel

D. Borrione , L. Ferro , Laurent Fesquet , Katell Morin-Allory , Y. Oddos et al.
France, Patent n° : FR.001.220016.000.S.P.2009.000.31500. 2009
Brevet hal-00578146 v1
Image document

Vérification Formelle dans le Modèle Polyédrique

Katell Morin-Allory
Réseaux et télécommunications [cs.NI]. Université Rennes 1, 2004. Français. ⟨NNT : ⟩
Thèse tel-00011522 v1