
Katell Morin-Allory
80
Documents
Publications
Publications
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A Survey on Automatic Assertion MinersIEEE 28th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2025), May 2025, Lyon, France. ⟨10.1109/DDECS63720.2025.11006673⟩
Communication dans un congrès
hal-05085439
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WIP: Building an Education Ecosystem for Next Generation Microelectronics Experts in Green and Circular Economy with Digitally-Supported Teaching Methods for Sustainable Chips and Applications (EU Project GreenChips-EDU)2024 IEEE Frontiers in Education Conference (FIE), Oct 2024, Washington, France. pp.1-5, ⟨10.1109/FIE61694.2024.10893342⟩
Communication dans un congrès
hal-04974462
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Formal Resilience Metric Characterization in Complex Digital Systems2024 IEEE European Test Symposium (ETS), May 2024, The Hague, France. pp.1-4, ⟨10.1109/ETS61313.2024.10567525⟩
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hal-04861327
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Formal Fault Injection in Digital Blocks with Mined Assertions2024 22nd ACM-IEEE International Symposium on Formal Methods and Models for System Design (MEMOCODE), ACM IEEE, Oct 2024, Raleigh, United States. pp.77-86, ⟨10.1109/MEMOCODE63347.2024.00014⟩
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hal-04861324
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A Generic CDC Modeling for Data Stability VerificationIEEE 30th International Conference on Electronics, Circuits and Systems (ICECS 2023), Dec 2023, Istanbul, Turkey
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hal-04331999
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Formal Temporal Characterization of Register Vulnerability in Digital Circuits2023 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Jun 2023, Foz do Iguacu, Brazil. pp.1-6, ⟨10.1109/ISVLSI59464.2023.10238514⟩
Communication dans un congrès
hal-04861320
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Data-driven Pruning for Bundled-data Circuits28th International Symposium on Asynchronous Circuits and Systems (ASYNC 2023, Jul 2023, Beijing, China
Communication dans un congrès
hal-04331929
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Method for Data-Driven Pruning in Micropipeline Circuits31st IFIP/IEEE Conference on Very Large Scale Integration (VLSI-SoC 2023), Oct 2023, Sharjah, United Arab Emirates
Communication dans un congrès
hal-04331953
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Cross-layer Approach to Assess FMEA on Critical Systems and Evaluate High-Level Model Realism29th IFIP/IEEE International Conference on very Large Scale Integration, VLSI-SoC 2021, Oct 2021, Singapour, Singapore. ⟨10.1109/VLSI-SoC53125.2021.9607001⟩
Communication dans un congrès
hal-03353865
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A High-Level Design Flow for Locally Body-Biased Asynchronous Circuits29th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC 2021), Oct 2021, Singapore, Singapore. ⟨10.1109/VLSI-SoC53125.2021.9606977⟩
Communication dans un congrès
hal-03662244
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FPU Reduced Variable Precision in Time: Application to the Jacobi Iterative MethodIEEE Computer Society Annual Symposium on VLSI (ISVLSI 2021), Jul 2021, Tampa (FL), United States. ⟨10.1109/ISVLSI51109.2021.00040⟩
Communication dans un congrès
hal-03332203
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FPU Bit-Width Optimization for Approximate Computing: A Non-Intrusive Approach15th Design & Technology of Integrated Systems in Nanoscale Era (DTIS 2020), Apr 2020, Marrakech, Morocco. ⟨10.1109/DTIS48698.2020.9080931⟩
Communication dans un congrès
hal-03331714
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Cross Layer Fault Simulations for Analyzing the Robustness of RTL Designs in Airborne Systems23rd International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), Apr 2020, Novi Sad, Serbia. pp.1-4, ⟨10.1109/DDECS50862.2020.9095559⟩
Communication dans un congrès
hal-02937868
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From High-Level Synthesis to Bundled-Data CircuitsInternational Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS 2020), Jul 2020, Samos, Greece
Communication dans un congrès
hal-02956234
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High Level Fault Injection Method for Evaluating Critical System Parameter Ranges2020 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS), Nov 2020, Glasgow, United Kingdom. pp.1-4, ⟨10.1109/ICECS49266.2020.9294821⟩
Communication dans un congrès
hal-03136621
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Body-Bias Micro-Generators for Activity-Driven Power ManagementFDSOI workshop at DATE Conference 2020, Mar 2020, Grenoble, France
Communication dans un congrès
hal-02956260
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Comparison of Synchronous and Asynchronous FIR Filter Architecture5th International Conference on Event-Based Control, Communication, and Signal Processing, May 2019, Vienna, Austria
Communication dans un congrès
hal-02157364
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A Distributed Body-Biasing Strategy for Asynchronous Circuits27th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC 2019), Oct 2019, Cuzco, Peru
Communication dans un congrès
hal-02170157
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Desynchronizing Circuits Synthesized with CatapultCIPSoC 2019, Dec 2019, Grenoble, France
Communication dans un congrès
hal-02956177
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Extraction of missing formal assumptions in under-constrained designs15th ACM-IEEE International Conference on Formal Methods and Models for System Design (MEMOCODE 2017), Sep 2017, Vienna, Austria. pp.94-103
Communication dans un congrès
hal-01704634
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Improving the Efficiency of Formal Verification: The Case of Clock-Domain Crossings24th IFIP/IEEE International Conference on Very Large Scale Integration - System on a Chip (VLSISOC), Sep 2016, Tallinn, Estonia. pp.108-129, ⟨10.1007/978-3-319-67104-8_6⟩
Communication dans un congrès
hal-01675192
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Conclusively Verifying Clock-Domain Crossings in Very Large Hardware DesignsIFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC'16) , Sep 2016, Tallinn, Estonia. pp.1-6
Communication dans un congrès
hal-01375436
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Verification and Synthesis of Digital Systems from AssertionsEcole d'hiver Francophone sur les Technologies de Conception des Systèmes embarqués Hétérogènes (FETCH'16), Jan 2016, Villards de Lans, France
Communication dans un congrès
hal-01342631
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Revisiting Regular Expressions in SyntHorus2: from PSL SEREs to HardwareForum on specification & Design Languages (FDL'15), Sep 2015, Barcelona, Spain
Communication dans un congrès
hal-01393837
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Enabler-Based Synchronizer Model for Clock Domain Crossing static VerificationForum on specification & Design Languages (FDL'15), Sep 2015, Barcelona, Spain
Communication dans un congrès
hal-01393835
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Design Understanding - At What Abstraction Level is the Pain Most Intense?Workshop on Design Automation for Understanding Hardware Designs (DUHDe Friday Workshop DATE 2015), Mar 2015, Grenoble, France
Communication dans un congrès
hal-01393830
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Design Understanding with Fast Prototyping from AssertionsWorkshop on Design Automation for Understanding Hardware Designs (Friday Workshop DATE'14), Mar 2014, Dresden, Germany
Communication dans un congrès
hal-01060431
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Contrôle autonome d'un nano-drone par caméra externeJournées pédagogiques du CNFM (JPCNFM), Nov 2014, Saint-Malo, France
Communication dans un congrès
hal-01166159
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SyntHorus-2: Automatic Prototyping from PSLIFIP/IEEE International Conference On Very Large Scale Integration (VLSI-SoC'13), Oct 2013, Istanbul, Turkey. pp.75-80
Communication dans un congrès
hal-00919892
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Automatic Prototyping of declarative properties on FPGAElectronic System Level Synthesis Conference (ESLsyn 2013), Jun 2013, Austin, Texas, United States
Communication dans un congrès
hal-01060028
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Fast Prototyping from Assertions: a Pragmatic Approach11th ACM-IEEE International Conference on "Formal Methods and Models for Codesign (MEMOCODE 2013), Oct 2013, Portland Oregon, United States
Communication dans un congrès
hal-00919990
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Vérification formelle12èmes Journées Pédagogiques de la Coordination Nationale pour la Formation en Micro et nanoélectronique (JPCNFM’12), Nov 2012, Saint-Malo, France
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hal-01413187
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Model of a Simple yet effective Operational AmplifierInternational Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD'12), Sep 2012, Seville, Spain. pp.165-168, ⟨10.1109/SMACD.2012.6339443⟩
Communication dans un congrès
hal-00746450
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A Performance Comparison Between the SystemC-AMS Models of ComputationedaWorkshop, May 2011, Dresden, Germany. pp.13-18
Communication dans un congrès
hal-00652944
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Synthesis of Quasi Delay Insensitive Monitors7th Conference on PhD Research in Microelectronics and Electronics (PRIME'11), Jul 2011, Madonna Di Campiglio (Trento), Italy. pp.225 - 228, ⟨10.1109/PRIME.2011.5966274⟩
Communication dans un congrès
hal-00646662
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C-elements for hardened self-timed circuits21st International Workshop on Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation (PATMOS'11), Sep 2011, Madrid, Spain. pp.247-256, ⟨10.1007/978-3-642-24154-3_25⟩
Communication dans un congrès
istex
hal-00652365
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Does Asynchronous technology bring robustness in synchronous circuit monitoring?Forum on specification & Design Languages (FDL'11), Sep 2011, Oldenburg, Germany
Communication dans un congrès
hal-00646699
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Formal Verification of C-element CircuitsIEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'11), Apr 2011, Ithaca (NY), United States. pp.55 - 64, ⟨10.1109/ASYNC.2011.14⟩
Communication dans un congrès
hal-00624249
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A refinement process for top-down mixed-signal designs thanks to SystemC-AMSIEEE 9th International New Circuits and Systems Conference (NEWCAS), Jun 2011, Bordeaux, France. pp.378 - 381, ⟨10.1109/NEWCAS.2011.5981249⟩
Communication dans un congrès
hal-00646654
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Delay Insensitivity Does Not Mean Slope Insensitivity!IEEE Symposium on Asynchronous Circuits and Systems (ASYNC'10), May 2010, Grenoble, France. pp.176 - 184, ⟨10.1109/ASYNC.2010.27⟩
Communication dans un congrès
hal-00492923
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Synthesis of asynchronous monitors for critical electronic systemsIEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS'10), Apr 2010, Vienna, Austria. pp.329 - 334, ⟨10.1109/DDECS.2010.5491756⟩
Communication dans un congrès
hal-00517676
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High-level symbolic simulation for automatic model extractionIEEE Symposium on Design and Diagnostics of Electronic Systems (DDECS'09), Apr 2009, Liberec, Czech Republic. pp.218-221, ⟨10.1109/DDECS.2009.5012132⟩
Communication dans un congrès
hal-00417314
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MYGEN: Automata-based On-line Test Generator for Assertion-based Verification19th Great Lakes Symposium on VLSI (GLSVLSI'09),, May 2009, Boston (MA), United States. pp.75-80, ⟨10.1145/1531542.1531563⟩
Communication dans un congrès
hal-00388359
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Synthorus: Highly Efficient Automatic Synthesis from PSL to HDLInternational Conference On Very Large Scale Integration (VLSI-SoC'09), Oct 2009, Florianopolis, Brazil
Communication dans un congrès
hal-00472107
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RAT-based formal verification of QDI asynchronous controllersForum on specifications and Design Languages (FDL'09), Sep 2009, Nice, Sophia Antipolis, France. pp.1-6
Communication dans un congrès
hal-00471574
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Initiation à la conception de VLSI numériques10èmes journées pédagogiques CNFM, Nov 2008, Saint-Malo, France
Communication dans un congrès
hal-00385508
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Assertion-Based Design with HorusInternational Conference on Formal Methods and Models for Codesign (MEMOCODE'2008), Jun 2008, Anaheim,CA, United States. pp.75-76, ⟨10.1109/MEMCOD.2008.4547691⟩
Communication dans un congrès
hal-00321962
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Proving and Disproving Assertion Rewrite Rules by Automated Theorem ProvingIEEE International High Level Design Validation and Test Workshop (HLDVT'2008), Lake Tahoe, Nov 2008, Lake Tahoe, Nevada, United States. pp.56-63, ⟨10.1109/HLDVT.2008.4695875⟩
Communication dans un congrès
hal-00354229
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Assertion-Based Verification and On-line Testing in HorusInternational Design and Test Workshop (IDT'08), Dec 2008, Monastir, Tunisia. pp.249 - 255
Communication dans un congrès
hal-00354278
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Prototyping Generators for On-line Test Vector Generation Based on PSL PropertiesWorkshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS'07), Apr 2007, Krakow, Russia. pp.1-6, ⟨10.1109/DDECS.2007.4295317⟩
Communication dans un congrès
hal-00222935
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Asynchronous online monitoring of logical and temporal assertions10th Forum on Specification and Design Languages (FDL'07), Sep 2007, Barcelona, Spain
Communication dans un congrès
hal-00222895
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On-line test vector generation from temporal regular expressionsIntensive Workshop on Service Oriented Computing (IWSOC'06), 2006, Le Caire, Egypt. pp.135—140
Communication dans un congrès
hal-00156359
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On-line test vector generation from temporal constraints written in PSLIFIP International Conference on Very Large Scale Integration (VLSI-SoC 2006), IFIP, 2006, Nice, France. pp.397-402
Communication dans un congrès
hal-00134450
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Designing parallel programs and integrated circuitsInternational Mathematica Symposium (IMS'06), 2006, Avignon, France. 13 p
Communication dans un congrès
hal-00142674
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On-line monitoring of properties built on regular expressionsForum on Specification and Design Languages (FDL'06), 2006, Darmstadt, Germany. pp.249-254
Communication dans un congrès
hal-00134431
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Automatic generation of a provable circuit model: from VHDL to PVS8ème International Mathematica Symposium (IMS'06), 2006, Avignon, France. 12 p
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hal-00142692
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Proven correct monitors from PSL specificationsProceedings of the conference on Design, automation and test in Europe, 2006, Munich, Germany. pp.1246-1251
Communication dans un congrès
hal-00079311
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Asynchronous on-line monitoring of PSL assertionsSeventeenth IEEE International Workshop on Rapid System Prototyping (RSP'06), IEEE, 2006, Chania, Crète, Greece. pp.98 102, ⟨10.1109/RSP.2006.9⟩
Communication dans un congrès
hal-00130525
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Asynchronous Assertion Monitors for multi-Clock Domain System VerificationSeventeenth IEEE International Workshop on Rapid System Prototyping (RSP'06), IEEE, 2006, Chania, Crète, Greece. pp.98- 102, ⟨10.1109/RSP.2006.9⟩
Communication dans un congrès
hal-00134475
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On-Line Assertion-Based Verification with Proven Correct Monitors3rd IEEE International Conference on Information and Communication Technology (ICICT'05), December 5-6, 2005, 2005, cairo, Egypt. pp.123-143
Communication dans un congrès
hal-00078798
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A proof of correctness for the construction of property monitorsHigh-Level Design Validation and Test Workshop, 2005. Tenth IEEE International, 2005, Nappa Valley, United States. pp.237- 244, ⟨10.1109/HLDVT.2005.1568843⟩
Communication dans un congrès
hal-00079004
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From Assertion-based Verification to Assertion-based Synthesis17th International Conference on Very Large Scale Integration (VLSISOC), Oct 2009, Florianópolis, Brazil. pp.94-117, ⟨10.1007/978-3-642-23120-9_6⟩
Communication dans un congrès
hal-01478893
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Real-Time Switched Capacitor Based Power Side-Channel Attack DetectionVLSI-SOC 2023, Oct 2023, Sharjah - UAE, Saudi Arabia
Poster de conférence
hal-04861368
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FMEA on Critical Systems: A Cross-Layer Approach Based on High-Level ModelsVictor Grimblatt; Chip Hong Chang; Ricardo Reis; Anupam Chattopadhyay; Andrea Calimera. VLSI-SoC: Technology Advancement on SoC Design, AICT-661, Springer Nature Switzerland; Springer Nature Switzerland, pp.113-134, 2022, VLSI-SoC: Technology Advancement on SoC Design, 978-3-031-16817-8. ⟨10.1007/978-3-031-16818-5_6⟩
Chapitre d'ouvrage
hal-04419787
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Property-Based Dynamic Verification and TestG. Nicolescu, I. O'Connor, C. Piguet. Design Technology for Heterogeneous Embedded Systems, springer, pp.157-176, 2012, ⟨10.1007/978-94-007-1125-9_8⟩
Chapitre d'ouvrage
istex
hal-00688409
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Asynchronous on-line monitoring of logical and temporal assertionsVillar Eugenio. Embedded Systems Specification and Design Languages: Selected Contributions from FDL'07, 10, Springer, pp.243-253, 2008, Lecture Notes in Electrical Engineering, ⟨10.1007/978-1-4020-8297-9_17⟩
Chapitre d'ouvrage
istex
hal-00293779
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On-line monitoring of properties built on regular expressions sequencesSorin A. Huss. Advances in Design and Specification Languages for Embedded Systems (Selected Contributions from FDL'06), Springer, pp.197-207, 2007, ISBN :978-1-4020-6147-9, ⟨10.1007/978-1-4020-6149-3_12⟩
Chapitre d'ouvrage
istex
hal-00229249
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Proving Parameterized Systems: the use of pseudo-pipelines in polyhedral logicCorrect Hardware Design and Verification Methods, springer, pp.376-379, 2005, 978-3-540-29105-3. ⟨10.1007/11560548_35⟩
Chapitre d'ouvrage
hal-00102816
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LogicielFrance, Patent n° : FR.001.220016.000.S.P.2009.000.31500. 2009
Brevet
hal-00578146
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Vérification Formelle dans le Modèle PolyédriqueRéseaux et télécommunications [cs.NI]. Université Rennes 1, 2004. Français. ⟨NNT : ⟩
Thèse
tel-00011522
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Verification of Control Properties in the Polyhedral Model[Research Report] RR-4756, INRIA. 2003
Rapport
(rapport de recherche)
inria-00071830
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