Lirida Naviner
- Télécom Paris
- Département Communications & Electronique (COMELEC)
- Laboratoire Traitement et Communication de l'Information (LTCI)
- Secure and Safe Hardware (SSH)
Publications
Publications
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RV-Sec5: Enhancing RISC-V Security Evaluation via Targeted ISA-Level Instrumentation using gem5AISC 2026 - 17th Australasian Information Security Conference, Australasian Computer Science Week (ACSW 2026), Feb 2026, Melbourne, Australia. In press, ⟨10.1145/3793638.3793640⟩ |
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Bypass Synchronization Primitives: GhostRace Attack and Mitigation on RISC-V7th Computing, Communications and IoT Applications Conference (ComComAp 2025), Dec 2025, Madrid, Spain |
Near-sensor testing method for observing radiation-induced soft errors in modern sensorsConference on Design of Circuits and Integrated Systems (DCIS 2025), Nov 2025, Santander, Spain |
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Opcode Analysis of Real Encryption-Based Microarchitectural Attacks Using gem5ComComAp 2025 - 7th Computing, Communications and IoT Applications Conference, Dec 2025, Madrid, Spain. pp.377-384, ⟨10.1109/ComComAp68359.2025.11353163⟩ |
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HYGENE: A Diffusion-Based Hypergraph Generation MethodThe 39th AAAI Conference on Artificial Intelligence e (AAAI-25), Association for the Advancement of Artificial Intelligence, Feb 2025, Philadelphia, United States. pp.16682-16690, ⟨10.1609/aaai.v39i16.33833⟩ |
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Leveraging gem5 and Machine Learning for End-to-End Detection of Cache-based Side-Channel Attack PatternsPROOFS 2025 - 13th International Workshop on Security Proofs for Embedded Systems, Sep 2025, Kuala Lumpur, Malaysia |
Impact of scaling up the sensor sampling frequency on the reliability of edge processing systems in tolerating soft errors caused by neutronsIEEE Sensors Conference 2024, Oct 2024, Kobe, Japan |
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Neutron radiation tests and assessment of edge computing systemsInvited talk presented in VII Workshop sobre os Efeitos das Radiações Ionizantes em Componentes e Circuitos Eletrônicos de Uso Aeroespacial (WERICE AEROESPACIAL 2024), Nov 2024, São José dos Campos, Brazil |
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Decoding Attack Behaviors by Analyzing Patterns in Instruction-Based Attacks using gem5RSP 2024 - IEEE International Workshop on Rapid System Prototyping, Oct 2024, North Carolina, United States. pp.1-6, ⟨10.1109/RSP64122.2024.10871078⟩ |
Fast analysis of combinatorial netlists correctness rate based on binomial law and partitioning2023 IEEE 24th Latin American Test Symposium (LATS), Mar 2023, Veracruz, Mexico. pp.1-6, ⟨10.1109/lats58125.2023.10154491⟩ |
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Fast and accurate estimation of correctness rate in combinatorial circuits based on clusteringIEEE Workshop on Silicon Errors in Logic – System Effects SELSE 2023, IEEE, Mar 2023, ONLINE, France. pp.1-6 |
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Minconvnets: a New Class of Multiplication-Less Neural Networks2022 IEEE International Conference on Image Processing (ICIP), Oct 2022, Bordeaux, France. pp.881-885, ⟨10.1109/ICIP46576.2022.9897286⟩ |
Ultra-low Power Access Strategy for Process-Voltage-Temperature Aware STT-MRAM2021 IEEE 14th International Conference on ASIC (ASICON), Oct 2021, Kunming, China. pp.1-4, ⟨10.1109/ASICON52560.2021.9620529⟩ |
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Hybrid MTJ-CMOS Integration for Sigma-Delta ADC2021 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH), Nov 2021, AB, Canada. pp.1-5, ⟨10.1109/NANOARCH53687.2021.9642236⟩ |
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Novel Self-timing Speculative Writing for Unreliable STT-MRAM2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT), Nov 2020, Kunming, China. pp.1-3, ⟨10.1109/ICSICT49897.2020.9278373⟩ |
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Magnetic Tunnel Junction-based Analog-to-Digital Converter using Spin Orbit Torque Mechanism2020 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS), Nov 2020, Glasgow, United Kingdom. pp.1-4, ⟨10.1109/ICECS49266.2020.9294780⟩ |
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Quad-Approx CNNs for Embedded Object Detection Systems2020 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS), Nov 2020, Glasgow, United Kingdom. pp.1-4, ⟨10.1109/ICECS49266.2020.9294829⟩ |
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Deep Learning Approaches for Sparse Recovery in Compressive Sensing2019 11th International Symposium on Image and Signal Processing and Analysis (ISPA), Sep 2019, Dubrovnik, Croatia. pp.129-134, ⟨10.1109/ISPA.2019.8868841⟩ |
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Comprehensive Pulse Shape Induced Failure Analysis in Voltage-Controlled MRAM2019 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH), Jul 2019, Qingdao, China. pp.1-6, ⟨10.1109/NANOARCH47378.2019.181292⟩ |
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Nonlinear Functions in Learned Iterative Shrinkage-Thresholding Algorithm for Sparse Signal Recovery2019 IEEE International Workshop on Signal Processing Systems (SiPS), Oct 2019, Nanjing, China. pp.324-329, ⟨10.1109/SiPS47522.2019.9020469⟩ |
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Stability and Variability Emphasized STT-MRAM Sensing Circuit With Performance Enhancement2018 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), Oct 2018, Chengdu, China. pp.386-389, ⟨10.1109/APCCAS.2018.8605603⟩ |
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MRAM-on-FDSOI Integration: A Bit-Cell Perspective2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Jul 2018, Hong Kong, China. pp.263-268, ⟨10.1109/ISVLSI.2018.00056⟩ |
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Reliability Emphasized MTJ/CMOS Hybrid Circuit Towards Ultra-Low Power2018 Conference on Design of Circuits and Integrated Systems (DCIS), Nov 2018, Lyon, France. pp.1-5, ⟨10.1109/DCIS.2018.8681471⟩ |
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Probability Aware Fault-Injection Approach for SER EstimationProceedings of IEEE Latin American Test Symposium (LATS), Mar 2018, São Paulo, SP, Brazil |
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Using FPGA self-produced transients to emulate SETs for SER estimationProceedings of IEEE Latin American Test Symposium (LATS), Mar 2018, São Paulo, SP, Brazil |
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Compressed Sensing for Wideband HF Channel Estimation4th International Conference on Frontiers of Signal Processing, Sep 2018, Poitiers, France. pp.1-5 |
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Design Space Exploration of Magnetic Tunnel Junction based Stochastic Computing in Deep LearningTo appear in Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI), May 2018, Chicago, Illinois, United States. pp.23-25 |
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Design, Synthesis and Application of A Novel Approximate Adder2018 IEEE 61st International Midwest Symposium on Circuits and Systems (MWSCAS), Aug 2018, Windsor, Canada. pp.488-491, ⟨10.1109/MWSCAS.2018.8624023⟩ |
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Reliability evaluation of circuits designed in multi- and single-stage versions2018 IEEE 9th Latin American Symposium on Circuits & Systems (LASCAS), Feb 2018, Puerto Vallarta, Mexico. pp.1-4, ⟨10.1109/LASCAS.2018.8399927⟩ |
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Enabling Resilient Voltage-Controlled MeRAM Using Write Assist TechniquesIEEE International Symposium on Circuits and Systems (ISCAS), May 2018, Florence, Italy |
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Novel Pulsed-Latch Replacement in Non-Volatile Flip-Flop CoreVLSI (ISVLSI), 2017 IEEE Computer Society Annual Symposium on, Jun 2017, Bochum, Germany |
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Asymmetrical Length Biasing for Energy Efficient Digital CircuitsIEEE Latin American Symposium on Circuits and Systems, Feb 2017, Bariloche, Argentina |
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Energy Efficient Magnetic Tunnel Junction Based Hybrid LSI Using Multi-Threshold UTBB-FD-SOI DeviceGreat Lakes Symposium on VLSI 2017 (GLSVLSI 17), May 2017, Banff, Canada |
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Practical metrics for evaluation of fault-tolerant logic designIEEE Conference of Russian Young Researchers in Electrical and Electronic Engineering, Feb 2017, Saint Petersbourgh, Russia. pp.569-573 |
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Sparsity Analysis using a Mixed Approach with Greedy and LS Algorithms on Channel EstimationInternational Conference on Frontiers of Signal Processing (ICFSP), Sep 2017, Paris, France. pp.91-95 |
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Analysis of Ageing effects on ARTIX7 XILINX FPGAEuropean Symposium on Reliability of Electron Devices, Failure Physics and Analysis (ESREF), Sep 2017, Bordeaux, France |
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A process-variation-resilient methodology of circuit design by using asymmetrical forward body bias in 28 nm FDSOIESREF 2016, 27th EUROPEAN SYMPOSIUM ON RELIABILITY OF ELECTRON DEVICES, FAILURE PHYSICS AND ANALYSIS, Sep 2016, Händel-Halle, Halle, Germany. ⟨10.1016/j.microrel.2016.07.073⟩ |
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Design Considerations for Reliable OxRAM-based Non-Volatile Flip-Flops in 28nm FD-SOI TechnologyIEEE International Symposium on Circuits and Systems (ISCAS 2016), May 2016, Montréal, Canada. pp.1146-1149, ⟨10.1109/ISCAS.2016.7527448⟩ |
A Layout-Based Fault Injection Methodology for SER Prediction: Implementation and Correlation with 65nm Heavy Ion Experimental ResultsProceedings of IEEE Nuclear and Space Radiation Effects Conference (NSREC), Jul 2016, New Orleans, United States |
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Approximate Computing in MOS/Spintronic Non-Volatile Full-Adder12th ACM/IEEE International Symposium on Nanoscale Architectures, Jun 2016, Beijing, China |
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Radiation Hardening Improvement of a SerDes under Heavy Ions up to 60 MeV.cm2/mg by Layout-Aware Fault InjectionProceedings of IEEE Workshop on Silicon Errors in Logic - System Effects (SELSE), Mar 2016, Austin, Texas, United States |
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A novel circuit design of true random number generator using magnetic tunnel junction12th ACM/IEEE International Symposium on Nanoscale Architectures (Nanoarch 2016), At Beijing, China, Jul 2016, Beijing, China |
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Design insights for reliable energy efficient OxRAM-based flip-flop in 28nm FD-SOIProceedings of IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), Oct 2015, Sonoma Valley, CA, United States |
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D2D Broadcast Communications for 4G PMR NetworksProceedings of IFIF International Conference on New Technologies, Mobility and Security (NTMS), Jul 2015, Paris, France |
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Stochastic Computation With Spin Torque Transfer Magnetic Tunnel JunctionIEEE-NEWCAS, Jun 2015, Grenoble, France |
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A Novel Analytical Method for Defect Tolerance AssessmentEuropean Symposium on Reliability of Electron devices, Failure physics and Analysis, Oct 2015, Toulouse, France |
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A Tool for Transient Fault Analysis in Combinational CircuitsIEEE International Conference on Electronics, Circuits, and Systems, Dec 2015, Caire, Egypt |
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Partial Triplication of a Sparc-V8 Microprocessor Using Fault InjectionProceedings of IEEE Latin American Symposium on Circuits and Systems (LASCAS), Feb 2015, Montevideo, Uruguay |
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Frequency and Voltage Effects on SER on a 65nm Sparc-V8 Microprocessor Under Radiation TestProceedings of IEEE International Reliability Physics Symposium (IRPS), Apr 2015, Monterrey, CA, United States |
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Ultra wide voltage range consideration of reliability-aware STT magnetic flip-flop in 28nm FDSOI technology26th European Symposium on Reliability of Electron Devices, Failure Physics and Analysis (ESREF), Oct 2015, Toulouse, France |
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A Layout-Aware Approach to Fault Injection for Improving Failure Mode PredictionProceedings of Workshop on Silicon Errors in Logic - System Effects (SELSE), Mar 2015, Austin, United States |
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Battery-aware network discovery algorithm for mobile terminals within heterogeneous networksProceedings of IEEE International Workshop on Computer Aided Modeling and Design of Communication Links and Networks (CAMAD), Dec 2014, Athens, Greece |
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Simulation Study of Aging in CMOS Binary AddersMIPRO 37th International Convention/Microelectronics, Electronics and Electronic Technology, May 2014, Opatija, Croatia |
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Cross Logic : A New Approach for Defect-Tolerant CircuitsIEEE International Conference on IC Design and Technology (ICICDT), May 2014, Austin, United States. pp.1-4 |
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Efficient Implementation for Accurate Analysis of CED Circuits Against Multiple Faults21st International Conference Mixed Design of Integrated Circuits and Systems (MIXDES), Jun 2014, Lublin, Poland |
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Impact of Cluster Size on Routability, Testability and Robustness of a Cluster in a Mesh FPGAIEEE Computer Society Annual Symposium on VLSI (ISVLSI'14), Jul 2014, Tampa, FL, United States. pp.553-558, ⟨10.1109/ISVLSI.2014.66⟩ |
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Reliability-aware Delay Faults Evaluation of CMOS Flip-Flops21st International Conference Mixed Design of Integrated Circuits and Systems (MIXDES), Jun 2014, Lublin, Poland |
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Comparative Study of Defect-Tolerant Multiplexers for FPGAs20th IEEE International On-Line Testing Symposium (IOLTS), Jul 2014, Platja d'Aro, Spain. pp.7-12 |
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OxRAM-Based Non Volatile Flip-Flop in 28nm FDSOI2014 IEEE 12th International New Circuits and Systems Conference (NEWCAS), Jun 2014, Trois Rivières, Canada. ⟨10.1109/NEWCAS.2014.6934003⟩ |
Analytical method for reliability assessment of concurrent checking circuits under multiple faultsMIPRO 37th International Convention/Microelectronics, Electronics and Electronic Technology, May 2014, Opatija, Croatia |
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A Defect-Tolerant Multiplexer Using Differential Logic for FPGAsIEEE 21st Mixed Design of Integrated Circuits and Systems Conference (MIXDES), Jun 2014, Lublin, Poland. pp.375-380 |
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Improving the Robustness of a Switch Box in a Mesh of Clusters FPGA15th IEEE Latin American Test Workshop (LATW), Mar 2014, Fortaleza, Brazil. pp.1-6 |
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Heavy ions test result on a 65nm sparc-v8 radiation-hard microprocessorIEEE International Reliability Physics Symposium, Jun 2014, Waikoloa, Hawai, United States |
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A hybrid reliability assessment method and its support of sequential logic modellingIEEE International On-line Test Symposium, Jul 2014, Platja d'Aro, Spain |
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Efficient Computation of Combinational Circuits Reliability Based on Probabilistic Transfer MatrixInternational Conference on IC Design and Technology (ICICDT), May 2014, Austin, United States |
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Flip-flop selection for in-situ slack-time monito- ring based on the activation probability of timing-critical paths.IEEE International On-line Test Symposium, Jul 2014, Platja d'Aro, Spain |
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A Study of Statistical Variability-aware MethodsIEEE International Symposium on Radio Frequency Integration Technology (RFIT), Aug 2014, Hefei, China |
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A Defect-tolerant Cluster in a Mesh SRAM-based FPGAInternational Conference on Field-Programmable Technology (FPT), Dec 2013, Kyoto, Japan. pp.434-437, ⟨10.1109/FPT.2013.6718407⟩ |
Reliability analysis of combinational circuits with the influences of noise and single-event transientsIEEE Symp. Defect and Fault Tolerance (DFT), Oct 2013, New York City, United States |
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Single Event Transient Mitigation Through Pulse Quenching: Effectiveness at Circuit LevelIEEE International Conference of Electronics, Circuits and Systems (ICECS), Dec 2013, Abu Dhabi, United Arab Emirates |
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A model to simulate the behaviour of probabilistic gatesJournées Nationales du Réseau Doctoral de Microélectronique, Jun 2013, Grenoble, France |
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Selective Hardening Against Multiple Faults Employing a Net-based Reliability AnalysisInternational New Circuits and Systems Conference (NEWCAS), Jun 2013, Paris, France |
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Comparison of Fault-Tolerant Fabless CLBs in SRAM-based FPGAsIEEE Latin-American Test Workshop (LATW), Apr 2013, Cordoba, Argentina. pp.1-6 |
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Evaluating CLB Designs under Multiple SETs in SRAM-based FPGAsIEEE Symp. Defect and Fault Tolerance (DFT), Oct 2013, New-York City, United States. pp.112-117 |
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Reliability Assessment of Combinational Logic Using First-Order-Only Fanout Reconvergence AnalysisMidwest Symposium on Circuits and Systems (MWSCAS), Aug 2013, Columbus, OH., United States |
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Exploring the Impact of Transient Faults on CORDIC ProcessorJournées Nationales du Réseau Doctoral en Micro-nanoélectronique (JNRDM), Jun 2013, Grenoble, France |
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Uplink energy efficiency in LTE systemsIEEE International Workshop on Computer Aided Modeling and Design of Communication Links and Networks, Sep 2013, Berlin, Germany |
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Nouvelle architecture de BLE tolérante aux fautes dans les FPGAs SRAMJournées Nationales du Réseau Doctoral de Microélectronique (JNRDM), Jun 2013, Grenoble, France |
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Evaluation of Fault-tolerant Composite Field AES S-Boxes under Multiple Transient FaultsIEEE International NEWCAS Conference, Jun 2013, Paris, France. pp.1 - 4 |
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A General Cost-effective Design Structure for Probabilistic-Based Noise-Tolerant Logic Functions in Nanometer CMOS TechnologyEurocon 2013, Jul 2013, Zagreb, Croatia. pp.1829-1836, ⟨10.1109/EUROCON.2013.6625225⟩ |
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A Low Cost Reliable Architecture for S-Boxes in AES ProcessorsIEEE Symp. Defect and Fault Tolerance (DFT), Oct 2013, New York City, U.S. Outlying Islands. pp.155-160 |
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Circuit-level Hardening Against Multiple Faults: Combining Global TMR and Selective HardeningJournées Nationales du Réseau Doctoral de Microélectronique, Jun 2013, Grenoble, France |
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SNaP: a Novel Hybrid Method for Circuit Reliability Assessment Under Multiple FaultsEuropean Symposium on Reliability of Electron Devices, Failure Physics and Analysis (ESREF), Oct 2013, Arcachon, France. pp.1230-1234 |
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A defect-tolerant area-efficient multiplexer for basic blocks in SRAM-based FPGAsEuropean Symposium on Reliability of Electron Devices, Failure Physics and Analysis (ESREF), Oct 2013, Arcachon, France. pp.1189-1193 |
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Single-Event-Induced Charge Sharing Effects in TMR with Different Levels of GranularityEuropean Conference on Radiation and Its Effects on Components and Systems (RADECS), Sep 2012, Biarritz, France |
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Exploring the Feasibility of Selective Hardening for Combinational LogicEuropean Symposium on Reliability of Electron Devices, Failure Physics and Analysis (ESREF), Oct 2012, Cagliari, Italy |
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Designing Digital Reliable Processors in NanotechnologiesNanoTechItaly, Nov 2012, Venice, Italy |
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Reliability Analysis of a Reed-Solomon DecoderIEEE International Midwest Symposium on Circuits and Systems (MWSCAS), Aug 2012, Boise, Idaho, United States |
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Green Solutions for Future LTE PMR NetworksIEEE International Workshop on Computer Aided Modeling and Design of Communication Links and Networks (CAMAD), Sep 2012, Barcelona, Spain |
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Selective Hardening Concerning Single and Multiple FaultsJournées Nationales du Réseau Doctoral de Microélectronique (JNRDM), Jun 2012, Marseille, France |
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Transient Fault Analysis of CORDIC ProcessorIEEE International Conference on Electronics, Circuits, and Systems (ICECS), Dec 2012, Séville, Spain. pp.757 - 760 |
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Transient Fault Analysis of CORDIC ProcessorIEEE International Conference on Electronics, Circuits, and Systems (ICECS), Dec 2012, Séville, Spain. pp.757 - 760 |
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Transient Fault Analysis of CORDIC ProcessorIEEE International Conference on Electronics, Circuits, and Systems (ICECS), Dec 2012, Séville, Spain. pp.757 - 760 |
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Tolérance aux défauts dans les FPGAsJournées Nationales du Réseau Doctoral de Microélectronique (JNRDM), Jun 2012, Marseille, France |
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Reliability estimation methods : Tradeoffs between complexity and accuracySouthern Simposium of Microelectronics, Apr 2012, Sao Miguel das Missoes, RS, Brazil |
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Parallel Scaling-Free and Area-Time Efficient CORDIC AlgorithmIEEE International Conference on Electronics, Circuits, and Systems (ICECS), Dec 2012, Séville, Spain. pp.149 - 152 |
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Towards the Mitigation of Multiple Faults Induced by Single Event Effects: Combining Global TMR and Selective HardeningEuropean Conference on Radiation and Its Effects on Components and Systems (RADECS), Sep 2012, Biarritz, France |
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Fault tolerant architectures in nanoelectronics: The progressive approachSouthern Simposium of Microelectronics, Apr 2012, Sao Miguel das Missoes, RS, Brazil |
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Selective Hardening Methodology Concerning Multiple FaultsIEEE Nuclear and Space Radiation Effects Conference, Jul 2012, Miami, Florida, United States |
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Signal Probability, Reliability and Error Bound of Majority Voter in TMRIEEE International Midwest Symposium on Circuits and Systems (MWSCAS), Aug 2012, Boise, Idaho, United States |
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Reliability and Hardening of FPGA Implementations face to Radiative ConstraintsJournées Nationales Electronique et Rayonnements Naturels au Niveau du Sol (RADSOL), Jun 2012, Paris, France |
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Analyzing and Alleviating the Impact of Errors on an SRAM-based FPGA ClusterIEEE International On-Line Testing Symposium (IOLTS), Jun 2012, Sitges, Spain. pp.31-36 |
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A New Fault-Tolerant Architecture for CLBs in SRAM-based FPGAsIEEE International Conference on Electronics, Circuits, and Systems (ICECS), Dec 2012, Sevilla, Spain. pp.761-764 |
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Selective Hardening Methodology for Combinational LogicIEEE Latin-American Test Workshop (LATW), Apr 2012, Quito, Ecuador. pp.6 |
Automatic Selective Hardening Against Soft Errors: a Cost-based and Regularity-aware ApproachIEEE International Conference on Electronics, Circuits, and Systems (ICECS), Dec 2012, Sevilla, Spain. pp.753-756 |
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Optimized Robust Digital Voter in TMR DesignsProceedings of Colloque National GdR SoC-SiP, Jun 2011, Lyon, France |
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Reliability analysis based on significanceArgentine School of Micro-Nanoelectronics Technology and Applications (EAMTA), Aug 2011, Buenos Aires, Argentina. http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=6021291 |
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An approach for efficient reliability improvement of digital circuitsColloque National GdR SoC-SiP, Jun 2011, Lyon, France |
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Effective metrics for reliability analysisCircuits and Systems (MWSCAS), 2010 53rd IEEE International Midwest Symposium on, Aug 2010, Seattle, WA, United States. http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=5548671&tag=1, ⟨10.1109/MWSCAS.2010.5548671⟩ |
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A 65 nm CMOS versatile ADC using time interleaving and ΣΔ modulation for multi-mode receiver2009 Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference (NEWCAS-TAISA), Jun 2009, Toulouse, France. pp.1-4, ⟨10.1109/NEWCAS.2009.5290510⟩ |
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Opcode Analysis of Real Encryption-Based Microarchitectural Attacks Using gem52025 Computing, Communications and IoT Applications (ComComAp), Dec 2025, Madrid, Spain. IEEE, pp.377-384, 2025, ⟨10.1109/ComComAp68359.2025.11353163⟩ |
Decoding Attack Behaviors by Analyzing Patterns in Instruction-Based Attacks using Gem5ACACES 2024 Poster Abstracts, Jul 2024, Fiuggi, Italy |
Cryogenic In-MRAM Computing2021 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH), IEEE, pp.1-6, 2021, ⟨10.1109/NANOARCH53687.2021.9642238⟩ |
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Compact thermal modeling of spin transfer torque magnetic tunnel junctionEuropean Symposium on Reliability of Electron Devices, Failure Physics and Analysis 2015, Oct 2015, Toulouse, France. , 2015, ⟨10.1016/j.microrel.2015.06.029⟩ |
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Compact model of magnetic tunnel junction with stochastic spin transfer torque switching for reliability analysesEuropean Symposium on Reliability of Electron Devices, Failure Physics and Analysis 2014, Sep 2014, Berlin, Germany. , 2014, ⟨10.1016/j.microrel.2014.07.019⟩ |
From DMO to D2DWireless Public Safety Networks: Overview and Challenges, ISTE Press & Elsivier, pp.9-126, 2015 |
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Reliability Aware AMS/RF Performance OptimizationPerformance Optimization Techniques in Analog, Mixed-Signal, and Radio-Frequency Circuit Design, IGI Global, 2014 |
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Reliability Aware AMS / RF Performance OptimizationMourad Fakhfakh, Esteban Tlelo-Cuautle, Maria Helena Fino. Performance Optimization Techniques in Analog, Mixed-Signal, and Radio-Frequency Circuit Design, 2014, ⟨10.4018/978-1-4666-6627-6.ch002⟩ |
Procédé permettant d'établir une stratégie d'économie d'énergie de batterie de terminaux mobilesFrance, N° de brevet: WO Patent App. PCT/EP2013/003,489. XP:Patent-14. 2014 |
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Procédé de Durcissement Logique par Partitionnement d'un Circuit ElectroniqueFrance, N° de brevet: 1261439. GG:BREVET-12. 2012, pp.21 |
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Structure d'Atténuation de Bruit d'une Fonction Logique CombinatoireFrance, N° de brevet: 1262053. KL:BREVET-12. 2012 |