Lorena Anghel

224
Documents
Affiliations actuelles
  • SPINtronique et TEchnologie des Composants (SPINTEC)
  • Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP)
Identifiants chercheurs
Contact

Présentation

CAREER HIGHLIGHTS

  • My research interests were initially oriented towards developing reliable digital integrated circuits in manometric CMSO technologies. Particular emphasis in soft errors modeling and evaluation of their effect on complex integrated design and transient faults hardware/software tolerant design. I have also investigated aging induced reliability issues through modelling and mitigation of these effects cross abstraction layers. More recently I have started a research activity on design, validation and qualification of hardware neural network architectures based on emerging technologies such as memristor and magnetic devices. I am also working on their testing and reliability. On this last topic, since 2019 I have been holding an Excellence Chair position at the AI Multi-Disciplinary Institute in Grenoble on the topic of “Non Volatile Emerging based Spiking Neural Network”.
  • My research activities have been supported by national funding such as French ANR, European funding such as EU projects (MEDEA, CATRENE, COST, RISE), and industrial support.
  • More than 220 publications in review based journals, international and national conferences, 6 book chapters, 15 invited talks
  • 4 best paper awards et 1 outstanding paper award of prestigious conferences such as IEEE Design Automation and Test in Europe (in 2000 and 2015), IEEE Interenational Reliability and Physics of Semiconductors (2012), IEEE VLSI Test Symposium (2004), IEEE Nanoarch (2016)

Since 2000 Supervision of 24 PhD Students (additional 2 international students), 2 post docs and more than 30 master and engineers students

Guest Editor for Special Issue Microprocessors and Microsystems Journal in 2014, and Associated Editor of Microelectronics Reliability 2018-2020, Design for Test Magazine since 2022

Vice Chair of Electronic Design and Automation Association – EDAA

Vice Chair of European Test Technology Technical Council, IEEE Computer Society Chapter

General Chair of IEEE Nanoarch 2022, IEEE VLSI Test Symposium 2020, MEDIAN Workshop 2015, IEEE European Test Symposium 2012, IEEE International on Line Testing Symposium 2005

Vice General Chair of IEEE VLSI Test Symposium 2017, 2018, 2019

Program Chair of IEEE Nanoarch 2017, IEEE VLSI Test Symposium 2015 and 2016, MEDIAN 2013, DCIS 2008 and 2009, DRVW 2008 and 2009.

Member of Program Committee of several IEEE international conferences and workshops related to design, test, reliability and fault tolerance of IEEE such as: VTS, ETS, DATE, LATS, IOLTS, DTIS, IDT, ITC, DCIS, ISVLSI, NANOARCH, DFTS, DMTM, DRVW, EWME, ICCAD, PRIME, SELSE, MEDIAN – every year I attend between 6-8 program committees

CURSUS AND DIPLOMA

Since September 2020 – Distinguised Full Professor at Grenoble Institute of Management and Engineering, June 2020 I have joint SPINTEC laboratory with Full University Professor position. Septembre 2010, Full University Professor (61ème CNU) at Grenoble Institute of Technology, Grenoble (Grenoble INP), Physics, Electronics and Materials Engineering School, affiliated at TIMA Laboratory Septembre 2007, Habilitation à Diriger des Recherches at Grenoble Institute of Technology, Grenoble (Grenoble INP), Micro and Nano Electronics Specialty 2001-2010, Associate Professor (61 section CNU) at Grenoble Institute of Technology, Grenoble (Grenoble INP), Electronics and Telecommunication Engineering School, affiliated at TIMA Laboratory 2000- 2001, Assistent Professor (27ème section CNU) at Joseph Fourier University, Applied Mathematics Institute, Grenoble 2000, PhD in Microelectronic Design, at Grenoble Institute of Technology, Grenoble (Grenoble INP). Cum Laudae 1997, Master of Science at Polytechnic University of Bucharest, Romania, Electronics and Telecommunication Engineering School 1996, Engineer Degree in Electronics and Telecommunication at Polytechnic University of Bucharest, Romania, Electronics and Telecommunication Engineering School

RESEARCH TOPICS

Spintronic-based Design of Neural Networks and Bayesian Neural Networks Reliability evaluation and Testability of Bio-Inspired Hardware Architectures Robustness of hardware accelerators design for machine learning Reliability CMOS and emerging technologies Nanometric Design and Nanotechnologies Methods for Reliability Assessment of Safe and Secure Circuits Fault-Tolerant HW/SW Architectures Cross-layers System-on-Chip (SOC) Reliability Analysis face to different sources: Manufacturing process variations, Soft errors provoked by Cosmic and Atmospheric Radiation, Aging induced Phenomena (NBTI, HCI, TDDB, etc.), Environment: Temperature, voltages Test and Fault Tolerance of Network on Chips (NOCs) in 3D technology Test and robustness of FPGA On Line Testing of Advanced Digital Circuits and Architectures

Domaines de recherche

Micro et nanotechnologies/Microélectronique Arithmétique des ordinateurs Architectures Matérielles [cs.AR] Systèmes embarqués Ingénierie assistée par ordinateur Performance et fiabilité [cs.PF]

Publications

194
8
5
3
2
2
2
2
1
1
1
1
1
1
13
7
6
6
5
5
5
4
4
4
3
3
3
3
3
3
3
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
20
12
3
2
2
2
1
2
119
56
42
3
2
2
1

Publications

Fully analog 28nm FD-SOI hardware solution for drift and variability mitigation of embedded PCM memories in spiking neural networks

Joao Henrique Quintino Palhares , Yann Beilliard , Nikhil Garg , Lorena Anghel , F. Alibart et al.
Frontiers in Neuroscience, In press
Article dans une revue hal-04647208 v1
Image document

Unbiased random bitstream generation using injection-locked spin-torque nano-oscillators

Nhat-Tan Phan , Nitin Prasad , Abderrazak Hakam , Ahmed Sidi El Valli , Lorena Anghel et al.
Physical Review Applied, 2024, 21 (3), pp.034063. ⟨10.1103/PhysRevApplied.21.034063⟩
Article dans une revue hal-04666735 v1

Phase Change Memory Drift Compensation in Spiking Neural Networks Using a Non-Linear Current Scaling Strategy

Joao Henrique Quintino Palhares , Nikhil Garg , Yann Beilliard , Lorena Anghel , Fabien Alibart et al.
Journal of Low Power Electronics and Applications, 2024, 14 (4), pp.50. ⟨10.3390/jlpea14040050⟩
Article dans une revue hal-04757786 v1

28 nm FDSOI embedded PCM exhibiting near zero drift at 12 K for cryogenic SNNs

Joao Henrique Quintino Palhares , Nikhil Garg , Pierre-Antoine Mouny , Yann Beilliard , J. Sandrini et al.
npj Unconventional Computing, 2024, 1 (1), pp.8. ⟨10.1038/s44335-024-00008-y⟩
Article dans une revue hal-04757815 v1
Image document

Spatial-SpinDrop: Spatial dropout-based binary Bayesian neural network with spintronics implementation

Soyed Tuhin Ahmed , Kamal Danouchi , Michael Hefenbrock , Guillaume Prenat , Lorena Anghel et al.
IEEE Transactions on Nanotechnology, 2024, 23, pp.636-643. ⟨10.1109/TNANO.2024.3445455⟩
Article dans une revue hal-04757807 v1

Techniques for detecting and masking faults in semantic segmentation applications

Stéphane Burel , Adrian Evans , Lorena Anghel
Microelectronics Reliability, 2024, 157, pp.115397. ⟨10.1016/j.microrel.2024.115397⟩
Article dans une revue hal-04757827 v1
Image document

MOZART+: Masking Outputs with Zeros for Improved Architectural Robustness and Testing of DNN Accelerators

Stephane Burel , Adrian Evans , Lorena Anghel
IEEE Transactions on Device and Materials Reliability, 2023, 22 (2), pp.120-128. ⟨10.1109/TDMR.2022.3159089⟩
Article dans une revue hal-03823955 v1

SpinBayes: Algorithm-Hardware Co-Design for Uncertainty Estimation Using Bayesian In-Memory Approximation on Spintronic-Based Architectures

Soyed Tuhin Ahmed , Kamal Danouchi , Michael Hefenbrock , Guillaume Prenat , Lorena Anghel et al.
ACM Transactions on Embedded Computing Systems (TECS), 2023, 22 (5s), pp.1-25. ⟨10.1145/3609116⟩
Article dans une revue hal-04202611 v1
Image document

Backpropagation-based learning techniques for deep spiking neural networks: a survey

Manon Dampfhoffer , Thomas Mesquida , Alexandre Valentian , Lorena Anghel
IEEE Transactions on Neural Networks and Learning Systems, 2023, pp.1-16. ⟨10.1109/TNNLS.2023.3263008⟩
Article dans une revue hal-04064177 v1
Image document

A tunable and versatile 28nm FD-SOI crossbar output circuit for low power analog SNN inference with eNVM synapses

Joao Henrique Quintino Palhares , Yann Beilliard , Jury Sandrini , Franck Arnaud , Kevin Garello et al.
Solid-State Electronics, 2023, 209, pp.108779. ⟨10.1016/j.sse.2023.108779⟩
Article dans une revue hal-04221623 v1

Self-Test Library Generation for In-field Test of Path Delay faults

Lorena Anghel , Riccardo Cantoro , Riccardo Masante , Michele Portolan , Sandro Sartoni et al.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2023, pp.1-1. ⟨10.1109/TCAD.2023.3268210⟩
Article dans une revue hal-04083231 v1

SpinDrop: Dropout-Based Bayesian Binary Neural Networks With Spintronic Implementation

Soyed Tuhin Ahmed , Kamal Danouchi , Christopher Münch , Guillaume Prenat , Lorena Anghel et al.
IEEE Journal on Emerging and Selected Topics in Circuits and Systems, 2023, 13 (1), pp.150-164. ⟨10.1109/JETCAS.2023.3242146⟩
Article dans une revue hal-04053929 v1

A fast, energy efficient and tunable magnetic tunnel junction based bitstream generator for stochastic computing

Etienne Becle , Guillaume Prenat , Philippe Talatchian , Lorena Anghel , Ioan-Lucian Prejbeanu
IEEE Transactions on Circuits and Systems I: Regular Papers, 2022, 69 (8), pp.3251-3259. ⟨10.1109/TCSI.2022.3173030⟩
Article dans une revue hal-03823959 v1
Image document

Investigating current-based and gating approaches for accurate and e-efficient spiking recurrent neural networks

Manon Dampfhoffer , Thomas Mesquida , Alexandre Valentian , Lorena Anghel
Lecture Notes in Computer Science, 2022, Artificial Neural Networks and Machine Learning – ICANN 2022, 13531, pp.359-370. ⟨10.1007/978-3-031-15934-3_30⟩
Article dans une revue hal-03823943 v2

Design-time exploration for process, environment and aging compensation techniques for low power reliable-Aware design

Lorena Anghel , Florian Cacho
IEEE Transactions on Emerging Topics in Computing, 2022, 10 (2), pp.581-590. ⟨10.1109/TETC.2021.3136288⟩
Article dans une revue hal-03599345 v1
Image document

Are SNNs really more energy-efficient than ANNs? An in-depth hardware-aware study

Manon Dampfhoffer , Thomas Mesquida , Alexandre Valentian , Lorena Anghel
IEEE Transactions on Emerging Topics in Computational Intelligence, 2022, 2022, pp.1-11. ⟨10.1109/TETCI.2022.3214509⟩
Article dans une revue cea-03852141 v1

Spintronic Memristor based Binarized Ensemble Convolutional Neural Network Architectures

Ghislain Takam Tchendjou , Kamal Danouchi , Guillaume Prenat , Lorena Anghel
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2022, pp.1-1. ⟨10.1109/TCAD.2022.3213612⟩
Article dans une revue hal-03823906 v1
Image document

Robust and Programmable Logic-In-Memory Devices Exploiting Skyrmion Confinement and Channeling Using Local Energy Barriers

Naveen Sisodia , Johan Pelloux-Prayer , Liliana D Buda-Prejbeanu , Lorena Anghel , Gilles Gaudin et al.
Physical Review Applied, 2022, 18 (1), pp.014025. ⟨10.1103/physrevapplied.18.014025⟩
Article dans une revue hal-03740728 v1
Image document

Programmable Skyrmion Logic Gates Based on Skyrmion Tunneling

Naveen Sisodia , Johan Pelloux-Prayer , Liliana D Buda-Prejbeanu , Lorena Anghel , Gilles Gaudin et al.
Physical Review Applied, 2022, 17 (6), pp.064035. ⟨10.1103/physrevapplied.17.064035⟩
Article dans une revue hal-03740729 v1

Deep insights on new embedded resistance and gated diode on thin film silicon BIMOS device with and without external polysilicon resistance for advanced ESD protection in FD-SOI technology

Ph. Galy , Lorena Anghel
Solid-State Electronics, 2021, 185, pp.108092. ⟨10.1016/j.sse.2021.108092⟩
Article dans une revue hal-04957170 v1
Image document

Activity-aware prediction of Critical Paths Aging in FDSOI technologies

K. Senthamarai Kannan , Michele Portolan , Lorena Anghel
Microelectronics Reliability, 2021, 124, ⟨10.1016/j.microrel.2021.114261⟩
Article dans une revue hal-03290896 v1
Image document

Stuck-At Fault Mitigation of Emerging Technologies Based Switching Lattices

Lorena Anghel , A. Bernasconi , V. Ciriani , L. Frontini , G. Trucco et al.
Journal of Electronic Testing: : Theory and Applications, 2020, pp.313-326. ⟨10.1007/s10836-020-05885-2⟩
Article dans une revue hal-03052790 v1
Image document

Circuit Design Steps for Nano-Crossbar Arrays: Area-Delay-Power Optimization with Fault Tolerance

Muhammed Ceylan Morgül , L. Frontini , O. Tunali , Lorena Anghel , V. Ciriani et al.
IEEE Transactions on Nanotechnology, 2020, pp.39-53. ⟨10.1109/TNANO.2020.3044017⟩
Article dans une revue hal-03065940 v1

Topology and design investigation on thin film silicon BIMOS device for ESD protection in FD-SOI technology

Philippe Galy , Louise de Conti , G. Delahaye , Lorena Anghel , Maud Vinet et al.
Microelectronics Reliability, 2019, ⟨10.1016/j.microrel.2019.06.069⟩
Article dans une revue hal-02457726 v1

Test and Reliability in Approximate Computing

Lorena Anghel , Mounir Benabdenbi , Alberto Bosio , Marcello Traiola , Elena Ioana Vatajelu
Journal of Electronic Testing: : Theory and Applications, 2018, 34 (4), pp.375-387. ⟨10.1007/s10836-018-5734-9⟩
Article dans une revue hal-01961787 v1
Image document

Logic synthesis and testing techniques for switching nano-crossbar arrays

D. Alexandrescu , M. Altun , Lorena Anghel , V. Ciriani , Mehdi B. Tahoori et al.
Microprocessors and Microsystems: Embedded Hardware Design , 2017, 54, pp.14-25. ⟨10.1016/j.micpro.2017.08.004⟩
Article dans une revue hal-01710817 v1

Non-volatile magnetic decoder based on MTJs

E.Y. Deng , Guillaune Prenat , Lorena Anghel , W.S. Zhao
Electronics Letters, 2016, 52 (21), pp.1774 - 1776. ⟨10.1049/el.2016.2450⟩
Article dans une revue hal-01864474 v1
Image document

Dependable Multicore Architectures at Nanoscale: The View From Europe

M. Ottavi , S. Pontarelli , D. Gizopoulos , C. Bolchini , M.K. Michael et al.
IEEE Design & Test, 2015, 32 (2), pp.17-28. ⟨10.1109/MDAT.2014.2359572⟩
Article dans une revue hal-01334167 v1

Fault-Tolerant Adaptive Routing under an Unconstrained Set of Node and Link Failures for Many-Core Systems-on-Chip

M. Dimopoulos , Yi Gang , Lorena Anghel , Mounir Benabdenbi , Nacer-Eddine Zergainoh et al.
Microprocessors and Microsystems: Embedded Hardware Design , 2014, 38 (6), pp.620-635. ⟨10.1016/j.micpro.2014.04.003⟩
Article dans une revue hal-01142543 v1

Reliability of TSV interconnects: Electromigration, thermal cycling, and impact on above metal level dielectric

T. Frank , S. Moreau , C. Chappaz , P. Leduc , L. Arnaud et al.
Microelectronics Reliability, 2013, 53 (1), pp.17-29. ⟨10.1016/j.microrel.2012.06.021⟩
Article dans une revue hal-01333966 v1

Kth-Aggressor Fault (KAF)-based Thru-Silicon-Via Interconnect Built-In Self-Test and Diagnosis

V. Pasca , Lorena Anghel , Mounir Benabdenbi
Journal of Electronic Testing: : Theory and Applications, 2012, 28, pp.Online First™, 3 August. ⟨10.1007/s10836-012-5322-3⟩
Article dans une revue istex hal-00744561 v1

CSL: Configurable Fault Tolerant Serial Links for Inter-die Communication in 3D Systems

V. Pasca , Lorena Anghel , M. Nicolaidis , Mounir Benabdenbi
Journal of Electronic Testing: : Theory and Applications, 2012, 28 (1), pp.137-150. ⟨10.1007/s10836-011-5260-5⟩
Article dans une revue istex hal-00650169 v1

Adaptive inter-layer message routing in 3D networks-on-chip

C. Rusu , Lorena Anghel , D. Avresky
Microprocessors and Microsystems: Embedded Hardware Design , 2011, 35 (7), pp.613-631. ⟨10.1016/j.micpro.2011.06.008⟩
Article dans une revue istex hal-00650162 v1

A Case Study on Phase-Locked Loop Automatic Layout Generation and Transient Fault Injection Analysis

C. Lazzari , Lorena Anghel , Ricardo Reis
Journal of Electronic Testing: : Theory and Applications, 2007, 23 (6), pp.625-633. ⟨10.1007/s10836-007-5055-x⟩
Article dans une revue istex hal-00226434 v1

CNTFET modeling and reconfigurable logic circuit design

Ian O'Connor , Junchen Liu , Frédéric Gaffiot , Fabien Prégaldiny , Cristell Maneux et al.
IEEE Transactions on Circuits and Systems, 2007, 54 (11), pp.2365-2379. ⟨10.1109/TCSI.2007.907835⟩
Article dans une revue hal-00187137 v1

Memory Defect Tolerance Architectures for Nanotechnologies

M. Nicolaidis , Lorena Anghel , M.N. Achouri
Journal of Electronic Testing: : Theory and Applications, 2005, Vol. 21, No. 4, August, pp.445 - 455. ⟨10.1007/s10836-005-0971-0⟩
Article dans une revue istex hal-00102825 v1

Simulating single event transients in VDSM ICs for ground level radiation

D. Alexandrescu , Lorena Anghel , M. Nicolaidis
Journal of Electronic Testing: : Theory and Applications, 2004, Aug. ; 20(4), pp.413-21. ⟨10.1023/B:JETT.0000039608.48856.33⟩
Article dans une revue istex hal-00013725 v1

Concurrent checking for VLSI

M. Nicolaidis , Lorena Anghel
Microelectronic Engineering, 1999, Volume 49, Issues 1-2 November, pp.139-156. ⟨10.1016/S0167-9317(99)00435-9⟩
Article dans une revue istex hal-00013767 v1

Low frequency noise in silicon carbide Schottky diodes

Lorena Anghel , T. Ouisse , T. Billon , P. Lassagne , C. Jaussaud
Diamond and Related Materials, 1997, Aug. ; 6(10), pp.1494-6. ⟨10.1016/S0925-9635(97)00055-1⟩
Article dans une revue istex hal-00015780 v1
Image document

Trade-offs in Neural Network Compression: Quantized and Binary Models for Keyword Spotting

Bruno Lovison-Franco , Jonathan Miquel , Aymen Romdhane , Guillaume Prenat , Lorena Anghel et al.
ICECS 2024 - 31st IEEE International Conference on Electronics Circuits and Systems, Nov 2024, Nancy, France. In press
Communication dans un congrès lirmm-04717703 v1

Leveraging stochastic properties of spintronic nanodevices for unconventional computing

Nhat Tan Phan , Lucile Soumah , Louise Desplat , Jonathan Peters , Nitin Prasad et al.
Spintronics XVII, Aug 2024, San Diego, France. pp.41, ⟨10.1117/12.3027425⟩
Communication dans un congrès hal-04757794 v1

KEYNOTE SPEACH - Design of Reliable Spintronic Based Stochastic Neuromorphic systems based on Spintronic emerging technologies

Lorena Anghel
IEEE EAST-WEST DESIGN & TEST SYMPOSIUM (EWDTS-2024), IEEE, Nov 2024, YEREVAN, Armenia
Communication dans un congrès hal-04928437 v1

NeuSpin: Design of a Reliable Edge Neuromorphic System Based on Spintronics for Green AI

Soyed Tuhin Ahmed , Kamal Danouchi , Guillaume Prenat , Lorena Anghel , Mehdi B. Tahoori
2024 Design, Automation & Test in Europe Conference & Exhibition (DATE), IEEE, Mar 2024, Valencia (Espagne), Spain
Communication dans un congrès hal-04637590 v1

Ferroelectric spin orbit devices for ultralow power computing

Salvatore Teresi , Paolo Sgarro , Aurélie Kandazoglou , Théo Frottier , Maxime Culot et al.
2024 8th IEEE Electron Devices Technology & Manufacturing Conference (EDTM), Mar 2024, Bangalore, India. pp.1-3, ⟨10.1109/EDTM58488.2024.10512348⟩
Communication dans un congrès hal-04637588 v1
Image document

Testing spintronics implemented Monte Carlo dropout-based Bayesian neural networks

Soyed Tuhin Ahmed , Kamal Danouchi , Michael Hefenbrock , Guillaume Prenat , Lorena Anghel et al.
ETS 2024 - IEEE European Test Symposium, May 2024, La Haye, Netherlands. pp.1-6, ⟨10.1109/ETS61313.2024.10567852⟩
Communication dans un congrès hal-04637589 v1

SMTJ-based Dropout Module for In-Memory Computing Bayesian Neural Networks

Kamal Danouchi , Guillaume Prenat , Lorena Anghel
2024 IEEE 24th International Conference on Nanotechnology (NANO), Jul 2024, Gijon, France. pp.501-506, ⟨10.1109/NANO61778.2024.10628972⟩
Communication dans un congrès hal-04757821 v1

Enhancing Reliability of Neural Networks at the Edge: Inverted Normalization with Stochastic Affine Transformations

Soyed Tuhin Ahmed , Kamal Danouchi , Guillaume Prenat , Lorena Anghel , Mehdi B. Tahoori
2024 Design, Automation & Test in Europe Conference & Exhibition (DATE), IEEE, Mar 2024, Valencia (Espagne), Spain
Communication dans un congrès hal-04637591 v1

Embedded Tutorial: Hardware design and Reliability Mitigation of Binary Bayesian Reasoning Speakers: Lorena Anghel (Grenoble INP) and Mehdi Tahoori (KIT)

Lorena Anghel , Mehdi Tahoori
IEEE VLSI Test Symposium, IEEE, Apr 2023, San Diego (CA), United States
Communication dans un congrès hal-04148196 v1

Scalable Spintronics-based Bayesian Neural Network for Uncertainty Estimation

Soyed Tuhin Ahmed , Kamal Danouchi , Michael Hefenbrock , Guillaume Prenat , Lorena Anghel et al.
2023 Design, Automation & Test in Europe Conference & Exhibition (DATE), Apr 2023, Antwerp, Belgium. pp.1-6, ⟨10.23919/DATE56975.2023.10137167⟩
Communication dans un congrès hal-04148193 v1

Minimum SRAM Retention Voltage: Insight about optimizing Power Efficiency across Temperature Profile, Process Variation and Aging

Y. Aslan , F. Cacho , T. Kumar , D. Janardan , A. Kumar et al.
2023 IEEE 29th International Symposium on On-Line Testing and Robust System Design (IOLTS), IEEE, Jul 2023, Crete, Greece. pp.1-6, ⟨10.1109/IOLTS59296.2023.10224895⟩
Communication dans un congrès hal-04202681 v1
Image document

Improving the Robustness of Neural Networks to Noisy Multi-Level Non-Volatile Memory-based Synapses

Manon Dampfhoffer , Joel Minguet Lopez , Thomas Mesquida , Alexandre Valentian , Lorena Anghel
2023 International Joint Conference on Neural Networks (IJCNN), Jun 2023, Gold Coast, Australia. pp.10.1109/IJCNN54540.2023.10191804, ⟨10.1109/IJCNN54540.2023.10191804⟩
Communication dans un congrès cea-04185987 v1

Probabilistic Bitstream Generator based on Superparamagnetic Tunnel Junctions

Kamal Danouchi , Guillaume Prenat , Lorena Anghel
2023 IEEE 23rd International Conference on Nanotechnology (NANO), Jul 2023, Jeju City, South Korea. pp.638-642, ⟨10.1109/NANO58406.2023.10231253⟩
Communication dans un congrès hal-04202711 v1
Image document

Leveraging sparsity with Spiking Recurrent Neural Networks for energy-efficient keyword spotting

Manon Dampfhoffer , Thomas Mesquida , Emmanuel Hardy , Alexandre Valentian , Lorena Anghel
2023 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP 2023), Jun 2023, Ixia-Ialyssos, Greece. ⟨10.1109/ICASSP49357.2023.10097174⟩
Communication dans un congrès hal-04149763 v1

A tunable 28nm FD-SOI crossbar output circuit forlow power analog SNN inference with eNVM synapses

Joao Henrique Quintino Palhares , Yann Beilliard , Jury Sandrini , Franck Arnaud , Kevin Garelo et al.
EUROSOI-ULIS 2023, May 2023, Tarragona, Spain
Communication dans un congrès hal-04298975 v1

Robustness and Power Efficiency in Spin-Orbit Torque-Based Probabilistic Logic Circuits

Kamal Danouchi , Guillaume Prenat , Philippe Talatchian , Louis Hutin , Lorena Anghel
2023 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), IEEE, Jun 2023, Foz do Iguacu, Brazil. pp.1-6, ⟨10.1109/ISVLSI59464.2023.10238682⟩
Communication dans un congrès hal-04202688 v1

Evaluating the Impact of Aging on Path-Delay Self-Test Libraries

Riccardo Cantoro , Sandro Sartoni , Matteo Sonza Reorda , Lorena Anghel , Michele Portolan
IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT 2023), Oct 2023, Juan-les-Pins, France. pp.1-7, ⟨10.1109/DFT59622.2023.10313531⟩
Communication dans un congrès hal-04303499 v1

On Using Cell-Aware Methodology for SRAM Bit Cell Testing

Xhesila Xhafa , Aymen Ladhar , Eric Faehn , Lorena Anghel , Gregory Di Pendina et al.
ETS 2023 - 28th IEEE European Test Symposium, May 2023, Venezia, Italy. pp.1-4, ⟨10.1109/ETS56758.2023.10174118⟩
Communication dans un congrès hal-04164704 v1
Image document

Designing networks of resistively-coupled stochastic Magnetic Tunnel Junctions for energy-based optimum search

Kamal Danouchi , Lucile Soumah , Corentin Bouchard , Florian Disdier , Aymen Fassatoui et al.
IEDM 2023 - 69th Annual IEEE International Electron Device Meeting, IEEE, Dec 2023, San Francisco, United States. pp.1-4, ⟨10.1109/IEDM45741.2023.10413843⟩
Communication dans un congrès hal-04359859 v1

Improving DNN fault tolerance in semantic segmentation applications

Stéphane Burel , Adrian Evans , Lorena Anghel
IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), Oct 2022, Austin, United States. pp.1-6, ⟨10.1109/DFT56152.2022.9962354⟩
Communication dans un congrès hal-03960998 v1

Binary Bayesian Neural Networks for Efficient Uncertainty Estimation Leveraging Inherent Stochasticity of Spintronic Devices

Soyed Tuhin Ahmed , Kamal Danouchi , Christopher Münch , Guillaume Prenat , Lorena Anghel et al.
17th ACM International Symposium on Nanoscale Architectures, Association for Computing machinery, Dec 2022, Virtual conference, United States. ⟨10.1145/3565478.3572536⟩
Communication dans un congrès hal-04054228 v1
Image document

Spin Orbit Torque-based Crossbar Array for Error Resilient Binary Convolutional Neural Network

Kamal Danouchi , Guillaume Prenat , Lorena Anghel
23RD IEEE LATIN-AMERICAN TEST SYMPOSIUM, Sep 2022, Montevideo, Uruguay
Communication dans un congrès hal-03834907 v1

Electrical Coupling of Perpendicular Superparamagnetic Tunnel Junctions for Probabilistic Computing

Nhat-Tan Phan , Lucile Soumah , Ahmed Sidi El Valli , Louis Hutin , Lorena Anghel et al.
NANOARCH '22: 17th ACM International Symposium on Nanoscale Architectures, ACM, Dec 2022, Virtual OR USA, United States. pp.1-6, ⟨10.1145/3565478.3572528⟩
Communication dans un congrès hal-04149769 v1
Image document

On Using Cell-Aware Models for Representing SRAM Architecture

Xhesila Xhafa , Aymen Ladhar , Eric Faehn , Lorena Anghel , Gregory Di Pendina et al.
16e Colloque National du GDR SoC², Jun 2022, Strasbourg, France
Communication dans un congrès lirmm-03987914 v1
Image document

Zero-Overhead Protection for CNN Weights

Stéphane Burel , Adrian Evans , Lorena Anghel
2021 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), Oct 2021, Athens (virtual), Greece. ⟨10.1109/DFT52944.2021.9568363⟩
Communication dans un congrès hal-03470345 v1

Fast behavioral VerilogA compact model for stochastic MTJ

Etienne Becle , Philippe Talatchian , Guillaume Prenat , Lorena Anghel , Ioan-Lucian Prejbeanu
ESSDERC 2021 - IEEE 51st European Solid-State Device Research Conference, Sep 2021, Grenoble, France. pp.259-262, ⟨10.1109/ESSDERC53440.2021.9631829⟩
Communication dans un congrès hal-03823963 v1

Ensemble neural networks with spintronic devices - Opportunities and challenges (KEYNOTE TALK)

Lorena Anghel
IEEE / ACM International Symposium on Nanoscale Architectures, Nov 2021, On line conference, France
Communication dans un congrès hal-03602525 v1

Monitoring setup and hold timing limits

Lorena Anghel , F. Cacho , X. Federspiel
2021 IEEE International Reliability Physics Symposium (IRPS), Mar 2021, Monterey, France. pp.1-6, ⟨10.1109/IRPS46558.2021.9405175⟩
Communication dans un congrès hal-03602481 v1
Image document

MOZART: Masking Outputs with Zeros for Architectural Robustness and Testing of DNN Accelerators

Stéphane Burel , Adrian Evans , Lorena Anghel
IEEE International On-Line Testing Symposium, Jun 2021, OnLine, France
Communication dans un congrès hal-03470265 v1

New Perspectives on Core In-field Path Delay Test

Lorena Anghel , Riccardo Cantoro , D. Foti , Michele Portolan , S. Sartoni et al.
International Test Conference (ITC 2020), Nov 2020, Washington DC, United States
Communication dans un congrès hal-03001829 v1
Image document

A Comprehensive End-to-end Solution for a Secure and Dynamic Mixed-signal 1687 System

Michele Portolan , R. Silveira Feitoza , G. Takam Tchendjou , V. Reynaud , K. Senthamarai Kannan et al.
2020 International Symposium on On-Line Testing and Robust System Design (IOLTS 2020), Jul 2020, Naples (Virtual Conference), Italy. ⟨10.1109/IOLTS50870.2020.9159721⟩
Communication dans un congrès hal-02939302 v1
Image document

From 1.8V to 0.19V voltage bias on analog spiking neuron in 28nm UTBB FD-SOI technology

V. Cinçon , Elena Ioana Vatajelu , Lorena Anghel , Philippe Galy
EUROSOI-ULIS 2020, Sep 2020, Caen, France
Communication dans un congrès hal-03001733 v1

State of the art in hardware-accelerated neural networks

Frédéric Pétrot , Lorena Anghel , Liliana Lilibeth Andrade Porras
Applied Machine Learning Days (AMLD 2020), Jan 2020, Lausanne, Switzerland
Communication dans un congrès hal-03185600 v1

Topology and design investigation on thin film silicon BIMOS device for ESD protection in FD-SOI technology

Philippe Galy , Louise de Conti , Maud Vinet , S. Cristoloveanu , G. Delahaye et al.
30th European Symposium on Reliability of Electron Devices, Failure Physics and Analysis (ESREF'2019), Sep 2019, Toulouse, France
Communication dans un congrès hal-02457693 v1

Managing Aging Induced Reliability at Run-time

Lorena Anghel
7th Workshop on Cross-layer Resiliency (IWCR'2019), Jul 2019, Stuttgart, Germany
Communication dans un congrès hal-02457526 v1
Image document

Rebooting Computing: The Challenges for Test and Reliability

Alberto Bosio , Ian O'Connor , G. Rodrigues , F. Lima , Elena Ioana Vatajelu et al.
2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), Oct 2019, Noordwijk, Netherlands. pp.8138-8143, ⟨10.1109/DFT.2019.8875270⟩
Communication dans un congrès hal-02462194 v1

Neuromorphic Computing - From Robust Hardware Architectures to Testing Strategies

Lorena Anghel , Giorgio Di Natale , Benoit Miramond , Elena Ioana Vatajelu , E. Vianello
26th IFIP IEEE International Conference on Very Large Scale Integration (VLSI SOC 2018), Oct 2018, Verona, Italy. pp.176-179, ⟨10.1109/VLSI-SoC.2018.8644897⟩
Communication dans un congrès hal-01961756 v1

Hidden-Delay-Fault Sensor for Test, Reliability and Security

Giorgio Di Natale , Elena Ioana Vatajelu , K. Senthamarai Kannan , Lorena Anghel
IEEE Design Automation and Test Conference in Europe (DATE 2019), Mar 2019, Florence, Italy
Communication dans un congrès hal-02166929 v1

Embedded Hardware Architectures for AI

Lorena Anghel
From Brain and Cognition to Artificial Intelligence Workshop, Jun 2019, Grenoble, France
Communication dans un congrès hal-02473894 v1

Run-time Age Induced Reliability Prediction for SOC

Lorena Anghel
IEEE Latin America Test Symposium (LATS 2019), Mar 2019, Santiago de Chile, Chile
Communication dans un congrès hal-02170194 v1

Flexi-AES: A Highly-Parameterizable Cipher for a Wide Range of Design Constraints

S. Mosanu , X. Guo , Lorena Anghel , Mircea Stan
IEEE 27th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM'2019), Apr 2019, San Diego, United States
Communication dans un congrès hal-02457584 v1

Aging Investigation of Digital Circuits using In-Situ Monitors

R. Shah , F. Cacho , Lorena Anghel
IEEE International Integrated Reliability Workshop (IIRW 2019), Oct 2019, Stanford Sierra, Fallen Leaf Lake, United States
Communication dans un congrès hal-02170209 v1

Special Session: Reliability of Hardware-Implemented Spiking Neural Networks (SNN)

Elena Ioana Vatajelu , Giorgio Di Natale , Lorena Anghel
IEEE VLSI Test Symposium (VTS 2019), Apr 2019, Monterey, United States
Communication dans un congrès hal-02166904 v1

Investigation of speed sensors accuracy for process and aging compensation

R. Shah , F. Cacho , Lorena Anghel
IEEE International reliability Physics Symposium (IRPS'2018), Mar 2018, San Francisco, United States
Communication dans un congrès hal-01896556 v1

Neuromorphic Circuits

Lorena Anghel
L’Intelligence Naturelle au cœur des enjeux de l’Intelligence Artificielle – Les atouts du site grenoblois, Jul 2018, Grenoble, France
Communication dans un congrès hal-02473890 v1
Image document

Resistive and spintronic RAMs: device, simulation, and applications

Elena Ioana Vatajelu , Lorena Anghel , Jean-Michel Portal , Marc Bocquet , Guillaume Prenat
IOLTS 2018 - IEEE 24th International Symposium on On-Line Testing And Robust System Design, Jul 2018, Platja d'Aro, Spain. pp.109-114, ⟨10.1109/IOLTS.2018.8474226⟩
Communication dans un congrès hal-01976583 v1

Integrated Synthesis Methodology for Crossbar Arrays

Muhammed Ceylan Morgül , L. Frontini , Elena Ioana Vatajelu , Lorena Anghel
IEEE NANOARCH'2018, Jul 2018, Athens, Greece
Communication dans un congrès hal-01898674 v1

NBTI aged cell rejuvenation with back biasing and resulting critical path reordering for digital circuits in 28nm FDSOI

A. Sivadasan , R. Shah , F. Cacho , Lorena Anghel
Design Automation and Test in Europe (DATE'2018), Mar 2018, Dresden, Germany
Communication dans un congrès hal-01897768 v1

Worload Dependent Reliability Timing Analysis Flow

A. Sivadasan , V. Huard , Lorena Anghel
DATE 2017, Mar 2017, Lausanne, Switzerland
Communication dans un congrès hal-01664169 v1

Test and reliability in approximate computing

Lorena Anghel , Mounir Benabdenbi , Alberto Bosio , Elena Ioana Vatajelu
IMSTW: International Mixed-Signal Testing Workshop, Jul 2017, Thessaloniki, Greece. ⟨10.1109/IMS3TW.2017.7995210⟩
Communication dans un congrès hal-01702768 v1

Architecture and Workload Dependant Digital Failure Rate

Ajith Sivadasan , S. Mhira , Armelle Notin , A. Benhassain , V. Huard et al.
IEEE International Reliability for Physics of Semiconductors (IRPS 2017), Apr 2017, Monterey, United States. ⟨10.1109/IRPS.2017.7936357⟩
Communication dans un congrès hal-01664216 v1

Fully-Connected Single-Layer STT-MTJ-based Spiking Neural Network under Process Variability

Elena Ioana Vatajelu , Lorena Anghel
ACM/IEEE International Symposium on Nanoscale Architectures - NANOARCH, Jul 2017, Newport, RI, United States
Communication dans un congrès hal-01664222 v1

Reliability Analysis of MTJ-based Functional Module for Neuromorphic Computing

Elena Ioana Vatajelu , Lorena Anghel
International Symposium on On-Line Testing and Robust System Design (IOLTS'17), Jun 2017, Thessaloniki, Greece
Communication dans un congrès hal-01525717 v1

Investigation of critical path selection for in-situ monitors insertion

F. Cacho , A. Benhassain , R. Shah , V. Huard , Lorena Anghel
23rd International Symposium on On-Line Testing and Robust System Design (IOLTS 2017), Jul 2017, Thessaloniki, Greece. pp.247-252
Communication dans un congrès hal-01730857 v1

Study of workload impact on BTI HCI induced aging of digital circuits

A. Sivadasan , F. Cacho , A. Benhassain , V. Huard , Lorena Anghel
Design Automation and Test in Europe (DATE'16), Mar 2016, Dresden, Germany
Communication dans un congrès hal-01474800 v1

Multi-context Non-volatile Content Addressable Memory Using Magnetic Tunnel Junctions

E. Deng , Guillaune Prenat , Lorena Anghel , W. Zhao
12th ACM/IEEE International Symposium on Nanoscale Architectures (NANOARCH'16), Jul 2016, Beijing, China
Communication dans un congrès hal-01474787 v1

A Hybrid Algorithm to Conservatively Check the Robustness of Circuits

N. Thole , Lorena Anghel , G. Fey
IEEE European Test Symposium (ETS'16), May 2016, Amsterdam, Netherlands
Communication dans un congrès hal-01474803 v1

Robustness of Timing in-situ Monitors for AVS Management

A. Benhassain , F. Cacho , V. Huard , S. Mhira , Lorena Anghel et al.
IEEE International Reliability Physics Semiconductor (IRPS'16), Apr 2016, Passadena, United States
Communication dans un congrès hal-01474794 v1

Moniteurs de fiabilité embarqués en technologie FDSOI: Implémentation et Applications

Lorena Anghel
Ecole d'hiver Francophone sur les Technologies de Conception des Systèmes Embarqués Hétérogènes (FETCH'16), Jan 2016, Vilard de Lans, France
Communication dans un congrès hal-01474809 v1

Early system failure prediction by using aging in situ monitors: Methodology of implementation and application results

Lorena Anghel , A. Benhassain , A. Sivadasan
IEEE 34th VLSI Test Symposium (VTS'16), Apr 2016, Las Vegas, NE, United States
Communication dans un congrès hal-01357213 v1

In-Situ Slack Monitors : Taking up the Challenge of On-die Monitoring of Variability and Reliability

A. Benhassain , S. Mhira , F. Cacho , V. Huard , Lorena Anghel
International Verification and Security Workshop, Jul 2016, Sant Feliu de Guixols, Spain
Communication dans un congrès hal-01474807 v1

System Failure Prediction with On-Chip Monitors

Lorena Anghel
Colloque National 2016 de GDR SOC-SIP, May 2016, Nantes, France
Communication dans un congrès hal-01474810 v1

Managing Wear out and Variability Monitors: IEEE 1687 to the Rescue

Lorena Anghel , Michele Portolan
East West Design and test Symposium, Oct 2016, Yerevan, Armenia
Communication dans un congrès hal-01513840 v1

Paradigm shift in the level of Quality and Reliability in semiconductors to a level smaller than 10ppb

Lorena Anghel
Automotive Reliability and Test Workshop, Nov 2016, Fort Worth, United States
Communication dans un congrès hal-01513849 v1

Multi-context non-volatile content addressable memory using magnetic tunnel junctions

Erya Deng , Guillaune Prenat , Lorena Anghel , Weisheng S Zhao
Nanoarch, Jul 2016, Beijing, China
Communication dans un congrès hal-01864477 v1

Workload Impact on BTI HCI Induced Aging of Digital Circuits: A System level Analysis

A. Sivadasan , F. Cacho , A. Benhassain , V. Huard , Lorena Anghel
Workshop on Early Reliability Modeling for Aging and Variability in Silicon Systems, Mar 2016, Dresden, Germany
Communication dans un congrès hal-01474799 v1

Synthesis and Performance Optimization of a Switching Nano-crossbar Computer

D. Alexandrescu , M. Altun , Lorena Anghel , A. Bernasconi , V. Ciriani et al.
Euromicro Conference on Digital System Design (Euromicro DSD/SEAA'16), Aug 2016, Limassol, Cyprus
Communication dans un congrès hal-01473915 v1

Early failure prediction by using in-situ monitors: Implementation and application results

A. Benhassain , F. Cacho , V. Huard , Lorena Anghel
Workshop on Early Reliability Modeling for Aging and Variability in Silicon Systems, Mar 2016, Dresden, Germany
Communication dans un congrès hal-01474797 v1

Application-independent testing of multilevel interconnect in mesh-based FPGAs

Saif-Ur Rehman , Mounir Benabdenbi , Lorena Anghel
IEEE 10th International Conference on Design and Technologies for Integrated System in Nanoscale (DTIS'15), Apr 2015, Naples, Italy. pp.1-6
Communication dans un congrès hal-01400596 v1

Timing in-situ monitors: Implementation strategy and applications results

A. Benhassain , F. Cacho , V. Huard , M. Saliva , Lorena Anghel et al.
IEEE Custom Integrated Circuits Conference (ICICC'16), Sep 2015, San Jose, CA, United States
Communication dans un congrès hal-01474805 v1

Reliability Measurements with In Situ Aging Monitors in FDSOI Technology

Lorena Anghel
International Test Conference (ITC'15), Oct 2015, Anaheim, United States
Communication dans un congrès hal-01400581 v1

Digital circuits reliability with in-situ monitors in 28nm fully depleted SOI

M. Saliva , F. Cacho , V. Huard , X. Federspiel , D. Angot et al.
Design, Automation & Test in Europe Conference & Exhibition (DATE'15), Mar 2015, Grenoble, France. pp.441-446
Communication dans un congrès hal-01400582 v1

Impact of Gate Oxide Breakdown in Logic Gates from 28nm FDSOI CMOS technology

M. Saliva , F. Cacho , C. Ndiaye , V. Huard , D. Angot et al.
IEEE International Reliability Physics Symposium (IRPS'15), Apr 2015, Monterrey, CA, United States. pp.CA.4.1 - CA.4.6
Communication dans un congrès hal-01400593 v1

Exploring the state dependent SET sensitivity of asynchronous logic - The muller-pipeline example

A. Steininger , V.S. Veeravalli , D. Alexandrescu , E. Costenaro , Lorena Anghel
32nd IEEE International Conference on Computer Design (ICCD'14), Oct 2014, Seoul, North Korea. pp.61-67
Communication dans un congrès hal-01400621 v1

Impact of Cluster Size on Routability, Testability and Robustness of a Cluster in a Mesh FPGA

Saif-Ur Rehman , Adrien Blanchardon , Arwa Ben Dhia , Mounir Benabdenbi , Roselyne Chotin-Avot et al.
IEEE Computer Society Annual Symposium on VLSI (ISVLSI'14), Jul 2014, Tampa, FL, United States. pp.553-558, ⟨10.1109/ISVLSI.2014.66⟩
Communication dans un congrès hal-01400630 v1

Efficient Fault-Tolerant Adaptive Routing under an unconstrained Set of Node and Link Failures for Many Cores System On Chip

M. Dimopoulos , Yi Gang , Mounir Benabdenbi , Lorena Anghel
Workshop on Dependable Multicore and Transactional Memory Systems (DMTM'14), (joint to HIPEAC event), Jan 2014, Vienna, Austria. pp.1-2
Communication dans un congrès hal-01128367 v1

New Approaches in Soft Errors Fault Tolerant Design for digital circuits based on Double Sampling Techniques

Lorena Anghel
Ecole d'hiver Francophone sur les Technologies de Conception des Systèmes embarqués Hétérogènes (FETCH 2014), Jan 2014, Ottawa, Canada
Communication dans un congrès hal-01060416 v1

Cost-efficient of a cluster in a mesh SRAM-based FPGA

Saif-Ur Rehman , Mounir Benabdenbi , Lorena Anghel
IEEE 20th International On-Line Testing Symposium (IOLTS'14), Jul 2014, Platja d'Aro, Girona, Spain. pp.75-80
Communication dans un congrès hal-01400623 v1

Single Event Effects in Muller C-Elements and Asynchronous Circuits Over a Wide Energy Spectrum

Lorena Anghel , V. Savulimedu Veeravalli , D. Alexandrescu , A. Steininger , K. Schneider-Hornstein et al.
The 10th IEEE Workshop on Silicon Errors in Logic - System Effects (SELSE'14), Apr 2014, Stanford, United States
Communication dans un congrès hal-01123646 v1

New Insight about Oxide Breakdown Occurrence at Circuit Level

M. Saliva , F. Cacho , V. Huard , D. Angot , M. Durand et al.
IEEE International Reliability Physics Symposium (IRPS'14), Jun 2014, Waikoloa, HI, United States
Communication dans un congrès hal-01128363 v1

BIST for Logic and Local Interconnect Resources in a Novel Mesh of Cluster FPGA

Saif-Ur Rehman , Mounir Benabdenbi , Lorena Anghel
IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), Oct 2013, New-York, United States. pp.296 - 301, ⟨10.1109/DFT.2013.6653622⟩
Communication dans un congrès hal-00982772 v1

Fault-tolerant adaptive routing under permanent and temporary failures for many-core systems-on-chip

M. Dimopulos , Yi Gang , Mounir Benabdenbi , Lorena Anghel , Nacer-Eddine Zergainoh et al.
IEEE International On-Line Testing symposium (IOLTS'13), Jul 2013, Chania, Crete, France. pp.7-12, ⟨10.1109/IOLTS.2013.6604043⟩
Communication dans un congrès hal-00997169 v1

Efficient link-level error resilience in 3D NoCs

V. Pasca , Saif-Ur Rehman , Lorena Anghel
IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS'12), Apr 2012, Tallinn, Estonia. pp.127-132, ⟨10.1109/DDECS.2012.6219038⟩
Communication dans un congrès hal-01128378 v1

A predictive bottom-up hierarchical approach to digital system reliability

V. Huard , E. Pion , F. Cacho , D. Croain , V. Robert et al.
IEEE International Reliability Physics Symposium (IRPS'12), Apr 2012, Anaheim, CA, United States. pp.4B.1.1 - 4B.1.10, ⟨10.1109/IRPS.2012.6241830⟩
Communication dans un congrès hal-00747363 v1

Electromigration degradation mechanism analysis of SnAgCu interconnects for eWLB package

T. Frank , C. Chappaz , L. Arnaud , X. Federspiel , F. Colella et al.
IEEE International Reliability Physics Symposium (IRPS'12), Apr 2012, Anaheim, CA, United States. pp.2E.5.1 - 2E.5.6, ⟨10.1109/IRPS.2012.6241792⟩
Communication dans un congrès hal-00747359 v1

Towards Low-cost Soft Error Mitigation in SRAM-based FPGAs: a Case Study on AT40K

J. Ferron , Lorena Anghel , Régis Leveugle
3rd IEEE Latin American Symposium on Circuits and Systems (LASCAS'12), Feb 2012, Playa del Carmen, Mexico
Communication dans un congrès hal-00676825 v1

Designing Single Chip Massively Parallel Processors Affected by Extreme Failure Rates

M. Nicolaidis , Lorena Anghel , Nacer-Eddine Zergainoh , D. Avresky
Design, Automation & Test in Europe Conference & Exhibition (DATE'12), Mar 2012, Dresden, Germany
Communication dans un congrès hal-01408773 v1

On the Dependability of 3D Interconnects

Lorena Anghel
Ecole d'hiver Francophone sur les Technologies de Conception des Systèmes embarqués Hétérogènes (FETCH'12), Jan 2012, Alpes d'Huez, France
Communication dans un congrès hal-00677047 v1

Electromigration Behavior of 3D-IC TSV Interconnects

T. Frank , C. Chappaz , L. Arnaud , S. Moreau , P. Leduc et al.
62nd Electronic Components and Technology Conference (ECTC'12), May 2012, San Diego, CA, United States. pp.326 - 330
Communication dans un congrès hal-01408775 v1

Through-Silicon-Via Built-In Self-Repair for Aggressive 3D Integration

M. Nicolaidis , V. Pasca , Lorena Anghel
IEEE 18th International On-Line Testing Symposium (IOLTS), Jun 2012, Sitges, Spain. pp.91-96, ⟨10.1109/IOLTS.2012.6313847⟩
Communication dans un congrès hal-00841561 v1

Design for Test and Reliability in Ultimate CMOS

M. Nicolaidis , Lorena Anghel , Nacer-Eddine Zergainoh , Y. Zorian , T. Karnik et al.
Design, Automation and Test in Europe (DATE'12), Mar 2012, Dresden, Germany. pp.677-682
Communication dans un congrès hal-00688282 v1

Memory BIST with address programmability

A. Fradi , M. Nicolaidis , Lorena Anghel
IEEE international On Line Testing Symposium (IOLT'11), Jul 2011, Athenes, Greece. pp.79 - 85, ⟨10.1109/IOLTS.2011.5993815⟩
Communication dans un congrès hal-00651913 v1

Bottom-up digital system-level reliability modeling

N.R. Amador , V. Huard , E. Pion , F. Cacho , D. Croain et al.
Custom Integrated Circuits Conference (CICC'11), Sep 2011, San Jose, Ca., United States. pp.1 - 4, ⟨10.1109/CICC.2011.6055343⟩
Communication dans un congrès hal-00651936 v1

I-BIRAS: Interconnect Built-In Self-Repair and Adaptive Serialization in 3D Integrated Systems

M. Nicolaidis , V. Pasca , Lorena Anghel
16th IEEE European Test Symposium (ETS'11), May 2011, Trondheim, Norway. pp.208 - 208, ⟨10.1109/ETS.2011.37⟩
Communication dans un congrès hal-00651916 v1

Electromigration Behavior of 3D-IC TSV

T. Frank , C. Chappaz , P. Leduc , L. Arnaud , S. Moreau et al.
Second IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits (3D IC), in conjuction with ITC, Sep 2011, Anaheim, United States
Communication dans un congrès hal-00651930 v1

Resistance Increase Due to Electromigration Induced Depletion Under TSV

T. Frank , C. Chappaz , P. Leduc , L. Arnaud , S. Moreau et al.
IEEE International Reliability Physics Symposium (IRPS'11), Monterey, CA, USA, April 10-14, Apr 2011, Monterey, ca., United States. pp.3F.4.1 - 3F.4.6, ⟨10.1109/IRPS.2011.5784499⟩
Communication dans un congrès hal-00599391 v1

On the Dependability of 3D Interconnects

Lorena Anghel , M. Nicolaidis , V. Pasca
Dependability Issues in Deep-submicron Technologies Workshop (DDT'11), May 2011, Trondheim, Norway
Communication dans un congrès hal-00650195 v1

Criticality of Configuration Bits in SRAM-based FPGAs: Predictive Analysis and Experimental Results

Lorena Anghel , J. Ferron , Régis Leveugle
Workshop on Design for Reliability and Variability (DRVW'11), May 2011, Dana Point, CA, United States
Communication dans un congrès hal-00624239 v1

Efficient Fault Detection Architecture Design of Latch-Based Low Power DSP/MCU Processor

H. Yu , M. Nicolaidis , Lorena Anghel , Nacer-Eddine Zergainoh
16th IEEE European Test Symposium (ETS'11), May 2011, Trondheim, Norway. pp.93 - 98, ⟨10.1109/ETS.2011.20⟩
Communication dans un congrès hal-00651920 v1

Analysis of configuration bit criticality in designs implemented with SRAM-based FPGAs

J. Ferron , Lorena Anghel , Régis Leveugle
IEEE Symposium on Industrial Electronics & Applications (ISIEA'11), Sep 2011, Langkawi, Malaysia. pp.83-88
Communication dans un congrès hal-00643903 v1

Designing cost-effective robust systems by accurate reliability modeling

Lorena Anghel , V. Huard
IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT'11), Oct 2011, Vancouver, Canada
Communication dans un congrès hal-00651413 v1

Configurable Thru-Silicon-Via interconnect Built-In Self-Test and diagnosis

V. Pasca , Lorena Anghel , Mounir Benabdenbi
IEEE Latin America Test Symposium Workshop (LATW'11), Mar 2011, Porto de Galinhas (PE), Brazil. pp.1-6, ⟨10.1109/LATW.2011.5985896⟩
Communication dans un congrès hal-00651437 v1

Non-regular 3D mesh Networks-on-Chip

V. Pasca , Lorena Anghel , C. Rusu , Mounir Benabdenbi
DAC Workshop on Diagnostic Services in Network-on-Chips (DSNoC'10), Jun 2010, Anaheim, United States
Communication dans un congrès hal-00505296 v1

Fault Tolerant Communication in 3D Integrated Systems

V. Pasca , Lorena Anghel , Mounir Benabdenbi
DSN Workshop on Dependable Systems and Networks (WDSN'10), Jun 2010, Chicago, United States. pp.131-135
Communication dans un congrès hal-00505291 v1

I-BIRAS: « Interconnect Built-In Self-Repair and Adaptive-Serialization

M. Nicolaidis , Lorena Anghel , V. Pasca
International Test Conference Workshop on Test of 3D Stacked Systems (3D-TEST), Nov 2010, Austin, TX, United States
Communication dans un congrès hal-01408780 v1

Configurable Serial Fault-Tolerant Link for Communication in 3D Integrated Systems

V. Pasca , Lorena Anghel , C. Rusu , Mounir Benabdenbi
International On-Line Test Symposium (IOLTS'10), Jul 2010, Corfu, Greece. pp.115-120
Communication dans un congrès hal-00505276 v1

Reliability approach of high density Through Silicon Via (TSV)

T. Frank , C. Chappaz , P. Leduc , L. Arnaud , S. Moreau et al.
12th Electronics Packaging Technology Conference (EPTC'10), Dec 2010, Singapore, Singapore. pp.321 - 324, ⟨10.1109/EPTC.2010.5702655⟩
Communication dans un congrès hal-00599560 v1

Interconnect Built-In Self-Repair and Adaptive-Serialization (I-BIRAS) for 3D integrated systems

M. Nicolaidis , V. Pasca , Lorena Anghel
IEEE International On-Line Testing Symposium (IOLTS'10), Jul 2010, Corfu, Greece. pp.218 - 218, ⟨10.1109/IOLTS.2010.5560198⟩
Communication dans un congrès hal-00544575 v1

Checkpoint and rollback recovery in network-on-chip based systems

C. Rusu , Lorena Anghel
Student forum at 15th Asia and South Pacific Design Automation Conference (ASP-DAC'10), Jan 2010, Taipei, Taiwan
Communication dans un congrès hal-00505319 v1

Technology roadmap and evolutions: challenge and criticality

Lorena Anghel
RADPRED Workshop, Jan 2010, Toulouse, France
Communication dans un congrès hal-01408768 v1

Configurable Fault-Tolerant Link for Inter-die Communication in 3D on-Chip Networks

V. Pasca , Lorena Anghel , C. Rusu , Mounir Benabdenbi
European Test Symposium (ETS'10), May 2010, Prague, Czech Republic. pp.258
Communication dans un congrès hal-00505308 v1

Fault Resilient Intra-die and Inter-die Communication in 3D Integrated Systems

V. Pasca , Lorena Anghel , Mounir Benabdenbi
PhD Research in Microelectronics and Electronics Conference, PRIME 2010, May 2010, Berlin, Germany
Communication dans un congrès hal-00505273 v1

RILM: Reconfigurable inter-layer routing mechanism for 3D multi-layer networks-on-chip

C. Rusu , Lorena Anghel , D. Avresky
International On-Line Test Symposium (IOLTS'10), Jul 2010, Corfu, Greece. pp.121-125
Communication dans un congrès hal-00505287 v1

Error Resilience of Inter-Die and Intra-Die Communication with 3D Spidergon STNoC

V. Pasca , Lorena Anghel , C. Rusu , R. Locatelli , M. Coppola
Design Automation and Test in Europe Conference, (DATE'10), Mar 2010, Dresden, Germany. pp.275-278
Communication dans un congrès hal-00505313 v1

A methodology and tool for predictive analysis of configuration bit criticality in SRAM-based FPGAs: experimental results

J. Ferron , Lorena Anghel , Régis Leveugle , A. Bocquillon , F. Miller et al.
3rd International Conference on Signals, Circuits & Systems (SCS), Nov 2009, Djerba, Tunisia
Communication dans un congrès hal-00471173 v1

Message routing in 3D networks-on-chip

C. Rusu , Lorena Anghel , D. Avresky
NORCHIP Conference 2009, Nov 2009, Trondheim, Norway
Communication dans un congrès hal-00505315 v1

Predictive analysis of configuration bit criticality in SRAM-based FPGAs – Methodology, tools, and results

J. Ferron , Lorena Anghel , Régis Leveugle
3ème Colloque du GdR SoC-SiP, Jun 2009, Paris, France
Communication dans un congrès hal-00471524 v1

An Effective Approach to Detect Logic Soft Errors in Digital Circuits Based on GRAAL

H. Yu , M. Nicolaidis , Lorena Anghel
10th International Symposium on Quality of Electronic Design (ISQED'09), Mar 2009, San Jose, CA, United States. pp.236-240, ⟨10.1109/ISQED.2009.4810300⟩
Communication dans un congrès hal-00419289 v1

Multi-level Fault Tolerance in 2D and 3D NoCs

Lorena Anghel , C. Rusu
Workshop international “NOC in Space Applications Round Table”, European Space Agency, Sep 2009, Noordwijk, Netherlands
Communication dans un congrès hal-01408770 v1

Efficient Coordinated Checkpointing Recovery Schemes for Network-on-Chip based Systems

C. Rusu , C. Grecu , Lorena Anghel
2nd International Workshop on Dependable Circuit Design (DECIDE'08), Nov 2008, Playa del Carmen, Mexico, Mexico
Communication dans un congrès hal-00505271 v1

Network-on-Chip Fault Tolerance through Checkpoint and Rollback Recovery

C. Rusu , C. Grecu , Lorena Anghel
National Symposium on System-on-Chip - System-in-Package (GdR SoC-SiP'08),, Jun 2008, Paris, France
Communication dans un congrès hal-00378216 v1

An Analysis and Design Technique to Reduce SET Sensitivity in Combinational Integrated Circuits

C. Lazzari , T. Assis , F. Kastensmidt , G. Wirth , Lorena Anghel et al.
16th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-Soc'08), Oct 2008, Rhodes Island, Greece. pp.114-117
Communication dans un congrès hal-01408783 v1

A flexible network-on-chip simulator for early design space exploration

C. Grecu , A. Ivanov , S. Saleh , C. Rusu , Lorena Anghel et al.
1st Microsystems and Nanoelectronics Research Conference (MNRC 2008), Oct 2008, Ottawa, Canada. pp.33-36, ⟨10.1109/MNRC.2008.4683371⟩
Communication dans un congrès hal-00417335 v1

Blocking and Non-blocking Checkpointing for Networks-on-Chip

C. Rusu , C. Grecu , Lorena Anghel
2nd IEEE Workshop on Dependable and Secure Nanocomputing (WDSN'08), Jun 2008, Anchorage, Alaska, United States
Communication dans un congrès hal-00378213 v1

Initiation à la conception de VLSI numériques

Lorena Anghel , Laurent Fesquet , Katell Morin-Allory
10èmes journées pédagogiques CNFM, Nov 2008, Saint-Malo, France
Communication dans un congrès hal-00385508 v1

Improving the Scalability of Checkpoint Recovery for Networks-on-Chip

C. Rusu , C. Grecu , Lorena Anghel
IEEE International Symposium on Circuits and Systems (ISCAS'08), Seattle, May 2008, Washington, United States. pp.2793-2796, ⟨10.1109/ISCAS.2008.4542037⟩
Communication dans un congrès hal-00378206 v1

Coordinated versus Uncoordinated Checkpoint Recovery for Network-on-Chip based Systems

C. Rusu , C. Grecu , Lorena Anghel
4th IEEE International Symposium on Electronic Design, Test and Applications (DELTA'08), Jan 2008, Hong Kong, China. pp.32-37, ⟨10.1109/DELTA.2008.75⟩
Communication dans un congrès hal-00378203 v1

Structures robustes pour circuits logiques à base de CNTFET

T. Dang , Lorena Anghel , Régis Leveugle
11ème Journées Nationales du Réseau Doctoral en Microélectronique (JNRDM'08), May 2008, Bordeaux, France. pp.66
Communication dans un congrès hal-00347976 v1

Communication Aware Recovery Configurations for Networks-on-Chip

C. Rusu , C. Grecu , Lorena Anghel
14th IEEE International Symposium On-Line Testing (IOLT'08), Jul 2008, Rhodes, Greece. pp.201-206, ⟨10.1109/IOLTS.2008.44⟩
Communication dans un congrès hal-00347938 v1

SET-Factor: An Analysis and Design Tool to Reduce SET Sensitivity in Integrated Circuits

C. Lazzari , T. Assis , F. Kastensmidt , G. Wirth , Lorena Anghel et al.
13th IEEE European Test Symposium (ETS'08), May 2008, Verbania, Italy
Communication dans un congrès hal-01408791 v1

Tools and methodology development for pulsed laser fault injection in SRAM-based FPGAs

V. Pouget , A. Douin , D. Lewis , P. Fouillat , G. Foucard et al.
8th Latin-American Test Workshop (LATW'07), 2007, Cuzco, Peru. pp.Session 8
Communication dans un congrès hal-00156318 v1

Defect Tolerant Logic Gates for Unreliable Future Nanotechnologies

Lorena Anghel , M. Nicolaidis
International Conference on Artificial Neural Networks (IWANN), Jun 2007, San Sebastian, Spain. pp.422-429, ⟨10.1007/978-3-540-73007-1⟩
Communication dans un congrès hal-00472162 v1

Essential Fault-Tolerance Metrics for NoC Infrastructures

C. Grecu , Lorena Anghel , Pande P.P. , A. Ivanov , R. Saleh
IEEE International On-Line Test Symposium (IOLT'07), Jul 2007, Crete, Greece. pp.37-42, ⟨10.1109/IOLTS.2007.31⟩
Communication dans un congrès hal-00174144 v1

Efficient Timing Closure with a Transistor Level Design Flow

C. Lazzari , Cr. Santos , A. Ziesemer , Lorena Anghel , Ricardo Reis
IFIP International Conference on Very Large Scale Integration (VLSI-SoC'07), Oct 2007, Atlanta, GA, United States. pp.312-315
Communication dans un congrès hal-01408793 v1

CNTFET-based CMOS-like gates and dispersion of characteristics

T. Dang , Lorena Anghel , V. Pasca , Régis Leveugle
International Design and Test Workshop (IDT'07), Dec 2007, Cairo, Egypt. pp.151-156
Communication dans un congrès hal-00202099 v1

CNTFET-based logic gates and characteristics

T. Dang , Lorena Anghel , Régis Leveugle
Silicon Nanoelectronics Workshop (SNW'07), Jun 2007, Kyoto, Japan. pp.2
Communication dans un congrès hal-00173965 v1

Multiple Event Transient Induced by Nuclear Reactions in CMOS Logic Cells

C. Rusu , A. Bougerol , Lorena Anghel , C. Weulerse , N. Buard et al.
13th IEEE International On-Line Testing symposium (IOLT'07), Jul 2007, Crete, Greece. pp.137-145, ⟨10.1109/IOLTS.2007.46⟩
Communication dans un congrès hal-00172599 v1

Efficient Transistor Sizing for Soft Error Protection in Combinational Logic Circuits

C. Lazzari , F. Lima , Lorena Anghel , Ricardo Reis
2nd International Workshop on Dependable Circuit Design (DECIDE’07), Dec 2007, Buenos Aires, Argentina
Communication dans un congrès hal-01408792 v1

Defects Tolerant Logic Gates for Unreliable Future Nanotechnologies

Lorena Anghel , M. Nicolaidis
Special Session of International Work-Conference on Artificial Neural Networks (IWANN'07), Jun 2007, San Sebastian, Spain
Communication dans un congrès hal-00547514 v1

SET fault injection methods in analog circuits: case study

A. Ammari , Lorena Anghel , Régis Leveugle , C. Lazzari , Ricardo Reis
8th Latin-American Test Workshop (LATW'07), Mar 2007, Cuzco, Peru. pp.155-160
Communication dans un congrès hal-00156749 v1

CNTFET-based logic gates and simulation

T. Dang , Lorena Anghel , Régis Leveugle
IEEE International Design and Test Workshop (IDT'06, Nov 2006, Dubai, United Arab Emirates. 6 p
Communication dans un congrès hal-00156737 v1

SET and SEU effects at multiple abstraction levels

Lorena Anghel
Single Event Effects Symposium (SEE'06), Jun 2006, Long Beach, CA,, United States
Communication dans un congrès hal-00544551 v1

CNTFET basics and simulation

T. Dang , Lorena Anghel , Régis Leveugle
Design and Test of Integrated Systems (DTIS'06), 2006, Tunis, Tunisia. pp.28-33
Communication dans un congrès hal-00105481 v1

Multiple Defects Tolerant Devices for Unreliable Future Nanotechnologies

C. Lazzari , Lorena Anghel , M. Nicolaidis
IEEE Latin American Test Workshop (LATW'06), Mar 2006, Buenos Aires, Argentina
Communication dans un congrès hal-01408796 v1

Prediction of transients induced by neutrons/protons in CMOS combinational logic cells

A. Hubert , A. Bougerol , F. Miller , N. Buard , Lorena Anghel et al.
12th IEEE International On-Line Testing Symposium (IOLTS'06), 2006, Lake Como, Italy. 9 pp., ⟨10.1109/IOLTS.2006.51⟩
Communication dans un congrès hal-00142517 v1

Phase-Locked Loop Automatic Layout Generation and Transient Fault Injection Analysis: A Case Study

C. Lazzari , Ricardo Reis , Lorena Anghel
12th IEEE International On-Line Testing Symposium (IOLTS'06), 2006, Lake Como, Italy. pp.165-172, ⟨10.1109/IOLTS.2006.48⟩
Communication dans un congrès hal-00143423 v1

Simulation and mitigation of single event effects

Lorena Anghel , M. Nicolaidis
11th-IEEE-International-On-Line-Testing-Symposium, 2005, French Riviera, France. pp.81, ⟨10.1109/IOLTS.2005.65⟩
Communication dans un congrès hal-00013721 v1

Evaluation of SET and SEU effects at multiple abstraction levels

Lorena Anghel , Régis Leveugle , Pierre Vanhauwaert
11th-IEEE-International-On-Line-Testing-Symposium., 2005, French Riviera, France. pp.309-12, ⟨10.1109/IOLTS.2005.28⟩
Communication dans un congrès hal-00015000 v1

On implementing a soft error hardening technique by using an automatic layout generator: case study

C. Lazzari , Lorena Anghel , Ricardo Reis
11th-IEEE-International-On-Line-Testing-Symposium., 2005, French Riviera, France. pp.29-34, ⟨10.1109/IOLTS.2005.45⟩
Communication dans un congrès hal-00015449 v1

Transient and permanent fault tolerance memory cells for unreliable future nanotechnologies

Lorena Anghel , E. Kolonis , M. Nicolaidis
IEEE Latin American Test Workshop (LATW'05), Mar 2005, Salvador Bahia, Brazil. pp.187-192
Communication dans un congrès hal-00457112 v1

Soft error circuit hardening techniques implementation using an automatic layout generator

C. Lazzari , Lorena Anghel , Ricardo Reis
Proceedings of IEEE Latin American Test Workshop (LATW'05), Mar 2005, Salvador Bahia, Brazil. pp.175-180
Communication dans un congrès hal-00460557 v1

A Diversified Memory Built-In Self-Repair Approach for Nanotechnologies

M. Nicolaidis , M.N. Achouri , Lorena Anghel
22nd IEEE VLSI Test Symposium, 2004, Napa Valley, United States. pp.313, ⟨10.1109/VTEST.2004.1299258⟩
Communication dans un congrès hal-00005750 v1

Evaluation of Memory Built-in Self Repair Techniques for High Defect Density Technologies

Lorena Anghel , M. Nicolaidis , M.N. Achouri
10th IEEE Pacific Rim International Symposium on Dependable Computing (PRDC'04), 2004, Tahiti, Papeete French Polynesia, France. pp.315-320, ⟨10.1109/PRDC.2004.1276581⟩
Communication dans un congrès hal-00005749 v1

Coupling Different Methodologies to Validate Obsolete Microprocessors

Lorena Anghel , Raoul Velazco , E. Sanchez , M. Sonza Reorda , G. Squillero
19th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'04), 2004, Cannes, France. pp.250-255, ⟨10.1109/DFT.2004.21⟩
Communication dans un congrès hal-00005828 v1

A Methodology for Test Replacement Solutions of Obsolete Processors

Raoul Velazco , Lorena Anghel , S. Saleh
9th IEEE International On-Line Testing Symposium, 2003, Kos International Convention Center, Kos Island, Greece. pp.209, ⟨10.1109/OLT.2003.1214400⟩
Communication dans un congrès hal-00005832 v1

Preliminary Validation of an Approach Dealing with Processor Obsolescence

Lorena Anghel , Raoul Velazco , S. Saleh , S. Deswaertes , A. El Moucary
18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'03), 2003, Boston, Cambridge, Ma, United States. pp.493, ⟨10.1109/DFTVS.2003.1250148⟩
Communication dans un congrès hal-00005829 v1

A Memory Built-In Self-Repair for High Defect Densities Based on Error Polarities

M. Nicolaidis , M.N. Achouri , Lorena Anghel
18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'03), 2003, Boston, Cambridge, Ma,, United States. pp.459, ⟨10.1109/DFTVS.2003.1250144⟩
Communication dans un congrès hal-00005830 v1

Memory Built-In Self-Repair for Nanotechnologies

M. Nicolaidis , M.N. Achouri , Lorena Anghel
9th IEEE International On-Line Testing Symposium, 2003, Kos International Convention Center, Kos Island, Greece. pp.94-8, ⟨10.1109/OLT.2003.1214373⟩
Communication dans un congrès hal-00005831 v1

Simulating single event transients in DVSM ICs for ground level radiation

D. Alexandrescu , M. Nicolaidis , Lorena Anghel
3rd IEEE Latin American Test Workshop (LATW'02), Feb 2002, Montevideo, Uruguay
Communication dans un congrès hal-01380851 v1

New methods for evaluating the impact of single event transients in VDSM ICs

D. Alexandrescu , Lorena Anghel , M. Nicolaidis
Proceedings-17th-IEEE-International-Symposium-on-Defect-and-Fault-Tolerance-in-VLSI-Systems.-DFT-2002, 2002, Vancouver, BC, Canada. pp.99-107, ⟨10.1109/DFTVS.2002.1173506⟩
Communication dans un congrès hal-00013736 v1

Self-checking circuits versus realistic faults in very deep submicron

Lorena Anghel , M. Nicolaidis , I. Alzaher-Noufal
Proceedings-18th-IEEE-VLSI-Test-Symposium, 2000, Montreal, Que., Canada. pp.55-63, ⟨10.1109/VTEST.2000.843827⟩
Communication dans un congrès hal-00013754 v1

Cost reduction and evaluation of a temporary faults detecting technique

Lorena Anghel , M. Nicolaidis
Proceedings-Design,-Automation-and-Test-in-Europe-Conference-and-Exhibition-2000-Cat.-No.-PR00537, 2000, Paris, France. pp.591-8, ⟨10.1109/DATE.2000.840845⟩
Communication dans un congrès hal-00013756 v1

Evaluation of a Soft Error Tolerance Technique Based on Time and/or Space Redundancy

Lorena Anghel , D. Alexandrescu , M. Nicolaidis
13th Symposium on Integrated Circuits and Systems Design (SBCCI'00), 2000, Manaus, Amazonas, Brazil. pp.237-42, ⟨10.1109/SBCCI.2000.876036⟩
Communication dans un congrès hal-00005833 v1

Implementation and evaluation of a soft error detecting technique

Lorena Anghel , M. Nicolaidis
The 5th IEEE International On-Line Testing Workshop (IOLTW'99), Jul 1999, Rhodes, Grèce
Communication dans un congrès hal-01357768 v1

Concurrent Checking for VLSI

M. Nicolaidis , Lorena Anghel
Third session on Reliability in VLSI circuits: operation, manufacturing and design: operation, manufacturing and design, Jun 1999, Austrans, France. pp.139 - 156
Communication dans un congrès hal-01412486 v1

Built-In Current Sensor for IDDQ Testing in Deep Submicron CMOS

T. Calin , Lorena Anghel , M. Nicolaidis
17TH IEEE VLSI Test Symposium, 1999, Dana Point, California, United States. pp.135-42, ⟨10.1109/VTEST.1999.766657⟩
Communication dans un congrès hal-00005845 v1

Asynchronous Current Monitors for Transient Fault Detection in Deep Submicron CMOS

T. Calin , Lorena Anghel , M. Nicolaidis
4th IEEE International On-Line Testing Workshop (IOLTW'98), Jul 1998, Capri, Italy
Communication dans un congrès hal-01413136 v1

Experimental investigation of noise sources in silicon carbide Schottky barriers

Lorena Anghel , T. Ouisse , T. Billon , P. Lassagne , C. Jaussaud
1996-International-Semiconductor-Conference.-19th-Edition.-CAS-'96-Proceedings-Cat.-No.96TH8170, 1996, Sinaia, Romania. pp.539-42 vol.2, ⟨10.1109/SMICND.1996.557436⟩
Communication dans un congrès hal-00015782 v1

Method to increase the switching speed of MOS transistors by dynamic bias of the bulk

F. Mitu , G. Brezeanu , G. Dilimot , Lorena Anghel , I. Enache
1995-International-Semiconductor-Conference.-CAS'95-Proceedings-Cat.-No.95TH8071, 1995, Sinaia, France. pp.241-4, ⟨10.1109/SMICND.1995.494907⟩
Communication dans un congrès hal-00015787 v1
Image document

In-memory-computing implementation of magnetoresistive networks for ultra-low-power computing

Aymen Romdhane , Bruno Lovison-Franco , Guillaume Prenat , Lorena Anghel , Pascal Benoit et al.
Journées Scientifiques Nationales 2024 du PEPR électronique, Mar 2024, Grenoble, France.
Poster de conférence hal-04697202 v1
Image document

Study and design of MRAM-based in-memory computing architectures for machine learning applications

Bruno Lovison-Franco , Aymen Romdhane , David Novo , Pascal Benoit , Guillaume Prenat et al.
Journées Scientifiques Nationales 2024 du PEPR Électronique, Mar 2024, Grenoble, France
Poster de conférence lirmm-04717768 v1
Image document

Towards Low-Power Embedded ECoG Decoding

Joe Saad , Adrian Evans , Ivan Miro Panades , Tetiana Aksenova , Lorena Anghel
GDR SoC2, Jun 2023, Lyon, France. 2023
Poster de conférence cea-04487786 v1

Cost-efficient Testing of LUT and Intra-cluster Interconnect of a Novel SRAM-based FPGA

Saif-Ur Rehman , Mounir Benabdenbi , Lorena Anghel
Colloque National System-On-Chip System-In-Package (SoC-SiP'13), Jun 2013, Lyon, France. 2013, Colloque National System-On-Chip System-In-Package (SoC-SiP'13)
Poster de conférence hal-01130179 v1

Design techniques to improve the resilience of computing systems: logic layer

Lorena Anghel , M. Nicolaidis
Cross-Layer Reliability of Computing Systems, iet - the institution of engineering and technology, pp.23-42, 2020
Chapitre d'ouvrage hal-02986823 v1

On-Chip Ageing Monitoring and System Adaptation

Lorena Anghel , R. Shah , F. Cacho
Ageing of Integrated Circuits: Causes, Effects and Mitigation TechniquesOn-Chip Ageing Monitoring and System Adaptation, pp.149-180, 2019, 978-3-030-23780-6. ⟨10.1007/978-3-030-23781-3_6⟩
Chapitre d'ouvrage hal-02448115 v1

Adaptive Routing for Fault Tolerance and Congestion Avoidance for 2D Mesh and Torus NoCs in Many-Core Systems-on-Chip

Mounir Benabdenbi , Lorena Anghel , M. Dimopoulos , Yi Gang
Advances in Microelectronics: Reviews, ifsa, international frequency sensor association, pp.405-435, 2017, 978-84-615-9012-4
Chapitre d'ouvrage hal-01707750 v1

Manufacturing Threats

Saman Kiamehr , Mehdi B. Tahoori , Lorena Anghel
Dependable Multicore Architectures at Nanoscale, springer, pp.3-35, 2017, 978-3-319-54421-2. ⟨10.1007/978-3-319-54422-9⟩
Chapitre d'ouvrage hal-02473938 v1

Multilevel Fault Effects Evaluation

Lorena Anghel , M. Rebaudengo , M. Sonza Reorda , M. Violante
RAOUL VELAZCO, PASCAL FOUILLAT and RICARDO REIS. Radiation Effects on Embedded Systems, Springer, pp.69-88, 2007, ISBN :978-1-4020-5645-1, ⟨10.1007/978-1-4020-5646-8⟩
Chapitre d'ouvrage hal-00185911 v1

A Transistor Placement Technique Using Genetic Algorithm And Analytical Programming

C. Lazzari , Lorena Anghel , Ricardo Reis
VLSI-SOC: From Systems to Silicon, (selected contributions from VLSI-SoC'05), Springer, pp.331-344, Vol.240, 2007, Series: IFIP International Federation for Information Processing, ⟨10.1007/978-0-387-73661-7_21⟩
Chapitre d'ouvrage hal-00191996 v1

Defects Tolerant Logic Gates for Unreliable Future Nanotechnologies

Lorena Anghel , M. Nicolaidis
Computational and Ambient Intelligence, Springer, pp.422-429, 2007, ISBN :978-3-540-73006-4, ⟨10.1007/978-3-540-73007-1_52⟩
Chapitre d'ouvrage istex hal-00229300 v1

Cost Reduction and Evaluation of a Temporary Faults Detecting Technique

Lorena Anghel , M. Nicolaidis
Rudy Lauwereins and Jan Madsen. Design, Automation, and Test in Europe (DATE) “The Most Influential Papers of 10 Years”, Springer, pp.423-438, 2007, ISBN :978-1-4020-6487-6, ⟨10.1007/978-1-4020-6488-3_31⟩
Chapitre d'ouvrage istex hal-00229513 v1
Image document

Les limites technologiques du silicium et tolérance aux fautes

Lorena Anghel
Autre [cs.OH]. Institut National Polytechnique de Grenoble - INPG, 2001. Français. ⟨NNT : ⟩
Thèse tel-00002907 v1
Image document

Conception Robuste dans les Technologies CMOS et post-CMOS

Lorena Anghel
Micro et nanotechnologies/Microélectronique. Institut National Polytechnique de Grenoble - INPG, 2007
HDR tel-00185993 v1