Lorena Anghel
- SPINtronique et TEchnologie des Composants (SPINTEC)
- Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP)
Présentation
CAREER HIGHLIGHTS Since 2000 Supervision of 24 PhD Students (additional 2 international students), 2 post docs and more than 30 master and engineers students Guest Editor for Special Issue Microprocessors and Microsystems Journal in 2014, and Associated Editor of Microelectronics Reliability 2018-2020, Design for Test Magazine since 2022 Vice Chair of Electronic Design and Automation Association – EDAA Vice Chair of European Test Technology Technical Council, IEEE Computer Society Chapter General Chair of IEEE Nanoarch 2022, IEEE VLSI Test Symposium 2020, MEDIAN Workshop 2015, IEEE European Test Symposium 2012, IEEE International on Line Testing Symposium 2005 Vice General Chair of IEEE VLSI Test Symposium 2017, 2018, 2019 Program Chair of IEEE Nanoarch 2017, IEEE VLSI Test Symposium 2015 and 2016, MEDIAN 2013, DCIS 2008 and 2009, DRVW 2008 and 2009. Member of Program Committee of several IEEE international conferences and workshops related to design, test, reliability and fault tolerance of IEEE such as: VTS, ETS, DATE, LATS, IOLTS, DTIS, IDT, ITC, DCIS, ISVLSI, NANOARCH, DFTS, DMTM, DRVW, EWME, ICCAD, PRIME, SELSE, MEDIAN – every year I attend between 6-8 program committees CURSUS AND DIPLOMA Since September 2020 – Distinguised Full Professor at Grenoble Institute of Management and Engineering,
June 2020 I have joint SPINTEC laboratory with Full University Professor position.
Septembre 2010, Full University Professor (61ème CNU) at Grenoble Institute of Technology, Grenoble (Grenoble INP), Physics, Electronics and Materials Engineering School, affiliated at TIMA Laboratory
Septembre 2007, Habilitation à Diriger des Recherches at Grenoble Institute of Technology, Grenoble (Grenoble INP), Micro and Nano Electronics Specialty
2001-2010, Associate Professor (61 section CNU) at Grenoble Institute of Technology, Grenoble (Grenoble INP), Electronics and Telecommunication Engineering School, affiliated at TIMA Laboratory
2000- 2001, Assistent Professor (27ème section CNU) at Joseph Fourier University, Applied Mathematics Institute, Grenoble
2000, PhD in Microelectronic Design, at Grenoble Institute of Technology, Grenoble (Grenoble INP). Cum Laudae
1997, Master of Science at Polytechnic University of Bucharest, Romania, Electronics and Telecommunication Engineering School
1996, Engineer Degree in Electronics and Telecommunication at Polytechnic University of Bucharest, Romania, Electronics and Telecommunication Engineering School RESEARCH TOPICS Spintronic-based Design of Neural Networks and Bayesian Neural Networks
Reliability evaluation and Testability of Bio-Inspired Hardware Architectures
Robustness of hardware accelerators design for machine learning
Reliability CMOS and emerging technologies Nanometric Design and Nanotechnologies
Methods for Reliability Assessment of Safe and Secure Circuits
Fault-Tolerant HW/SW Architectures
Cross-layers System-on-Chip (SOC) Reliability Analysis face to different sources: Manufacturing process variations, Soft errors provoked by Cosmic and Atmospheric Radiation, Aging induced Phenomena (NBTI, HCI, TDDB, etc.), Environment: Temperature, voltages
Test and Fault Tolerance of Network on Chips (NOCs) in 3D technology
Test and robustness of FPGA
On Line Testing of Advanced Digital Circuits and Architectures
Domaines de recherche
Publications
Publications
Fault Modeling and Testing of Spin-Orbit Torque-Based Multipillar Memory Cell2025 IFIP/IEEE 33rd International Conference on Very Large Scale Integration (VLSI-SoC), Oct 2025, Puerto Varas, France. pp.1-5, ⟨10.1109/VLSI-SoC64688.2025.11421751⟩ |
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Spintronic Devices for Thermodynamically Guided Analog Computing2025 Device Research Conference (DRC), Jun 2025, Durham, United States. pp.i-ii, ⟨10.1109/DRC66027.2025.11105749⟩ |
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KEYNOTE SPEACH - Design of Reliable Spintronic Based Stochastic Neuromorphic systems based on Spintronic emerging technologiesIEEE EAST-WEST DESIGN & TEST SYMPOSIUM (EWDTS-2024), IEEE, Nov 2024, YEREVAN, Armenia |
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Trade-offs in Neural Network Compression: Quantized and Binary Models for Keyword SpottingICECS 2024 - 31st IEEE International Conference on Electronics Circuits and Systems, Nov 2024, Nancy, France. In press |
Leveraging stochastic properties of spintronic nanodevices for unconventional computingSpintronics XVII, Aug 2024, San Diego, France. pp.41, ⟨10.1117/12.3027425⟩ |
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Ferroelectric spin orbit devices for ultralow power computing2024 8th IEEE Electron Devices Technology & Manufacturing Conference (EDTM), Mar 2024, Bangalore, India. pp.1-3, ⟨10.1109/EDTM58488.2024.10512348⟩ |
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NeuSpin: Design of a Reliable Edge Neuromorphic System Based on Spintronics for Green AI2024 Design, Automation & Test in Europe Conference & Exhibition (DATE), IEEE, Mar 2024, Valencia (Espagne), Spain |
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SMTJ-based Dropout Module for In-Memory Computing Bayesian Neural Networks2024 IEEE 24th International Conference on Nanotechnology (NANO), Jul 2024, Gijon, France. pp.501-506, ⟨10.1109/NANO61778.2024.10628972⟩ |
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Testing spintronics implemented Monte Carlo dropout-based Bayesian neural networksETS 2024 - IEEE European Test Symposium, May 2024, La Haye, Netherlands. pp.1-6, ⟨10.1109/ETS61313.2024.10567852⟩ |
Enhancing Reliability of Neural Networks at the Edge: Inverted Normalization with Stochastic Affine Transformations2024 Design, Automation & Test in Europe Conference & Exhibition (DATE), IEEE, Mar 2024, Valencia (Espagne), Spain |
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Minimum SRAM Retention Voltage: Insight about optimizing Power Efficiency across Temperature Profile, Process Variation and Aging2023 IEEE 29th International Symposium on On-Line Testing and Robust System Design (IOLTS), IEEE, Jul 2023, Crete, Greece. pp.1-6, ⟨10.1109/IOLTS59296.2023.10224895⟩ |
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Leveraging sparsity with Spiking Recurrent Neural Networks for energy-efficient keyword spotting2023 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP 2023), Jun 2023, Ixia-Ialyssos, Greece. ⟨10.1109/ICASSP49357.2023.10097174⟩ |
Probabilistic Bitstream Generator based on Superparamagnetic Tunnel Junctions2023 IEEE 23rd International Conference on Nanotechnology (NANO), Jul 2023, Jeju City, South Korea. pp.638-642, ⟨10.1109/NANO58406.2023.10231253⟩ |
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Improving the Robustness of Neural Networks to Noisy Multi-Level Non-Volatile Memory-based Synapses2023 International Joint Conference on Neural Networks (IJCNN), Jun 2023, Gold Coast, Australia. pp.10.1109/IJCNN54540.2023.10191804, ⟨10.1109/IJCNN54540.2023.10191804⟩ |
Robustness and Power Efficiency in Spin-Orbit Torque-Based Probabilistic Logic Circuits2023 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), IEEE, Jun 2023, Foz do Iguacu, Brazil. pp.1-6, ⟨10.1109/ISVLSI59464.2023.10238682⟩ |
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A tunable 28nm FD-SOI crossbar output circuit forlow power analog SNN inference with eNVM synapsesEUROSOI-ULIS 2023, May 2023, Tarragona, Spain |
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Evaluating the Impact of Aging on Path-Delay Self-Test LibrariesIEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT 2023), Oct 2023, Juan-les-Pins, France. pp.1-7, ⟨10.1109/DFT59622.2023.10313531⟩ |
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Designing networks of resistively-coupled stochastic Magnetic Tunnel Junctions for energy-based optimum searchIEDM 2023 - 69th Annual IEEE International Electron Device Meeting, IEEE, Dec 2023, San Francisco, United States. pp.1-4, ⟨10.1109/IEDM45741.2023.10413843⟩ |
On Using Cell-Aware Methodology for SRAM Bit Cell TestingETS 2023 - 28th IEEE European Test Symposium, May 2023, Venezia, Italy. pp.1-4, ⟨10.1109/ETS56758.2023.10174118⟩ |
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Embedded Tutorial: Hardware design and Reliability Mitigation of Binary Bayesian Reasoning Speakers: Lorena Anghel (Grenoble INP) and Mehdi Tahoori (KIT)IEEE VLSI Test Symposium, IEEE, Apr 2023, San Diego (CA), United States |
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Scalable Spintronics-based Bayesian Neural Network for Uncertainty Estimation2023 Design, Automation & Test in Europe Conference & Exhibition (DATE), Apr 2023, Antwerp, Belgium. pp.1-6, ⟨10.23919/DATE56975.2023.10137167⟩ |
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Electrical Coupling of Perpendicular Superparamagnetic Tunnel Junctions for Probabilistic ComputingNANOARCH '22: 17th ACM International Symposium on Nanoscale Architectures, ACM, Dec 2022, Virtual OR USA, United States. pp.1-6, ⟨10.1145/3565478.3572528⟩ |
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Spin Orbit Torque-based Crossbar Array for Error Resilient Binary Convolutional Neural Network23RD IEEE LATIN-AMERICAN TEST SYMPOSIUM, Sep 2022, Montevideo, Uruguay |
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On Using Cell-Aware Models for Representing SRAM Architecture16e Colloque National du GDR SoC², Jun 2022, Strasbourg, France |
Improving DNN fault tolerance in semantic segmentation applicationsIEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), Oct 2022, Austin, United States. pp.1-6, ⟨10.1109/DFT56152.2022.9962354⟩ |
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Binary Bayesian Neural Networks for Efficient Uncertainty Estimation Leveraging Inherent Stochasticity of Spintronic Devices17th ACM International Symposium on Nanoscale Architectures, Association for Computing machinery, Dec 2022, Virtual conference, United States. ⟨10.1145/3565478.3572536⟩ |
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Zero-Overhead Protection for CNN Weights2021 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), Oct 2021, Athens (virtual), Greece. ⟨10.1109/DFT52944.2021.9568363⟩ |
Fast behavioral VerilogA compact model for stochastic MTJESSDERC 2021 - IEEE 51st European Solid-State Device Research Conference, Sep 2021, Grenoble, France. pp.259-262, ⟨10.1109/ESSDERC53440.2021.9631829⟩ |
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Ensemble neural networks with spintronic devices - Opportunities and challenges (KEYNOTE TALK)IEEE / ACM International Symposium on Nanoscale Architectures, Nov 2021, On line conference, France |
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Monitoring setup and hold timing limits2021 IEEE International Reliability Physics Symposium (IRPS), Mar 2021, Monterey, France. pp.1-6, ⟨10.1109/IRPS46558.2021.9405175⟩ |
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MOZART: Masking Outputs with Zeros for Architectural Robustness and Testing of DNN AcceleratorsIEEE International On-Line Testing Symposium, Jun 2021, OnLine, France |
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A Comprehensive End-to-end Solution for a Secure and Dynamic Mixed-signal 1687 System2020 International Symposium on On-Line Testing and Robust System Design (IOLTS 2020), Jul 2020, Naples (Virtual Conference), Italy. ⟨10.1109/IOLTS50870.2020.9159721⟩ |
State of the art in hardware-accelerated neural networksApplied Machine Learning Days (AMLD 2020), Jan 2020, Lausanne, Switzerland |
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From 1.8V to 0.19V voltage bias on analog spiking neuron in 28nm UTBB FD-SOI technologyEUROSOI-ULIS 2020, Sep 2020, Caen, France |
New Perspectives on Core In-field Path Delay TestInternational Test Conference (ITC 2020), Nov 2020, Washington DC, United States |
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Topology and design investigation on thin film silicon BIMOS device for ESD protection in FD-SOI technology30th European Symposium on Reliability of Electron Devices, Failure Physics and Analysis (ESREF'2019), Sep 2019, Toulouse, France |
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Managing Aging Induced Reliability at Run-time7th Workshop on Cross-layer Resiliency (IWCR'2019), Jul 2019, Stuttgart, Germany |
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Rebooting Computing: The Challenges for Test and Reliability2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), Oct 2019, Noordwijk, Netherlands. pp.8138-8143, ⟨10.1109/DFT.2019.8875270⟩ |
Neuromorphic Computing - From Robust Hardware Architectures to Testing Strategies26th IFIP IEEE International Conference on Very Large Scale Integration (VLSI SOC 2018), Oct 2018, Verona, Italy. pp.176-179, ⟨10.1109/VLSI-SoC.2018.8644897⟩ |
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Embedded Hardware Architectures for AIFrom Brain and Cognition to Artificial Intelligence Workshop, Jun 2019, Grenoble, France |
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Flexi-AES: A Highly-Parameterizable Cipher for a Wide Range of Design ConstraintsIEEE 27th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM'2019), Apr 2019, San Diego, United States |
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Hidden-Delay-Fault Sensor for Test, Reliability and SecurityIEEE Design Automation and Test Conference in Europe (DATE 2019), Mar 2019, Florence, Italy |
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Run-time Age Induced Reliability Prediction for SOCIEEE Latin America Test Symposium (LATS 2019), Mar 2019, Santiago de Chile, Chile |
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Special Session: Reliability of Hardware-Implemented Spiking Neural Networks (SNN)IEEE VLSI Test Symposium (VTS 2019), Apr 2019, Monterey, United States |
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Aging Investigation of Digital Circuits using In-Situ MonitorsIEEE International Integrated Reliability Workshop (IIRW 2019), Oct 2019, Stanford Sierra, Fallen Leaf Lake, United States |
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Neuromorphic CircuitsL’Intelligence Naturelle au cœur des enjeux de l’Intelligence Artificielle – Les atouts du site grenoblois, Jul 2018, Grenoble, France |
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Investigation of speed sensors accuracy for process and aging compensationIEEE International reliability Physics Symposium (IRPS'2018), Mar 2018, San Francisco, United States |
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Resistive and spintronic RAMs: device, simulation, and applicationsIOLTS 2018 - IEEE 24th International Symposium on On-Line Testing And Robust System Design, Jul 2018, Platja d'Aro, Spain. pp.109-114, ⟨10.1109/IOLTS.2018.8474226⟩ |
Integrated Synthesis Methodology for Crossbar ArraysIEEE NANOARCH'2018, Jul 2018, Athens, Greece |
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NBTI aged cell rejuvenation with back biasing and resulting critical path reordering for digital circuits in 28nm FDSOIDesign Automation and Test in Europe (DATE'2018), Mar 2018, Dresden, Germany |
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Reliability Analysis of MTJ-based Functional Module for Neuromorphic ComputingInternational Symposium on On-Line Testing and Robust System Design (IOLTS'17), Jun 2017, Thessaloniki, Greece |
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Fully-Connected Single-Layer STT-MTJ-based Spiking Neural Network under Process VariabilityACM/IEEE International Symposium on Nanoscale Architectures - NANOARCH, Jul 2017, Newport, RI, United States |
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Architecture and Workload Dependant Digital Failure RateIEEE International Reliability for Physics of Semiconductors (IRPS 2017), Apr 2017, Monterey, United States. ⟨10.1109/IRPS.2017.7936357⟩ |
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Investigation of critical path selection for in-situ monitors insertion23rd International Symposium on On-Line Testing and Robust System Design (IOLTS 2017), Jul 2017, Thessaloniki, Greece. pp.247-252 |
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Worload Dependent Reliability Timing Analysis FlowDATE 2017, Mar 2017, Lausanne, Switzerland |
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Test and reliability in approximate computingIMSTW: International Mixed-Signal Testing Workshop, Jul 2017, Thessaloniki, Greece. ⟨10.1109/IMS3TW.2017.7995210⟩ |
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A Hybrid Algorithm to Conservatively Check the Robustness of CircuitsIEEE European Test Symposium (ETS'16), May 2016, Amsterdam, Netherlands |
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Multi-context Non-volatile Content Addressable Memory Using Magnetic Tunnel Junctions12th ACM/IEEE International Symposium on Nanoscale Architectures (NANOARCH'16), Jul 2016, Beijing, China |
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Study of workload impact on BTI HCI induced aging of digital circuitsDesign Automation and Test in Europe (DATE'16), Mar 2016, Dresden, Germany |
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Managing Wear out and Variability Monitors: IEEE 1687 to the RescueEast West Design and test Symposium, Oct 2016, Yerevan, Armenia |
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In-Situ Slack Monitors : Taking up the Challenge of On-die Monitoring of Variability and ReliabilityInternational Verification and Security Workshop, Jul 2016, Sant Feliu de Guixols, Spain |
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System Failure Prediction with On-Chip MonitorsColloque National 2016 de GDR SOC-SIP, May 2016, Nantes, France |
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Moniteurs de fiabilité embarqués en technologie FDSOI: Implémentation et ApplicationsEcole d'hiver Francophone sur les Technologies de Conception des Systèmes Embarqués Hétérogènes (FETCH'16), Jan 2016, Vilard de Lans, France |
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Robustness of Timing in-situ Monitors for AVS ManagementIEEE International Reliability Physics Semiconductor (IRPS'16), Apr 2016, Passadena, United States |
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Early system failure prediction by using aging in situ monitors: Methodology of implementation and application resultsIEEE 34th VLSI Test Symposium (VTS'16), Apr 2016, Las Vegas, NE, United States |
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Paradigm shift in the level of Quality and Reliability in semiconductors to a level smaller than 10ppbAutomotive Reliability and Test Workshop, Nov 2016, Fort Worth, United States |
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Workload Impact on BTI HCI Induced Aging of Digital Circuits: A System level AnalysisWorkshop on Early Reliability Modeling for Aging and Variability in Silicon Systems, Mar 2016, Dresden, Germany |
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Early failure prediction by using in-situ monitors: Implementation and application resultsWorkshop on Early Reliability Modeling for Aging and Variability in Silicon Systems, Mar 2016, Dresden, Germany |
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Synthesis and Performance Optimization of a Switching Nano-crossbar ComputerEuromicro Conference on Digital System Design (Euromicro DSD/SEAA'16), Aug 2016, Limassol, Cyprus |
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Multi-context non-volatile content addressable memory using magnetic tunnel junctionsNanoarch, Jul 2016, Beijing, China |
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Application-independent testing of multilevel interconnect in mesh-based FPGAsIEEE 10th International Conference on Design and Technologies for Integrated System in Nanoscale (DTIS'15), Apr 2015, Naples, Italy. pp.1-6 |
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Timing in-situ monitors: Implementation strategy and applications resultsIEEE Custom Integrated Circuits Conference (ICICC'16), Sep 2015, San Jose, CA, United States |
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Reliability Measurements with In Situ Aging Monitors in FDSOI TechnologyInternational Test Conference (ITC'15), Oct 2015, Anaheim, United States |
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Impact of Gate Oxide Breakdown in Logic Gates from 28nm FDSOI CMOS technologyIEEE International Reliability Physics Symposium (IRPS'15), Apr 2015, Monterrey, CA, United States. pp.CA.4.1 - CA.4.6 |
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Digital circuits reliability with in-situ monitors in 28nm fully depleted SOIDesign, Automation & Test in Europe Conference & Exhibition (DATE'15), Mar 2015, Grenoble, France. pp.441-446 |
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Efficient Fault-Tolerant Adaptive Routing under an unconstrained Set of Node and Link Failures for Many Cores System On ChipWorkshop on Dependable Multicore and Transactional Memory Systems (DMTM'14), (joint to HIPEAC event), Jan 2014, Vienna, Austria. pp.1-2 |
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Impact of Cluster Size on Routability, Testability and Robustness of a Cluster in a Mesh FPGAIEEE Computer Society Annual Symposium on VLSI (ISVLSI'14), Jul 2014, Tampa, FL, United States. pp.553-558, ⟨10.1109/ISVLSI.2014.66⟩ |
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New Approaches in Soft Errors Fault Tolerant Design for digital circuits based on Double Sampling TechniquesEcole d'hiver Francophone sur les Technologies de Conception des Systèmes embarqués Hétérogènes (FETCH 2014), Jan 2014, Ottawa, Canada |
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Cost-efficient of a cluster in a mesh SRAM-based FPGAIEEE 20th International On-Line Testing Symposium (IOLTS'14), Jul 2014, Platja d'Aro, Girona, Spain. pp.75-80 |
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Single Event Effects in Muller C-Elements and Asynchronous Circuits Over a Wide Energy SpectrumThe 10th IEEE Workshop on Silicon Errors in Logic - System Effects (SELSE'14), Apr 2014, Stanford, United States |
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New Insight about Oxide Breakdown Occurrence at Circuit LevelIEEE International Reliability Physics Symposium (IRPS'14), Jun 2014, Waikoloa, HI, United States |
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Exploring the state dependent SET sensitivity of asynchronous logic - The muller-pipeline example32nd IEEE International Conference on Computer Design (ICCD'14), Oct 2014, Seoul, North Korea. pp.61-67 |
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Fault-tolerant adaptive routing under permanent and temporary failures for many-core systems-on-chipIEEE International On-Line Testing symposium (IOLTS'13), Jul 2013, Chania, Crete, France. pp.7-12, ⟨10.1109/IOLTS.2013.6604043⟩ |
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BIST for Logic and Local Interconnect Resources in a Novel Mesh of Cluster FPGAIEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), Oct 2013, New-York, United States. pp.296 - 301, ⟨10.1109/DFT.2013.6653622⟩ |
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Efficient link-level error resilience in 3D NoCsIEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS'12), Apr 2012, Tallinn, Estonia. pp.127-132, ⟨10.1109/DDECS.2012.6219038⟩ |
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On the Dependability of 3D InterconnectsEcole d'hiver Francophone sur les Technologies de Conception des Systèmes embarqués Hétérogènes (FETCH'12), Jan 2012, Alpes d'Huez, France |
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Designing Single Chip Massively Parallel Processors Affected by Extreme Failure RatesDesign, Automation & Test in Europe Conference & Exhibition (DATE'12), Mar 2012, Dresden, Germany |
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Towards Low-cost Soft Error Mitigation in SRAM-based FPGAs: a Case Study on AT40K3rd IEEE Latin American Symposium on Circuits and Systems (LASCAS'12), Feb 2012, Playa del Carmen, Mexico |
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A predictive bottom-up hierarchical approach to digital system reliabilityIEEE International Reliability Physics Symposium (IRPS'12), Apr 2012, Anaheim, CA, United States. pp.4B.1.1 - 4B.1.10, ⟨10.1109/IRPS.2012.6241830⟩ |
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Electromigration degradation mechanism analysis of SnAgCu interconnects for eWLB packageIEEE International Reliability Physics Symposium (IRPS'12), Apr 2012, Anaheim, CA, United States. pp.2E.5.1 - 2E.5.6, ⟨10.1109/IRPS.2012.6241792⟩ |
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Through-Silicon-Via Built-In Self-Repair for Aggressive 3D IntegrationIEEE 18th International On-Line Testing Symposium (IOLTS), Jun 2012, Sitges, Spain. pp.91-96, ⟨10.1109/IOLTS.2012.6313847⟩ |
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Electromigration Behavior of 3D-IC TSV Interconnects62nd Electronic Components and Technology Conference (ECTC'12), May 2012, San Diego, CA, United States. pp.326 - 330 |
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Design for Test and Reliability in Ultimate CMOSDesign, Automation and Test in Europe (DATE'12), Mar 2012, Dresden, Germany. pp.677-682 |
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Bottom-up digital system-level reliability modelingCustom Integrated Circuits Conference (CICC'11), Sep 2011, San Jose, Ca., United States. pp.1 - 4, ⟨10.1109/CICC.2011.6055343⟩ |
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Memory BIST with address programmabilityIEEE international On Line Testing Symposium (IOLT'11), Jul 2011, Athenes, Greece. pp.79 - 85, ⟨10.1109/IOLTS.2011.5993815⟩ |
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On the Dependability of 3D InterconnectsDependability Issues in Deep-submicron Technologies Workshop (DDT'11), May 2011, Trondheim, Norway |
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Resistance Increase Due to Electromigration Induced Depletion Under TSVIEEE International Reliability Physics Symposium (IRPS'11), Monterey, CA, USA, April 10-14, Apr 2011, Monterey, ca., United States. pp.3F.4.1 - 3F.4.6, ⟨10.1109/IRPS.2011.5784499⟩ |
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I-BIRAS: Interconnect Built-In Self-Repair and Adaptive Serialization in 3D Integrated Systems16th IEEE European Test Symposium (ETS'11), May 2011, Trondheim, Norway. pp.208 - 208, ⟨10.1109/ETS.2011.37⟩ |
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Electromigration Behavior of 3D-IC TSVSecond IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits (3D IC), in conjuction with ITC, Sep 2011, Anaheim, United States |
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Efficient Fault Detection Architecture Design of Latch-Based Low Power DSP/MCU Processor16th IEEE European Test Symposium (ETS'11), May 2011, Trondheim, Norway. pp.93 - 98, ⟨10.1109/ETS.2011.20⟩ |
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Analysis of configuration bit criticality in designs implemented with SRAM-based FPGAsIEEE Symposium on Industrial Electronics & Applications (ISIEA'11), Sep 2011, Langkawi, Malaysia. pp.83-88 |
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Criticality of Configuration Bits in SRAM-based FPGAs: Predictive Analysis and Experimental ResultsWorkshop on Design for Reliability and Variability (DRVW'11), May 2011, Dana Point, CA, United States |
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Designing cost-effective robust systems by accurate reliability modelingIEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT'11), Oct 2011, Vancouver, Canada |
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Configurable Thru-Silicon-Via interconnect Built-In Self-Test and diagnosisIEEE Latin America Test Symposium Workshop (LATW'11), Mar 2011, Porto de Galinhas (PE), Brazil. pp.1-6, ⟨10.1109/LATW.2011.5985896⟩ |
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Non-regular 3D mesh Networks-on-ChipDAC Workshop on Diagnostic Services in Network-on-Chips (DSNoC'10), Jun 2010, Anaheim, United States |
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Fault Tolerant Communication in 3D Integrated SystemsDSN Workshop on Dependable Systems and Networks (WDSN'10), Jun 2010, Chicago, United States. pp.131-135 |
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Checkpoint and rollback recovery in network-on-chip based systemsStudent forum at 15th Asia and South Pacific Design Automation Conference (ASP-DAC'10), Jan 2010, Taipei, Taiwan |
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Interconnect Built-In Self-Repair and Adaptive-Serialization (I-BIRAS) for 3D integrated systemsIEEE International On-Line Testing Symposium (IOLTS'10), Jul 2010, Corfu, Greece. pp.218 - 218, ⟨10.1109/IOLTS.2010.5560198⟩ |
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Reliability approach of high density Through Silicon Via (TSV)12th Electronics Packaging Technology Conference (EPTC'10), Dec 2010, Singapore, Singapore. pp.321 - 324, ⟨10.1109/EPTC.2010.5702655⟩ |
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Configurable Serial Fault-Tolerant Link for Communication in 3D Integrated SystemsInternational On-Line Test Symposium (IOLTS'10), Jul 2010, Corfu, Greece. pp.115-120 |
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I-BIRAS: « Interconnect Built-In Self-Repair and Adaptive-SerializationInternational Test Conference Workshop on Test of 3D Stacked Systems (3D-TEST), Nov 2010, Austin, TX, United States |
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Technology roadmap and evolutions: challenge and criticalityRADPRED Workshop, Jan 2010, Toulouse, France |
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Configurable Fault-Tolerant Link for Inter-die Communication in 3D on-Chip NetworksEuropean Test Symposium (ETS'10), May 2010, Prague, Czech Republic. pp.258 |
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Fault Resilient Intra-die and Inter-die Communication in 3D Integrated SystemsPhD Research in Microelectronics and Electronics Conference, PRIME 2010, May 2010, Berlin, Germany |
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RILM: Reconfigurable inter-layer routing mechanism for 3D multi-layer networks-on-chipInternational On-Line Test Symposium (IOLTS'10), Jul 2010, Corfu, Greece. pp.121-125 |
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Error Resilience of Inter-Die and Intra-Die Communication with 3D Spidergon STNoCDesign Automation and Test in Europe Conference, (DATE'10), Mar 2010, Dresden, Germany. pp.275-278 |
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A methodology and tool for predictive analysis of configuration bit criticality in SRAM-based FPGAs: experimental results3rd International Conference on Signals, Circuits & Systems (SCS), Nov 2009, Djerba, Tunisia |
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Message routing in 3D networks-on-chipNORCHIP Conference 2009, Nov 2009, Trondheim, Norway |
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Predictive analysis of configuration bit criticality in SRAM-based FPGAs – Methodology, tools, and results3ème Colloque du GdR SoC-SiP, Jun 2009, Paris, France |
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Multi-level Fault Tolerance in 2D and 3D NoCsWorkshop international “NOC in Space Applications Round Table”, European Space Agency, Sep 2009, Noordwijk, Netherlands |
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An Effective Approach to Detect Logic Soft Errors in Digital Circuits Based on GRAAL10th International Symposium on Quality of Electronic Design (ISQED'09), Mar 2009, San Jose, CA, United States. pp.236-240, ⟨10.1109/ISQED.2009.4810300⟩ |
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Network-on-Chip Fault Tolerance through Checkpoint and Rollback RecoveryNational Symposium on System-on-Chip - System-in-Package (GdR SoC-SiP'08),, Jun 2008, Paris, France |
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Improving the Scalability of Checkpoint Recovery for Networks-on-ChipIEEE International Symposium on Circuits and Systems (ISCAS'08), Seattle, May 2008, Washington, United States. pp.2793-2796, ⟨10.1109/ISCAS.2008.4542037⟩ |
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Initiation à la conception de VLSI numériques10èmes journées pédagogiques CNFM, Nov 2008, Saint-Malo, France |
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Blocking and Non-blocking Checkpointing for Networks-on-Chip2nd IEEE Workshop on Dependable and Secure Nanocomputing (WDSN'08), Jun 2008, Anchorage, Alaska, United States |
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An Analysis and Design Technique to Reduce SET Sensitivity in Combinational Integrated Circuits16th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-Soc'08), Oct 2008, Rhodes Island, Greece. pp.114-117 |
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A flexible network-on-chip simulator for early design space exploration1st Microsystems and Nanoelectronics Research Conference (MNRC 2008), Oct 2008, Ottawa, Canada. pp.33-36, ⟨10.1109/MNRC.2008.4683371⟩ |
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Coordinated versus Uncoordinated Checkpoint Recovery for Network-on-Chip based Systems4th IEEE International Symposium on Electronic Design, Test and Applications (DELTA'08), Jan 2008, Hong Kong, China. pp.32-37, ⟨10.1109/DELTA.2008.75⟩ |
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Structures robustes pour circuits logiques à base de CNTFET11ème Journées Nationales du Réseau Doctoral en Microélectronique (JNRDM'08), May 2008, Bordeaux, France. pp.66 |
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SET-Factor: An Analysis and Design Tool to Reduce SET Sensitivity in Integrated Circuits13th IEEE European Test Symposium (ETS'08), May 2008, Verbania, Italy |
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Communication Aware Recovery Configurations for Networks-on-Chip14th IEEE International Symposium On-Line Testing (IOLT'08), Jul 2008, Rhodes, Greece. pp.201-206, ⟨10.1109/IOLTS.2008.44⟩ |
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Efficient Coordinated Checkpointing Recovery Schemes for Network-on-Chip based Systems2nd International Workshop on Dependable Circuit Design (DECIDE'08), Nov 2008, Playa del Carmen, Mexico, Mexico |
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Efficient Timing Closure with a Transistor Level Design FlowIFIP International Conference on Very Large Scale Integration (VLSI-SoC'07), Oct 2007, Atlanta, GA, United States. pp.312-315 |
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CNTFET-based CMOS-like gates and dispersion of characteristicsInternational Design and Test Workshop (IDT'07), Dec 2007, Cairo, Egypt. pp.151-156 |
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CNTFET-based logic gates and characteristicsSilicon Nanoelectronics Workshop (SNW'07), Jun 2007, Kyoto, Japan. pp.2 |
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Defects Tolerant Logic Gates for Unreliable Future NanotechnologiesSpecial Session of International Work-Conference on Artificial Neural Networks (IWANN'07), Jun 2007, San Sebastian, Spain |
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SET fault injection methods in analog circuits: case study8th Latin-American Test Workshop (LATW'07), Mar 2007, Cuzco, Peru. pp.155-160 |
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Multiple Event Transient Induced by Nuclear Reactions in CMOS Logic Cells13th IEEE International On-Line Testing symposium (IOLT'07), Jul 2007, Crete, Greece. pp.137-145, ⟨10.1109/IOLTS.2007.46⟩ |
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Efficient Transistor Sizing for Soft Error Protection in Combinational Logic Circuits2nd International Workshop on Dependable Circuit Design (DECIDE’07), Dec 2007, Buenos Aires, Argentina |
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Essential Fault-Tolerance Metrics for NoC InfrastructuresIEEE International On-Line Test Symposium (IOLT'07), Jul 2007, Crete, Greece. pp.37-42, ⟨10.1109/IOLTS.2007.31⟩ |
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Tools and methodology development for pulsed laser fault injection in SRAM-based FPGAs8th Latin-American Test Workshop (LATW'07), 2007, Cuzco, Peru. pp.Session 8 |
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Defect Tolerant Logic Gates for Unreliable Future NanotechnologiesInternational Conference on Artificial Neural Networks (IWANN), Jun 2007, San Sebastian, Spain. pp.422-429, ⟨10.1007/978-3-540-73007-1⟩ |
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SET and SEU effects at multiple abstraction levelsSingle Event Effects Symposium (SEE'06), Jun 2006, Long Beach, CA,, United States |
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CNTFET basics and simulationDesign and Test of Integrated Systems (DTIS'06), 2006, Tunis, Tunisia. pp.28-33 |
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Multiple Defects Tolerant Devices for Unreliable Future NanotechnologiesIEEE Latin American Test Workshop (LATW'06), Mar 2006, Buenos Aires, Argentina |
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Prediction of transients induced by neutrons/protons in CMOS combinational logic cells12th IEEE International On-Line Testing Symposium (IOLTS'06), 2006, Lake Como, Italy. 9 pp., ⟨10.1109/IOLTS.2006.51⟩ |
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Phase-Locked Loop Automatic Layout Generation and Transient Fault Injection Analysis: A Case Study12th IEEE International On-Line Testing Symposium (IOLTS'06), 2006, Lake Como, Italy. pp.165-172, ⟨10.1109/IOLTS.2006.48⟩ |
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CNTFET-based logic gates and simulationIEEE International Design and Test Workshop (IDT'06, Nov 2006, Dubai, United Arab Emirates. 6 p |
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On implementing a soft error hardening technique by using an automatic layout generator: case study11th-IEEE-International-On-Line-Testing-Symposium., 2005, French Riviera, France. pp.29-34, ⟨10.1109/IOLTS.2005.45⟩ |
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Transient and permanent fault tolerance memory cells for unreliable future nanotechnologiesIEEE Latin American Test Workshop (LATW'05), Mar 2005, Salvador Bahia, Brazil. pp.187-192 |
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Soft error circuit hardening techniques implementation using an automatic layout generatorProceedings of IEEE Latin American Test Workshop (LATW'05), Mar 2005, Salvador Bahia, Brazil. pp.175-180 |
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Evaluation of SET and SEU effects at multiple abstraction levels11th-IEEE-International-On-Line-Testing-Symposium., 2005, French Riviera, France. pp.309-12, ⟨10.1109/IOLTS.2005.28⟩ |
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Simulation and mitigation of single event effects11th-IEEE-International-On-Line-Testing-Symposium, 2005, French Riviera, France. pp.81, ⟨10.1109/IOLTS.2005.65⟩ |
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A Diversified Memory Built-In Self-Repair Approach for Nanotechnologies22nd IEEE VLSI Test Symposium, 2004, Napa Valley, United States. pp.313, ⟨10.1109/VTEST.2004.1299258⟩ |
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Evaluation of Memory Built-in Self Repair Techniques for High Defect Density Technologies10th IEEE Pacific Rim International Symposium on Dependable Computing (PRDC'04), 2004, Tahiti, Papeete French Polynesia, France. pp.315-320, ⟨10.1109/PRDC.2004.1276581⟩ |
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Coupling Different Methodologies to Validate Obsolete Microprocessors19th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'04), 2004, Cannes, France. pp.250-255, ⟨10.1109/DFT.2004.21⟩ |
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A Memory Built-In Self-Repair for High Defect Densities Based on Error Polarities18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'03), 2003, Boston, Cambridge, Ma,, United States. pp.459, ⟨10.1109/DFTVS.2003.1250144⟩ |
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Preliminary Validation of an Approach Dealing with Processor Obsolescence18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'03), 2003, Boston, Cambridge, Ma, United States. pp.493, ⟨10.1109/DFTVS.2003.1250148⟩ |
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Memory Built-In Self-Repair for Nanotechnologies9th IEEE International On-Line Testing Symposium, 2003, Kos International Convention Center, Kos Island, Greece. pp.94-8, ⟨10.1109/OLT.2003.1214373⟩ |
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A Methodology for Test Replacement Solutions of Obsolete Processors9th IEEE International On-Line Testing Symposium, 2003, Kos International Convention Center, Kos Island, Greece. pp.209, ⟨10.1109/OLT.2003.1214400⟩ |
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New methods for evaluating the impact of single event transients in VDSM ICsProceedings-17th-IEEE-International-Symposium-on-Defect-and-Fault-Tolerance-in-VLSI-Systems.-DFT-2002, 2002, Vancouver, BC, Canada. pp.99-107, ⟨10.1109/DFTVS.2002.1173506⟩ |
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Simulating single event transients in DVSM ICs for ground level radiation3rd IEEE Latin American Test Workshop (LATW'02), Feb 2002, Montevideo, Uruguay |
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Self-checking circuits versus realistic faults in very deep submicronProceedings-18th-IEEE-VLSI-Test-Symposium, 2000, Montreal, Que., Canada. pp.55-63, ⟨10.1109/VTEST.2000.843827⟩ |
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Cost reduction and evaluation of a temporary faults detecting techniqueProceedings-Design,-Automation-and-Test-in-Europe-Conference-and-Exhibition-2000-Cat.-No.-PR00537, 2000, Paris, France. pp.591-8, ⟨10.1109/DATE.2000.840845⟩ |
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Evaluation of a Soft Error Tolerance Technique Based on Time and/or Space Redundancy13th Symposium on Integrated Circuits and Systems Design (SBCCI'00), 2000, Manaus, Amazonas, Brazil. pp.237-42, ⟨10.1109/SBCCI.2000.876036⟩ |
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Concurrent Checking for VLSIThird session on Reliability in VLSI circuits: operation, manufacturing and design: operation, manufacturing and design, Jun 1999, Austrans, France. pp.139 - 156 |
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Built-In Current Sensor for IDDQ Testing in Deep Submicron CMOS17TH IEEE VLSI Test Symposium, 1999, Dana Point, California, United States. pp.135-42, ⟨10.1109/VTEST.1999.766657⟩ |
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Implementation and evaluation of a soft error detecting techniqueThe 5th IEEE International On-Line Testing Workshop (IOLTW'99), Jul 1999, Rhodes, Grèce |
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Asynchronous Current Monitors for Transient Fault Detection in Deep Submicron CMOS4th IEEE International On-Line Testing Workshop (IOLTW'98), Jul 1998, Capri, Italy |
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Experimental investigation of noise sources in silicon carbide Schottky barriers1996-International-Semiconductor-Conference.-19th-Edition.-CAS-'96-Proceedings-Cat.-No.96TH8170, 1996, Sinaia, Romania. pp.539-42 vol.2, ⟨10.1109/SMICND.1996.557436⟩ |
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Method to increase the switching speed of MOS transistors by dynamic bias of the bulk1995-International-Semiconductor-Conference.-CAS'95-Proceedings-Cat.-No.95TH8071, 1995, Sinaia, France. pp.241-4, ⟨10.1109/SMICND.1995.494907⟩ |
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Study and design of MRAM-based in-memory computing architectures for machine learning applicationsJournées Scientifiques Nationales 2024 du PEPR Électronique, Mar 2024, Grenoble, France |
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In-memory-computing implementation of magnetoresistive networks for ultra-low-power computingJournées Scientifiques Nationales 2024 du PEPR électronique, Mar 2024, Grenoble, France. |
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Towards Low-Power Embedded ECoG DecodingGDR SoC2, Jun 2023, Lyon, France. 2023 |
Cost-efficient Testing of LUT and Intra-cluster Interconnect of a Novel SRAM-based FPGAColloque National System-On-Chip System-In-Package (SoC-SiP'13), Jun 2013, Lyon, France. 2013, Colloque National System-On-Chip System-In-Package (SoC-SiP'13) |
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EditorialElsevier, 38 (6), pp.565 - 566, 2014, Microprocessors and Microsystems, ⟨10.1016/j.micpro.2014.07.003⟩ |
Proceedings of 11th IEEE International On-Line Testing Symposium (IOLT 2005)Saint Raphael, French Riviera, France, July 6-8, 2005IEEE, 330 p., 2005 |
Design techniques to improve the resilience of computing systems: logic layerCross-Layer Reliability of Computing Systems, iet - the institution of engineering and technology, pp.23-42, 2020 |
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On-Chip Ageing Monitoring and System AdaptationAgeing of Integrated Circuits: Causes, Effects and Mitigation TechniquesOn-Chip Ageing Monitoring and System Adaptation, pp.149-180, 2019, 978-3-030-23780-6. ⟨10.1007/978-3-030-23781-3_6⟩ |
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Manufacturing ThreatsDependable Multicore Architectures at Nanoscale, springer, pp.3-35, 2017, 978-3-319-54421-2. ⟨10.1007/978-3-319-54422-9⟩ |
Adaptive Routing for Fault Tolerance and Congestion Avoidance for 2D Mesh and Torus NoCs in Many-Core Systems-on-ChipAdvances in Microelectronics: Reviews, ifsa, international frequency sensor association, pp.405-435, 2017, 978-84-615-9012-4 |
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A Transistor Placement Technique Using Genetic Algorithm And Analytical ProgrammingVLSI-SOC: From Systems to Silicon, (selected contributions from VLSI-SoC'05), Springer, pp.331-344, Vol.240, 2007, Series: IFIP International Federation for Information Processing, ⟨10.1007/978-0-387-73661-7_21⟩ |
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Defects Tolerant Logic Gates for Unreliable Future NanotechnologiesComputational and Ambient Intelligence, Springer, pp.422-429, 2007, ISBN :978-3-540-73006-4, ⟨10.1007/978-3-540-73007-1_52⟩ |
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Cost Reduction and Evaluation of a Temporary Faults Detecting TechniqueRudy Lauwereins and Jan Madsen. Design, Automation, and Test in Europe (DATE) “The Most Influential Papers of 10 Years”, Springer, pp.423-438, 2007, ISBN :978-1-4020-6487-6, ⟨10.1007/978-1-4020-6488-3_31⟩ |
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Multilevel Fault Effects EvaluationRAOUL VELAZCO, PASCAL FOUILLAT and RICARDO REIS. Radiation Effects on Embedded Systems, Springer, pp.69-88, 2007, ISBN :978-1-4020-5645-1, ⟨10.1007/978-1-4020-5646-8⟩ |
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Les limites technologiques du silicium et tolérance aux fautesAutre [cs.OH]. Institut National Polytechnique de Grenoble - INPG, 2001. Français. ⟨NNT : ⟩ |
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Conception Robuste dans les Technologies CMOS et post-CMOSMicro et nanotechnologies/Microélectronique. Institut National Polytechnique de Grenoble - INPG, 2007 |