Marie-Lise Flottes
Présentation
Publications
Publications
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Power Analysis Attack Against post-SAT Logic Locking schemesETS 2024 - 29th IEEE European Test Symposium, May 2024, The Hague, Netherlands. pp.1-6, ⟨10.1109/ETS61313.2024.10567311⟩ |
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Logic Locking: Exploration of a new key-gate based on tristate logicLATS 2024 - 25th IEEE Latin American Test Symposium, Apr 2024, Maceio, Brazil. pp.1-6, ⟨10.1109/LATS62223.2024.10534598⟩ |
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A Novel March Test Algorithm for Testing 8T SRAM-based IMC ArchitecturesDATE 2024 - 27th Design, Automation & Test in Europe Conference & Exhibition, Mar 2024, Valence, Spain. pp.1-6, ⟨10.23919/DATE58400.2024.10546583⟩ |
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Intra-cell Resistive-Open Defect Analysis on a Foundry 8T SRAM-based IMC ArchitectureETS 2023 - 28th IEEE European Test Symposium, May 2023, Venise, Italy. pp.1-4, ⟨10.1109/ETS56758.2023.10174107⟩ |
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Analysis of Resistive-Open Defects on a Foundry 8T SRAM-based IMC Architecture17e Colloque National du GDR SoC², Jun 2023, Lyon, France |
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Resynthesis-based Attacks Against Logic LockingISQED 2023 - 24th International Symposium on Quality Electronic Design, Apr 2023, San Fransisco, CA, United States. pp.1-8, ⟨10.1109/ISQED57927.2023.10129403⟩ |
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Analysis of Read Port Short Defects in an 8T SRAM-based IMC Architecture16e Colloque National du GDR SoC², Jun 2022, Strasbourg, France |
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A new key-gate insertion strategy for logic locking with high output corruptionTHCon 2022 - Toulouse Hacking Convention, ENAC, Apr 2022, Toulouse, France |
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Leveraging Layout-based Effects for Locking Analog ICsASHES 2022 - 6th Workshop on Attacks and Solutions in Hardware Security @CCS 2022, Nov 2022, Los Angeles, CA, United States. pp.5-13, ⟨10.1145/3560834.3563826⟩ |
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A Lightweight, Plug-and-Play and Autonomous JTAG Authentication IP for Secure Device TestingETS 2022 - 27th IEEE European Test Symposium, May 2022, Barcelona, Spain. pp.1-4, ⟨10.1109/ETS54262.2022.9810364⟩ |
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Preliminary Defect Analysis of 8T SRAM Cells for In-Memory Computing ArchitecturesDTIS 2021 - 16th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, Jun 2021, Montpellier, France. ⟨10.1109/DTIS53253.2021.9505101⟩ |
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Preliminary Defect Analysis of 8T SRAM Cells Used for In-Memory Computing15e Colloque National du GDR SoC², Jun 2021, Rennes, France |
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High-level Intellectual Property Obfuscation via Decoy ConstantsIOLTS 2021 - 27th IEEE International Symposium on On-Line Testing and Robust System Design, Jun 2021, Torino, Italy. pp.1-7, ⟨10.1109/IOLTS52814.2021.9486714⟩ |
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On Preventing SAT Attack with Decoy Key-InputsISVLSI 2021 - IEEE Computer Society Annual Symposium on VLSI, Jul 2021, Tampa, United States. pp.114-119, ⟨10.1109/ISVLSI51109.2021.00031⟩ |
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A Plug and Play Digital ABIST Controller for Analog Sensors in Secure DevicesETS 2021 - 26th IEEE European Test Symposium, May 2021, Bruges, Belgium. pp.1-4, ⟨10.1109/ETS50041.2021.9465480⟩ |
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Logic Locking a Design-for-Trust IC Design TechniqueFETCH 2020 - École d'hiver Francophone sur les Technologies de Conception des Systèmes Embarqués Hétérogènes, Feb 2020, Montréal, Canada |
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A Secure Scan Controller for Protecting Logic LockingIOLTS 2020 - 26th IEEE International Symposium on On-Line Testing and Robust System Design, Jul 2020, Napoli, Italy. pp.1-6, ⟨10.1109/IOLTS50870.2020.9159730⟩ |
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Development and Application of Embedded Test Instruments to Digital, Analog/RFs and Secure ICsIOLTS 2020 - 26th IEEE International Symposium on On-Line Testing and Robust System Design, Jul 2020, Napoli, Italy. pp.1-4, ⟨10.1109/IOLTS50870.2020.9159723⟩ |
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Stream Cipher Based Encryption in IEEE Test StandardsTRUDEVICE 2019 - 8th Workshop on Trustworthy Manufacturing and Utilization of Secure Devices, May 2019, Baden Baden, Germany |
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A Comprehensive Approach to a Trusted Test InfrastructureIVSW 2019 - 4th IEEE International Verification and Security Workshop, Jul 2019, Rhodes, Greece. pp.43-48, ⟨10.1109/IVSW.2019.8854428⟩ |
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Encryption-Based Secure JTAGDDECS 2019 - 22nd International Symposium on Design and Diagnostics of Electronic Circuits and Systems, Apr 2019, Cluj-Napoca, Romania. pp.1-6, ⟨10.1109/DDECS.2019.8724654⟩ |
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Providing Confidentiality and Integrity in Ultra Low Power IoT DevicesDTIS 2019 - 14th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, Apr 2019, Mykonos, Greece. ⟨10.1109/DTIS.2019.8735090⟩ |
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A new secure stream cipher for scan chain encryption3rd IEEE International Verification and Security Workshop (IVSW 2018), Jul 2018, Platja d’Aro, Spain. pp.68-73, ⟨10.1109/IVSW.2018.8494852⟩ |
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Laser fault injection at the CMOS 28 nm technology node: an analysis of the fault modelFDTC: Fault Diagnosis and Tolerance in Cryptography, Sep 2018, Amsterdam, Netherlands. pp.1-6, ⟨10.1109/FDTC.2018.00009⟩ |
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Does stream cipher-based scan chains encryption really prevent scan attacks?TRUDEVICE Workshop, Mar 2018, Dresden, Germany |
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The case of using CMOS FD-SOI rather than CMOS bulk to harden ICs against laser attacksIOLTS: International On-Line Testing Symposium, Jul 2018, Platja d’Aro, Spain. pp.214-219, ⟨10.1109/IOLTS.2018.8474230⟩ |
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Encryption of test data: which cipher is better?PRIME: PhD Research in Microelectronics and Electronics, Jul 2018, Prague, Czech Republic. pp.85-88, ⟨10.1109/PRIME.2018.8430366⟩ |
Assessing Body Built-In Current Sensors for Detection of Multiple Transient FaultsESREF 2018 - European Symposium on Reliability of Electron Devices, Failure Physics and Analysis, Oct 2018, Aalborg, Denmark |
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SI ECCS: SECure context saving for IoT devicesDTIS 2018 - 13th International Conference on Design and Technology of Integrated Systems in Nanoscale Era, Apr 2018, Taormina, Italy. ⟨10.1109/DTIS.2018.8368561⟩ |
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Scan Chain EncryptionDOCTIS: Journée des Doctorants de l’école doctorale I2S, 2017, Montpellier, France |
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Experimentations on scan chain encryption with PRESENTIVSW: International Verification and Security Workshop, Jul 2017, Thessaloniki, Greece. pp.45-50, ⟨10.1109/IVSW.2017.8031543⟩ |
Hacking the Control Flow error detection mechanismIVSW: International Verification and Security Workshop, Jul 2017, Thessaloniki, Greece. pp.51-56, ⟨10.1109/IVSW.2017.8031544⟩ |
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Scan chain encryption for the test, diagnosis and debug of secure circuitsETS: European Test Symposium, May 2017, Limassol, Cyprus. ⟨10.1109/ETS.2017.7968248⟩ |
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Using Outliers to Detect Stealthy Hardware Trojan Triggering?IVSW: International Verification and Security Workshop, Jul 2016, Sant Feliu de Guixols, France |
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Duplication-based Concurrent Detection of Hardware Trojans in Integrated CircuitsTRUDEVICE, Nov 2016, Barcelona, Spain |
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Hardware Trust through Layout Filling: a Hardware Trojan Prevention TechniqueISVLSI: International Symposium on Very Large Scale Integration, Jul 2016, Pittsburgh, United States. pp.254-259, ⟨10.1109/ISVLSI.2016.22⟩ |
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New Testing Procedure for Finding Insertion Sites of Stealthy Hardware TrojansDATE 2015 - 18th Design, Automation and Test in Europe Conference and Exhibition, Mar 2015, Grenoble, France. pp.776-781, ⟨10.7873/DATE.2015.1102⟩ |
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On the limitations of logic testing for detecting Hardware Trojans HorsesDTIS: Design and Technology of Integrated Systems in Nanoscale Era, Apr 2015, Naples, Italy. ⟨10.1109/DTIS.2015.7127362⟩ |
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3D DFT Challenges and SolutionsISVLSI: International Symposium on Very Large Scale Integration, Jul 2015, Montpellier, France. pp.603-608, ⟨10.1109/ISVLSI.2015.11⟩ |
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Hardware Trojan Prevention using Layout-Level Design ApproachECCTD: European Conference on Circuit Theory and Design, Aug 2015, Trondheim, Norway. ⟨10.1109/ECCTD.2015.7300093⟩ |
Session-less based thermal-aware 3D-SIC test schedulingETS: European Test Symposium, May 2015, Cluj-Napoca, Romania. ⟨10.1109/ETS.2015.7138732⟩ |
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Laser-Induced Fault Effects in Security-Dedicated CircuitsVLSI-SoC: Very Large Scale Integration and System-on-Chip, Oct 2014, Playa del Carmen, Mexico. pp.220-240, ⟨10.1007/978-3-319-25279-7_12⟩ |
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Figure of merits of 28nm Si technologies for implementing laser attack resistant security dedicated circuitsISVLSI: International Symposium on Very Large Scale Integration, Jul 2015, Montpellier, France. pp.362-367, ⟨10.1109/ISVLSI.2015.76⟩ |
Sensitivity to fault laser injection: a comparison between 28nm bulk and FD-SOI technologyTRUDEVICE Workshop, Sep 2015, Saint-Malo, France |
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Validation Of Single BBICS Architecture In Detecting Multiple FaultsATS: Asian Test Symposium, Nov 2015, Mumbai, India |
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Multi-segment Enhanced Scan-chains for Secure ICsTRUDEVICE Workshop, Sep 2015, Saint-Malo, France |
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Hierarchical Secure DfTTRUDEVICE Workshop, Sep 2015, St Malo, France |
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A Novel Hardware Logic Encryption Technique for thwarting Illegal Overproduction and Hardware TrojansIOLTS: International On-Line Testing Symposium, Jul 2014, Platja d'Aro, Girona, Spain. pp.49-54, ⟨10.1109/IOLTS.2014.6873671⟩ |
Layout-Aware Laser Fault Injection Simulation and Modeling: from physical level to gate levelDTIS: Design and Technology of Integrated Systems in Nanoscale Era, May 2014, Santorin, Greece. ⟨10.1109/DTIS.2014.6850665⟩ |
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Design of Bulk Built-In Current Sensors to Detect Single Event Effects and Laser-Induced Fault Injection AttemptsJoint MEDIAN–TRUDEVICE Open Forum, Sep 2014, Amsterdam, Netherlands |
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Laser attacks on integrated circuits: from CMOS to FD-SOIDTIS: Design and Technology of Integrated Systems in Nanoscale Era, May 2014, Santorin, Greece. ⟨10.1109/DTIS.2014.6850664⟩ |
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Simulating Laser Effects on ICs, from Physical Level to Gate Level: a comprehensive approachTRUDEVICE Workshop, May 2014, Paderborn, Germany |
Built-In Self-Test for Manufacturing TSV Defects before bondingVTS: VLSI Test Symposium, Apr 2014, Napa, CA, United States. ⟨10.1109/VTS.2014.6818771⟩ |
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Customized Cell Detector for Laser-Induced-Fault DetectionIOLTS: International On-Line Testing Symposium, Jul 2014, Platja d'Aro, Spain. pp.37-42, ⟨10.1109/IOLTS.2014.6873669⟩ |
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Improving the ability of Bulk Built-In Current Sensors to detect Single Event Effects by using triple-well CMOS25th European Symposium on Reliability of Electron Devices, Failure Physics and Analysis (ESREF 2014), Sep 2014, Berlin, Germany |
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2D to 3D Test Pattern Retargeting Using IEEE P1687 Based 3D DFT ArchitecturesISVLSI: International Symposium on Very Large Scale Integration, Jul 2014, Tampa, FL, United States. pp.386-391, ⟨10.1109/ISVLSI.2014.83⟩ |
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Identification of Hardware Trojans triggering signalsFirst Workshop on Trustworthy Manufacturing and Utilization of Secure Devices, May 2013, Avignon, France |
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A 3D IC BIST for pre-bond test of TSVs using Ring OscillatorsNEWCAS: New Circuits and Systems, Jun 2013, Paris, France. pp.001-004 |
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A JTAG based 3D DfT architecture using automatic die detectionPRIME 2013 - 9th Conference on Ph.D. Research in Microelectronics and Electronics, Jun 2013, Villach, France. pp.341-344, ⟨10.1109/PRIME.2013.6603184⟩ |
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3D Design For Test Architectures Based on IEEE P16874th IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits (3D-TEST), Sep 2013, Anaheim, CA, United States |
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A Bulk Built-in Sensor for Detection of Fault AttacksHOST: Hardware-Oriented Security and Trust, Jun 2013, Austin, TX, United States. pp.51-54, ⟨10.1109/HST.2013.6581565⟩ |
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A smart test controller for scan chains in secure circuitsIOLTS: International On-Line Testing Symposium, Jul 2013, Chania, Greece. pp.228-229, ⟨10.1109/IOLTS.2013.6604085⟩ |
A BIST Method for TSVs Pre-Bond TestIDT'13: 8th IEEE International Design & Test Symposium, Dec 2013, Marrakesh, Morocco. pp.1-6, ⟨10.1109/IDT.2013.6727081⟩ |
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Laser-Induced Fault SimulationEUROMICRO DSD/SEAA, Sep 2013, Santander, Spain. pp.609-614, ⟨10.1109/DSD.2013.72⟩ |
Sensitivity tuning of a bulk built-in current sensor for optimal transient-fault detectionESREF: European Symposium on Reliability of Electron devices, Failure physics and analysis, Sep 2013, Arcachon, France. pp.B3c-2 #68 |
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TSVs Pre-Bond Testing: a test scheme for capturing BIST responses3D-Test: Testing Three-Dimensional Stacked Integrated Circuits, Sep 2013, Anaheim, CA, United States |
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A single built-in sensor to check pull-up and pull-down CMOS networks against transient faultsPATMOS: Power and Timing Modeling, Optimization and Simulation, Sep 2013, Karlsruhe, Germany. pp.157-163, ⟨10.1109/PATMOS.2013.6662169⟩ |
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How to Sample Results of Concurrent Error Detection Schemes in Transient Fault Scenarios?RADECS: Radiation and Its Effects on Components and Systems, Sep 2011, Sevilla, Spain. pp.635-642, ⟨10.1109/RADECS.2011.6131361⟩ |
Circuits intégrés en 3DROADEF 2012 - 13e Congrès de la Société Française de Recherche Opérationnelle et d'Aide à la Décision, Apr 2012, Angers, France |
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On-Chip Comparison for Testing Secure ICsDCIS 2012 - 27th Conference on Design of Circuits and Integrated Systems, Nov 2012, Avignon, France. pp.112-117 |
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A New Scan Attack on RSA in Presence of Industrial CountermeasuresCOSADE: Constructive Side-Channel Analysis and Secure Design, May 2012, Darmstadt, Germany. pp.89-104, ⟨10.1007/978-3-642-29912-4_8⟩ |
Novel transient-fault detection circuit featuring enhanced bulk built-in current sensor with low-power sleep-modeESREF: European Symposium on Reliability of Electron devices, Failure physics and analysis, Oct 2012, Cagliari, Italy |
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Are Advanced DfT Structures Sufficient for Preventing Scan-Attacks?VTS'12: 30th IEEE VLSI Test Symposium, Apr 2012, Maui, Hawai, United States. pp.246-251 |
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Calibrating Bulk Built-in Current Sensors for Detecting Transient FaultsColloque GDR SoC-SiP, 2012, Lyon, France |
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A Scan-based Attack on Elliptic Curve Cryptosystems in presence of Industrial Design-for-Testability StructuresIEEE International Symposium on Defect and Fault Tolerance in VLSI & Nanotechnology Systems, United States. http://www.dfts.org/ |
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A New Bulk Built-in Current Sensor-Based Strategy for Dealing with Long-Duration Transient Faults in Deep-Submicron TechnologiesDFT'2011: International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, Oct 2011, Vancouver, Canada. pp.302-308, ⟨10.1109/DFT.2011.15⟩ |
Power Consumption Traces Realignment to Improve Differential Power AnalysisDDECS'11: 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits ans Systems, Germany. pp.201-206 |
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Timing Issues of Transient Faults in Concurrent Error Detection SchemesGdR SoC-SiP'2011: Colloque national du Groupement de Recherche System-On-Chip et System-In-Package, Jun 2011, Lyon, France. http://www2.lirmm.fr/~w3mic/SOCSIP/ |
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Timing Issues for an Efficient Use of Concurrent Error Detection CodesLATW: Latin American Test Workshop, Mar 2011, Porto de Galinhas, Brazil. pp.1-6, ⟨10.1109/LATW.2011.5985933⟩ |
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New Security Threats Against Chips Containing Scan Chain StructuresHOST'11: IEEE International Symposium on Hardware-Oriented Security and Trust, San Diego, CA, United States. pp.105-110 |
Scan Attacks and Countermeasures in Presence of Scan Response CompactorsETS: European Test Symposium, May 2011, Trondheim, Norway. pp.19-24, ⟨10.1109/ETS.2011.30⟩ |
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New side-channel attack against scan chains9th CryptArchi Workshop (2011), Jun 2011, Bochum, Germany. pp.2 |
Evaluation of Concurrent Error Detection Techniques on the Advanced Encryption StandardIOLTS: International On-Line Testing Symposium, Jul 2010, Corfu, Greece. pp.223-228, ⟨10.1109/IOLTS.2010.5560196⟩ |
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Waveforms re-Alignment to Improve DPA AttacksCryptArchi: Cryptographic Architectures, Jun 2010, Gif-sur-Yvette, France |
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Evaluation of Resistance to Differential Power Analysis: Execution Time Optimizations for DesignersDELTA'10: Fifth IEEE International Symposium on Electronic Design, Test and Application, Jan 2010, Ho Chi Minh City, Vietnam. pp.256-261 |
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Ensuring High Testability without Degrading SecurityDDECS'10: IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, Vienna, Austria. pp.6 |
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Evaluation of Concurrent Error Detection Techniques on the Advanced Encryption StandardETS: European Test Symposium, May 2010, Prague, Czech Republic |
Tutorial on Design For Testability & Digital SecurityIEEE 10th Latin American Test Workshop, 2009, Buzios, Brazil |
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Ensuring High Testability without Degrading SecurityETS: European Test Symposium, May 2009, Seville, Spain |
Execution Time Reduction of Differential Power Analysis ExperimentsLATW'09: 10th Latin-American Test Workshop, Mar 2009, Armaçao dos Buzios, Brazil, pp.1-5, ⟨10.1109/LATW.2009.4813819⟩ |
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Improving the Test of NoC-Based SoCs with Help of Compression SchemesISVLSI: IEEE Symposium on Very Large Scale Integration, Apr 2008, Montpellier, France. pp.139-144, ⟨10.1109/ISVLSI.2008.86⟩ |
A Reliable Architecture for the Advanced Encryption Standard13th IEEE European Test Symposium, May 2008, Verbania, Italy. pp.13-18, ⟨10.1109/ETS.2008.26⟩ |
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An Integrated Validation Environment for Differential Power AnalysisSAME'08: Sophia-Antipolis Forum on MicroElectronics 2008, Sep 2008, Sophia-Antipolis, France |
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Low Cost Self-Test of Crypto-DevicesWDSN'08: 2nd Workshop on Dependable and Secure Nanocomputing, Jun 2008, Anchorage, Canada, United States. pp.41-46 |
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Stuck-at-Faults Test using Differential Power AnalysisLPonTR'08: Workshop on Low Power Design Impact on Test and Reliability, May 2008, Italy |
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AES-based BIST: Self-test, Test Pattern Generation and Signature Analysis4th IEEE International Symposium on Electronic Design, Test and Applications (DELTA), Jan 2008, Hong-Kong, China. pp.314-321, ⟨10.1109/DELTA.2008.86⟩ |
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L'auto-test d'un coeur de chiffrement AESJNRDM'08 : Journées Nationales du Réseau Doctoral en Microélectronique, May 2008, France. pp.4 |
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Observability of Stuck-at-Faults with Differential Power AnalysisLATW'08: IEEE Latin American Test Workshop, Feb 2008, Mexico. pp.N/A |
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An Integrated Validation Environment for Differential Power AnalysisDELTA: Electronic Design, Test and Applications, Jan 2008, Hong Kong, China. pp.527-532, ⟨10.1109/DELTA.2008.61⟩ |
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A Reliable Architecture for Substitution Boxes in Integrated CryptographicDCIS'08: Conference on Design of Circuits and Integrated Systems, Nov 2008, pp.27-32 |
Power Supply Investigation for Wireless Wafer TestLATW'08: 9th Latin-American Test Workshop, Mar 2008, Puebla, Mexico. pp.165-170 |
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Test Data Compression and TAM DesignVLSI-SoC 2007 - IFIP International Conference on Very Large Scale Integration, Oct 2007, Atlanta, GA, United States. pp.178-183, ⟨10.1109/VLSISOC.2007.4402494⟩ |
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An On-Line Fault Detection Scheme for SBoxes in Secure CircuitsIOLTS 2007 - 13th IEEE International On-Line Testing and Robust System Design Symposium, Jul 2007, Heraklion, Crete, Greece. pp.57-62, ⟨10.1109/IOLTS.2007.16⟩ |
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Utilisation de ressources cryptographiques pour le test des circuits sécurisésColloque du GDR SoC-SiP, Jun 2007, Paris, France |
On-Line Self-Test of AES Hardware ImplementationsDSN'07: Workshop on Dependable and Secure Nanocomputing, Jun 2007, Edinburgh, United Kingdom |
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A Novel Parity Bit Scheme for SBOX in AES CircuitsIEEE Design and Diagnostics of Electronic Circuits and Systems (DDECS), Apr 2007, Cracovie, Poland. pp.267-271, ⟨10.1109/DDECS.2007.4295295⟩ |
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AES vs LFSR Based Test Pattern Generation: A Comparative StudyLATW: Latin American Test Workshop, Mar 2007, Cuzco, Peru. pp.314-321 |
Test and SecurityCryptArchi: Cryptographic Architectures, Jun 2007, Montpellier, France |
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Compression de Données de Test : Réduction du Nombre de Broches et Gain en Temps de TestJNRDM: Journées Nationales du Réseau Doctoral de Microélectronique, May 2006, Rennes, France |
Scan Pattern WatermarkingLATW'06: 7th IEEE Latin American Test Workshop, Mar 2006, Buenos Aires, pp.63-67 |
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A secure Scan Design MethodologyDATE: Design, Automation and Test in Europe, Mar 2006, Munich, Germany. pp.1177-1178, ⟨10.1109/DATE.2006.244019⟩ |
A Secure Scan Design MethodologyLATW'06: 7th IEEE Latin American Test Workshop, Mar 2006, Buenos Aires, Argentina. pp.81-86 |
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Testing System-in-Package WirelesslyLATW'06: 7th Latin American Test Workshop, 2006, Buenos Aires, Argentina. pp.73-78 |
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Fitting ATE Channels with Scan Chains: A Comparison Between a Test Data Compression Technique and Serial Loading of Scan ChainsDELTA'06: Third IEEE International Workshop on Electronics DesignTest & Applications, Kuala Lumpur (Malaysia), pp.295-300 |
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Secure Scan Techniques: a ComparisonIOLTS: International On-Line Testing Symposium, Jul 2006, Como, Italy. pp.119-124, ⟨10.1109/IOLTS.2006.55⟩ |
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Testing System-In-Package WirelesslyDTIS: Design and Technology of Integrated Systems in Nanoscale Era, Sep 2006, Tunis, Tunisia. pp.222-226 |
Test Control for Secure Scan DesignsETS: European Test Symposium, May 2005, Tallinn, Estonia. pp.190-195 |
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Mutation sampling technique for the generation of structural test data6th IEEE Latin American Test Workshop, Mar 2005, Salvador, Bahia, Brazil |
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Test Engineering Education in Europe: The EuNICE Test ProjectEDUTECH'05, 2005, France |
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Scan Design and Secure Chips : Can They Work TogetherSAME'05: Sophia-Antipolis Forum on MicroElectronics, Oct 2005, Sophia-Antipolis, France |
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Mutation Sampling Technique for the Generation of Structural Test DataDATE 2005 - 8th Design, Automation and Test in Europe Conference and Exhibition, Mar 2005, Munich, Germany. pp.1022-1023, ⟨10.1109/DATE.2005.220⟩ |
Testing a Secure Device: High Coverage with Very Low ObservabilityITC'04: International Test Conference, Oct 2004 |
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Digital, Memory and Mixed-Signal Test Engineering Education: Five Centres of Competences in EuropeDELTA: Electronic Design, Test and Applications, Jan 2004, Perth, Australia. pp.135-139 |
User-Constrained Test Architecture Design for Modular SOC TestingETS: European Test Symposium, May 2004, Ajaccio, Corsica, France. pp.80-85, ⟨10.1109/ETSYM.2004.1347611⟩ |
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Test Digital, Test de Mémoires, Test Mixte : 5 Centres de Compétence pour la Formation en EuropeCNFM'04 : 8ème Journées Pédagogiques du Comité National de Formation en Microélectronique, 2004, Saint Malo, France. p. 242 |
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Scan design and secure chip [secure IC testing]IOLTS: International On-Line Testing Symposium, Jul 2004, Madeira Island, Portugal. pp.219-224, ⟨10.1109/OLT.2004.1319691⟩ |
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An Arithmetic Structure for Test Data Horizontal CompressionDATE 2004 - 7th Design, Automation and Test in Europe Conference and Exhibition, Feb 2004, Paris, France. pp.428-434, ⟨10.1109/DATE.2004.1268884⟩ |
On Using Test Vector Differences for Reducing Test Pin NumbersDELTA'04: 2nd International Workshop on Electronic DesignTest and Applications, Jan 2004, Perth (Australia), pp.275-280 |
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Structural and Functional Analysis for Initialization of High Pipelined Industrial BISTed Circuits Using Partial ResetLATW: 4th IEEE Latin American Test Workshop, Natal, Brazil. pp.84-89 |
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Test Engineering Education in Europe: The EuNICE-Test ProjectMSE: Microelectronic Systems Education, Jun 2003, Anaheil, CA, United States. pp.85-86, ⟨10.1109/MSE.2003.1205266⟩ |
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An Efficient Approach to SoC Wrapper Design, TAM Configuration and Test SchedulingETW: European Test Workshop, 2003, Maastricht, Netherlands. pp.51-56 |
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Software-Based Testing of Sequential VHDL Descriptions8th IEEE European Test Workshop (ETW), May 2003, Maastricht, Netherlands. pp.199-200 |
European Network for Test EducationDELTA'02: 1st International Workshop on Electronic DesignTest and Applications, Christchurch, New Zeland, pp.230-239 |
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A Simple and Effective Compression Scheme for Test Pins ReductionHLDVT 2002 - 7th IEEE International High Level Design Validation and Test Workshop, Oct 2002, Cannes, France. pp.165-168, ⟨10.1109/HLDVT.2002.1224447⟩ |
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Initialization of Partially LBISTed Sequential CircuitsETW: European Test Workshop, May 2002, Corfou, Greece |
Initialisatioin des Circuits Séquentiels Avant Test Intégré et Scan PartielColloque du GDR CAO de Circuits et Systèmes Intégrés, Paris (France), France. pp. 39-42 |
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A Remote Access to Engineering Test Facilities for the Distant Education of European Microelectronics Students32nd Annual Frontiers in Education (FIE), Nov 2002, Boston, MA, United States. pp.T2E-24, ⟨10.1109/FIE.2002.1157943⟩ |
EuNICE-Test Project: A remote Access to Engineering Test for European UniversitiesEWME: European Workshop on Microelectronics Education, 2002, Vigo, Spain. pp.133-136 |
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A Heuristic for Test scheduling at System LevelDATE: Design, Automation and Test in Europe, Mar 2002, Paris, France. pp.1124-1124, ⟨10.1109/DATE.2002.998480⟩ |
Is high level test synthesis just design for test?ITC: International Test Conference, Oct 1995, Washington, DC, United States. pp.294-298, ⟨10.1109/TEST.1995.529846⟩ |
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Full key recovery for advanced Logic Locking SchemesCHES 2024 - Conference on Cryptographic Hardware and Embedded Systems, Sep 2024, Halifax, Canada. |
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Logic-Locking schemes and side channel attacks resilienceSAFEST Workshop, Jun 2023, Tallinn (Virtual), Estonia |
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Sécurité et intégrité dans un Contexte Embarqué15e Colloque National du GDR SoC², Jun 2021, Rennes, France |
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Encryption Techniques for Test Infrastructures13e Colloque National Du GDR SoC², Jun 2019, Montpellier, France. |
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Scan chain encryption, a countermeasure against scan attacksPHISIC: Practical Hardware Innovations in Security Implementation and Characterization, May 2018, Gardanne, France. , Workshop on Practical Hardware Innovations in Security Implementation and Characterization, 2018 |
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Sécurité des moyens de test des SoCJournée thématique des GDR SoC² et Sécurité Informatique : Sécurité des SoC complexes hétérogènes – de la TEE au matériel, Sep 2018, Paris, France. 2018 |
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SECCS: SECure Context Saving for IoT Devices12e Colloque National du GDR SoC/SiP, Jun 2018, Paris, France. 2018 |
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Stream cipher-based scan encryption in test standards12e Colloque National du GDR SoC/SiP, Jun 2018, Paris, France. 2018 |
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Scan chain encryption in Test StandardsSURREALIST: SecURity, REliAbiLity, test, prIvacy, Safety and Trust of Future Devices, May 2018, Bremen, Germany. , Workshop on SecURity, REliAbiLity, test, prIvacy, Safety and Trust of Future Devices, 2018 |
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Scan Chain Encryption for the Test, Diagnosis and Debug of Secure CircuitsSETS: South European Test Seminar, Mar 2017, Alpe d'Huez, France. , 2017 |
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Sécurisation des structures de test : étude comparative11e Colloque National du GDR SoC/SiP, Jun 2017, Bordeaux, France. 2017 |
Detection and Prevention of Hardware Trojan through Logic TestingTRUDEVICE, Nov 2016, Barcelona, Spain. , 4th Workshop on Trustworthy Manufacturing and Utilization of Secure Devices, Manufacturing test of secure devices / Reverse engineering countermeasures / Other topics, pp.#33, 2016, Posters IV |
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Exact wafer matching process wafer to wafer inegration3D Integration Applications, 2012, Grenoble, France. Workshop on 3D Integration Applications, Technology, Architecture, Design, Automation, and Test, 2012 |
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tLIFTING : A Multi-level Delay-annotated Fault Simulator for Digital CircuitsDCIS 2012 - 27th Conference on Design of Circuits and Integrated Systems, Nov 2012, Avignon, France. , 2012 |
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TOETS: Work Package 1The European Nanoelectronics Forum 2011, Nov 2011, Dublin, Ireland. , 2011 |
Wireless Wafer Test for Iterative Testing During System Assembly3D-Test: Testing Three-Dimensional Stacked Integrated Circuits, Nov 2010, Austin, Texas, United States. , 1st IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits, 2010 |
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Wireless Test Structure for Integrated SystemsITC'2008: International Test Conference, Oct 2008, Santa Clara, CA, United States. pp.N/A, 2008, ⟨10.1109/TEST.2008.4700704⟩ |
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A Dependable Parallel Architecture for SBoxesReCoSoc'07: International Workshop on Reconfigurable Communication Centric System-On-Chips, Jun 2007, Montpellier, France. pp.CD-ROM, 2007 |
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TAM Design and Test Data Compression for SoC Test Cost ReductionETS: European Test Symposium, May 2007, Freiburg, Germany. 12th IEEE European Test Symposium, pp.241-246, 2007 |
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Improving NoC-based Testing Through Compression SchemesDATE: Design, Automation and Test in Europe, Apr 2007, Nice, France. , 2007 |
Test Engineering Education in Europe: The CRTC Experience Through the EuNICE-Test ProjectAchim Rettberg and Christophe Bobda. IFIP TC10 Working Conference: EduTech'05, Oct 2005, France. , pp.63-77, 2005 |
Test de Circuits et de Systèmes IntégrésCollection EGEM, Ed.Hermès, 2004, 2-7462-0864-4 |
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SOC Design MethodologiesSpringer, 2002, ⟨10.1007/978-0-387-35597-9⟩ |
Chapitre 6 : On Countermeasures Against Fault Attacks on the Advanced Encryption StandardMarc Joye and Michael Tunstall. Fault Analysis in Cryptography, Springer, pp.89-109, 2012, Information Security and Cryptography, 978-3-642-29656-0 (-7 for eBook) |
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Chapter 9: Fault Detection in Crypto-devicesWei Zhang. Fault Detection, InTech, pp.177-194, 2010, 978-953-307-037-7. ⟨10.5772/213⟩ |
Compression-Based SoC Test InfrastructuresVLSI-SoC: Advanced Topics on Systems on a Chip, 291, Springer, pp.53-68, 2009, IFIP Advances in Information and Communication Technology, 978-0-387-89557-4 |
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Power-Constrained Test Scheduling for SoCs Under a "No Session" SchemeSOC Design Methodologies, 90, Kluwer Academic Publishers, pp.401-412, 2002, IFIP — The International Federation for Information Processing, 978-1-4757-6530-4. ⟨10.1007/978-0-387-35597-9_34⟩ |
System and Method for Wirelessly Testing Integrated CircuitsSpain, Patent n° : EP 08290891 WO 2010031879 (A1). 2008, pp.N/A |
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Test and Harware Security2008 |