Nathalie Julien

Documents

Publications

	Industrie et pandémie, quelles mutations ? Nathalie Julien , Eric Martin France Forum, 2020 Journal articles hal-03170845v1
	L'usine du futur sera humaine ou ne sera pas... Nathalie Julien , Eric Martin France Forum, 2019 Journal articles hal-02512118v1
	Le robot doit désormais prendre en compte son environnement Nathalie Julien Revue “Industries et Technologies“, 2019 Journal articles hal-02512121v1
	Énergie et puissance dans les systèmes embarqués Nathalie Julien Les Techniques de l'Ingenieur, 2015 Journal articles hal-02511905v1
	Estimation et optimisation de la consommation des mémoires Eric Senn , Gwenolé Corre , Nathalie Julien Revue des Sciences et Technologies de l'Information - Série TSI : Technique et Science Informatiques, 2008, 27 (1-2) Journal articles hal-00489820v1
	High-Level Interconnect Delay and Power Estimation Antoine Courtay , Olivier Sentieys , Johann Laurent , Nathalie Julien Journal of Low Power Electronics, 2008, 4 (1), pp.1-13. ⟨10.1166/jolpe.2008.152⟩ Journal articles hal-00267248v1
	Méthodes et outils d'estimation de la consommation de code embarqué sur processeur Johann Laurent , Eric Senn , Nathalie Julien Revue des Sciences et Technologies de l'Information - Série TSI : Technique et Science Informatiques, 2007, 26 (5), pp.509 Journal articles hal-00163973v1
	Power Consumption and Performance's Library on DSPs: Case Study MPEG2 Jalel Ktari , Mohamed Abid , Nathalie Julien , Johann Laurent Journal of Computer Science, 2007, 3, pp.168-173 Journal articles hal-00133994v1
	An FPGA power aware design flow David Elleouet , Yannig Savary , Nathalie Julien Lecture Notes in Computer Science, 2006, 4148/2006, pp.415-424 Journal articles hal-00437285v1
	SoftExplorer: Estimating and Optimizing the Power and Energy Consumption of a C Program for DSP Applications Eric Senn , Johann Laurent , Nathalie Julien , Eric Martin Eurasip Journal on Applied Signal Processing, 2005, Volume 2005, N°16, pp.2641-2654 Journal articles hal-00077302v1
	Panorama des outils d'analyse et d'optimisation de la consommation dans les SOC Nathalie Julien Annals of Telecommunications - annales des télécommunications, 2004, Numéro Systèmes sur puce électronique pour les télécommunications V59, pp.N°7-8 Journal articles hal-00105951v1
	Functional Level Power Analysis of Complex Processor Johann Laurent , Nathalie Julien , Eric Senn , Eric Martin Global DSP, 2003, 3 issue 9, pp 3-13 Journal articles hal-00077897v1
	Power Consumption Modeling and Characterization of the TI C6201 Nathalie Julien , Johann Laurent , Eric Senn , Eric Martin IEEE Micro, 2003, September/October 2003, http://computer.org Journal articles hal-00077330v1
	Low Power Synthesis Methodology with Data Format Optimization applied on a DWT Nathalie Julien , Eric Martin , Stéphane Gaillard Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology, 2003, 35, pp.195-211 Journal articles hal-00105943v1
	"Power Consumption Modeling of the TI C6201 and Characterization of its Architectural Complexity", IEEE Micro, Special Issue on Power- and Complexity-Aware Design, Nathalie Julien , Johann Laurent , Eric Senn , Eric Martin , Dave Albonesi IEEE Micro, 2003, x Journal articles hal-00083227v1
	High Level Power Analysis for Embedded DSP Software Johann Laurent , Nathalie Julien , Eric Martin IEEE TCCA NewsLetter, 2001, January 2001, pp.41 Journal articles hal-00077573v1

	Modeling of Smart Batteries for the Realization of a Digital Twin Prototype Fatemeh Taei , Mohammed Adel Hamzaoui , Nathalie Julien 9th International Conference on Control, Decision and Information Technologies (CoDIT 2023), Jul 2023, Rome, Italy. pp.2396-2401, ⟨10.1109/CoDIT58514.2023.10284101⟩ Conference papers hal-04457315v1
	Aide à la conception de l’architecture d’un jumeau numérique par la modélisation des données Doha Nefti , Mohammed Adel Hamzaoui , Nathalie Julien , Fayçal Balkaid CIGI QUALITA MOSIM 2023 Propulser la performance, Jun 2023, Trois-Rivières, Canada Conference papers hal-04121075v1
	Modular and Distributed Architecture using an Embedded Digital Twin for Assistive Technologies Adaptation Aurélian Houé , Cédric Seguin , Florent Frizon de Lamotte , Nathalie Julien , Willy Allègre 13th International Workshop on Service-Oriented, Holonic and Multi-Agent Manufacturing Systems for Industry of the Future (SOHOMA2023),, Université Savoie Mont Blanc, Sep 2023, Annecy, France Conference papers hal-04327426v1
	Modélisation comportementale d'un data center pour le développement d'un jumeau numérique Marouane El Mernissi , Roland Donat , Mohammed Hamzaoui , Nathalie Julien CIGI Qualita MOSIM 2023, Jun 2023, Québec, Canada Conference papers hal-04116913v1
	Long Short Term Memory-based anomaly detection applied to an industrial dosing pump Anthony Fombonne de Galatheau , Alexandru Liviu Olteanu , Nathalie Julien , Steven Le Garrec 14th IFAC Workshop on Intelligent Manufacturing Systems, Mar 2022, Tel-Aviv, Israel. pp.240-245, ⟨10.1016/j.ifacol.2022.04.200⟩ Conference papers hal-03663621v1
	Typology as a Deployment Tool for Digital Twins: Application to Maintenance in Industry Alexandre Blanchet , Nathalie Julien , Mohammed Adel Hamzaoui 32nd European Safety and Reliability Conference (ESREL 2022), Aug 2022, Dublin, Ireland Conference papers hal-03834124v1
	Using Cognitive Work Analysis to deploy collaborative digital twins : application to predictive maintenance Naomi Kamoise , Clément Guérin , Mohammed Hamzaoui , Nathalie Julien European Safety and Reliability Conference, Aug 2022, Dublin, Ireland. ⟨10.3850/978-981-18-5183-4_S10-10-646-cd⟩ Conference papers hal-03774847v1
	A Usage-driven Approach to Characterize and Implement Industrial Digital Twins Nathalie Julien , Eric Martin ESREL 31st European Safety and Reliability Conference, Sep 2021, Angers, France Conference papers hal-03257109v1
	How to Characterize a Digital Twin: A Usage-Driven Classification Nathalie Julien , Eric Martin 17th IFAC Symposium on Information Control Problems in Manufacturing, INCOM21, Jun 2021, Budapest, Hungary Conference papers hal-03170836v1
	Une approche générique du jumeau numérique pilotée par les usages Nathalie Julien , Eric Martin s-mart2021 : 17ème colloque national S-mart AIP-PRIMECA, Mar 2021, Valenciennes, France Conference papers hal-03170857v1
	Cobots, robots fixes, robots mobiles, comment les intégrer ? Nathalie Julien Salon Global Industrie, Mar 2019, Lyon, France Conference papers hal-02512132v1
	L'humain dans l'usine du futur Nathalie Julien Colloque Enseigner l'industrie du futur, Dec 2019, Nanterre, France Conference papers hal-02512139v1
	L'usine du futur, un défi pour tous Nathalie Julien Echange avec Université Québec Trois Rivières, Dec 2018, Trois Rivières, Canada Conference papers hal-02512143v1
	Cluster-Head Selection Algorithm to Enhance Energy-Efficiency and Reliability of Wireless Sensor Networks Van-Trinh Hoang , Nathalie Julien , Pascal Berruet 20th European Wireless (EW) Conference., May 2014, Barcelona, Spain. pp. xxx Conference papers hal-00975338v1
	On-line self-diagnosis based on power measurement for a wireless sensor node Van-Trinh Hoang , Nathalie Julien , Pascal Berruet First IEEE Workshop on Highly-Reliable Power-Efficient Embedded Designs, Feb 2013, Shenzhen, China. p. xx-xx Conference papers hal-00782758v2
	Increasing the autonomy of Wireless Sensor Node by effective use of both DPM and DVFS methods Van-Trinh Hoang , Nathalie Julien , Pascal Berruet 12th Edition of IEEE Faible Tension Faible Consommation - IEEE FTFC 2013, Jun 2013, Paris, France. pp.xx-yy Conference papers hal-00823924v1
	The detection and localization of hard-failure for Wireless Sensor Node based on online power management Van-Trinh Hoang , Nathalie Julien , Pascal Berruet Le huitième colloque du GDR SOC-SIP du CNRS, Jun 2013, Lyon, France Conference papers hal-00975322v1
	Conception sous Contraintes de Sûreté de Fonctionnement et de Consommation d'énergie de Réseau de Capteurs Sans Fil Van-Trinh Hoang , Nathalie Julien , Pascal Berruet Le sixième colloque du GDR SOC-SIP du CNRS, Jun 2012, Paris, France Conference papers hal-00975319v1
	Design under Constraints of Availability and Energy for Sensor Node in Wireless Sensor Network Van-Trinh Hoang , Nathalie Julien , Pascal Berruet IEEE International Conference on Design and Architectures for Signal and Image Processing (DASIP), October 2012, Oct 2012, Karlsruhe, Germany. pp.E-ISBN : 978-2-9539987-4-0 Conference papers hal-00768442v1
	Virtual SoPC Rad-Hardening for Satellite Applications Ludovic Barrandon , Thierry Capitaine , Loïc Lagadec , Nathalie Julien , Christophe Moy ReCoSoC'10, May 2010, Karlsruhe, Germany. 2 p Conference papers hal-00489327v1
	Building and Using System, Algorithmic, and Architectural Power and Energy Models in the FPGA Design-Flow Eric Senn , Nathalie Julien ReCoSoC 2006, Jul 2009, France Conference papers hal-00083353v1
	Interconnect Explorer: A High-level Power Estimation Tool for On-Chip Interconnects Antoine Courtay , Johann Laurent , Olivier Sentieys , Nathalie Julien User Track of the Design Automation Conference, DAC 2009, Jul 2009, San Francisco, United States. pp.1 Conference papers hal-00417246v1
	Using Integer Linear Programming in Test-Bench Generation for Evaluating Communication Processors Eric Senn , David Monnereau , André Rossi , Nathalie Julien 12th Euromicro Conference on Digital System Design, 2009, Greece. pp.217-220, ⟨10.1109/DSD.2009.236⟩ Conference papers hal-00662617v1
	Using integer linear programming in test-bench generation for evaluating communication processors Eric Senn , André Rossi , Nathalie Julien , Dominique Monnereau 12th Euromicro Conference on Digital System Design (DSD), Aug 2009, Patras, Greece Conference papers hal-00489826v1
	New Directions in Interconnect Performance Optimization Antoine Courtay , Johann Laurent , Nathalie Julien , Olivier Sentieys 3rd International Conference on Design and Technology of Integrated Systems in Nanoscale Era, 2008. DTIS 2008., Mar 2008, Tozeur, Tunisia. pp.6, ⟨10.1109/DTIS.2008.4540228⟩ Conference papers hal-00294132v1
	Modélisation, Estimation et Optimisation de la consommation des interconnexions dans les SOC Antoine Courtay , Johann Laurent , Nathalie Julien , Olivier Sentieys GDR SOC SIP, Jun 2008, Paris, France Conference papers hal-00294145v1
	Novel Cross-Transition Elimination Technique Improving Delay and Power Consumption for On-Chip Buses Antoine Courtay , Johann Laurent , Olivier Sentieys , Nathalie Julien International Workshop on Power and Timing Modeling, Optimization and Simulation. PATMOS 2008, Sep 2008, Lisbonne, Portugal. pp.359-368 Conference papers hal-00345737v1
	Modélisation et estimation de la consommation des interconnexions dans les SOC Antoine Courtay , Johann Laurent , Olivier Sentieys , Nathalie Julien FTFC, May 2007, Paris, France. pp.121 Conference papers hal-00169256v1
	Performance estimation of communication processors using design of experiments Eric Senn , Nathalie Julien Workshop on Design and Architectures for Signal and Image Processing, DASIP07, Nov 2007, Grenoble, France. pp.1 Conference papers hal-00370837v1
	High-Level Power Estimation and Exploration of FPGA Eric Senn , Nathalie Julien IEEE International Symposium on Industrial Electronics, Jun 2007, Vigo, Spain. pp.1 Conference papers hal-00370839v1
	A High Level SoC Power Estimation Based on IP Modeling David Elleouet , Nathalie Julien , Dominique Houzet 13th Reconfigurable Architectures Workshop, Apr 2006, Rhodes Island, Greece. pp.XX-XX Conference papers hal-00105873v1
	Building and Using System, Algorithmic, and Architectural Power and Energy Models in the FPGA Design-Flow Eric Senn , Nathalie Julien , David Elleouet , Yannig Savary , Nabil Abdelli Jul 2006, pp.XX-XX Conference papers hal-00105912v1
	Interconnexions et consommation: où en sommes nous? Antoine Courtay , Olivier Sentieys , Nathalie Julien MajecSTIC, Nov 2006, LORIENT, France. pp.Interconnexions et consommation: où en sommes nous? Conference papers hal-00169249v1
	A FPGA Power Aware Design Flow David Elleouet , Yannig Savary , Nathalie Julien Power and Timing Modeling, Optimization and Simulation 2006, Sep 2006, Montpellier, France. pp.XX-XX Conference papers hal-00105869v1
	Méthodologie de Modélisation de la Consommation des Applications sur FPGA David Elleouet , Nathalie Julien , Dominique Houzet May 2006, pp.XX-XX Conference papers hal-00105911v1
	Une méthode d'optimisation mémoire à haut niveau par gestion logicielle de cache (scratchpad)" Florian Marteil , Eric Senn , Nathalie Julien , Eric Martin May 2005 Conference papers hal-00083345v1
	Estimation de la consommation logicielle dans un système embarqué : Etude de cas Jalel Ktari , Johann Laurent , Mohamed Abid , Nathalie Julien 2005, pp.55-59 Conference papers hal-00077590v1
	Réduction de l'influence du placement mémoire par la synthèse de haut niveau Gwenolé Corre , Nathalie Julien , Eric Senn , Eric Martin FTFC'05 (journées d'études Faible Tension Faible Consommation), 2005, Paris, France Conference papers hal-00077388v1
	Méthodologie de Modélisation de la Consommation d'Applications à Haut-Niveau pour la Conception Système. David Elleouet , Nathalie Julien , Olivier Déforges , Dominique Houzet Apr 2005, pp.XX-XX Conference papers hal-00105900v1
	Méthodologie de Modélisation Multi-Niveau de la consommation des Applications sur FPGA. Yannig Savary , David Elleouet , Nathalie Julien , Dominique Houzet , Frédéric Blanc May 2005, pp.97-102 Conference papers hal-00105790v1
	Méthodologie de modélisation de la consommation sur FPGA : Application au VirtexE 400 Yannig Savary , Nathalie Julien , Eric Senn , Frédéric Blanc , Laurent Letellier Apr 2005, pp.125-137 Conference papers hal-00105819v1
	Etude de la consommation de plates-formes multiprocesseurs Johann Laurent , Eric Senn , Nathalie Julien , Eric Martin 2005, pp.33-38 Conference papers hal-00077589v1
	Méthodologie de Modélisation à Haut-niveau de la Consommation des Applications du T.D.S.I sur FPGA David Elleouet , Nathalie Julien , Olivier Déforges , Dominique Houzet Jan 2005, pp.XX-XX Conference papers hal-00105903v1
	A High Level Power modeling IP Methodology for SoC Design Based on FPGA Approach David Elleouet , Nathalie Julien , Dominique Houzet Dec 2005, pp.XX-XX Conference papers hal-00105888v1
	Power/Energy Estimation in SoCs by Multi-Level Parametric Modeling Nathalie Julien , Johann Laurent , Eric Senn , David Elleouet , Yannig Savary Jun 2005, pp.XX-XX Conference papers hal-00105910v1
	High Level Ageing Vectors Management for Data Intensive Applications Gwenolé Corre , Eric Senn , Nathalie Julien , Eric Martin 2005 Conference papers hal-00077305v1
	A Complete Methodology for Memory Optimization in DSP Applications Florian Marteil , Nathalie Julien , Eric Senn , Eric Martin Sep 2004 Conference papers hal-00083337v1
	A Memory Aware behavioral Synthesis Tool for Real-Time VLSI Circuits Gwenolé Corre , Nathalie Julien , Eric Martin , Eric Senn ACM Great Lake Symposium on VLSI, 2004, Boston, France. pp.82-85 Conference papers hal-00077370v1
	Memory aware HLS and the implementation of ageing vectors Gwenolé Corre , Eric Senn , Nathalie Julien , Eric Martin EUROMICRO Symposium on Digital System Design, 2004, Rennes, France. pp.88-95 Conference papers hal-00077366v1
	Algorithmic level power and energy optimization for DSP applications: SoftExplorer Eric Senn , Johann Laurent , Nathalie Julien , Eric Martin ISIVC, 2004, Brest, France Conference papers hal-00013978v1
	Power Consumption Characterization and Modeling of Embedded Memories in Xilinx Virtex 400E FPGA David Elleouet , Nathalie Julien , Dominique Houzet , Jean-Gabriel Cousin , Eric Martin Digital System Design, EUROMICRO Systems on (DSD'04), Aug 2004, France. pp.394 - 401, ⟨10.1109/DSD.2004.75⟩ Conference papers hal-00105905v1
	Memory Accesses management during High Level Synthesis Gwenolé Corre , Eric Senn , Pierre Bomel , Nathalie Julien , Eric Martin IEEE ACM CO-DESign symposium and International Symposium on System Synthesis, 2004, stockholm, Sweden. pp.42-47 Conference papers hal-00077355v1
	SoftExplorer: estimation, characterization and optimization of the power and energy consumption at the algorithmic level Eric Senn , Johann Laurent , Nathalie Julien , Eric Martin 2004, pp.10 Conference papers hal-00013977v1
	Functional Level Power Analysis: An Efficient Approach for Modeling the Power Consumption of Complex Processors Johann Laurent , Eric Senn , Nathalie Julien , Eric Martin DATE, 2004, Paris, France. pp 666 Conference papers hal-00013979v1
	"High Level Ageing Vectors Management for Data Intensive Applications", Gwenole Corre , Eric Senn , Nathalie Julien , Eric Martin Sep 2004 Conference papers hal-00083341v1
	SoftExplorer: estimation of the power and energy consumption for DSP applications Eric Senn , Johann Laurent , Nathalie Julien , Eric Martin 2004, pp.0 Conference papers hal-00013976v1
	A Memory Aware High Level Synthesis Tool Gwenole Corre , Nathalie Julien , Eric Senn , Eric Martin ISVLSI 2004, 2004, Tempa (florida), United States Conference papers hal-00008501v1
	approche logicielle de la consommation dans les systèmes embarqués Nathalie Julien Congrès international de Signaux, Circuits et Systèmes, SCS2004, Mar 2004, Monastir, Tunisia Conference papers hal-00106246v1
	A Memory Aware High Level Synthesis Tool Gwenolé Corre , Nathalie Julien , Eric Senn , Eric Martin International Symposium on VLSI, 2004, Lafayette, Louisiana, United States. pp.279-280 Conference papers hal-00077377v1
	Memory Aware High-Level Synthesis for Embedded Systems Gwenolé Corre , Eric Senn , Nathalie Julien , Eric Martin IADIS conference on Applied Computing, 2004, Lisbonne, Portugal. pp.499-506 Conference papers hal-00077375v1
	Ordonnancement sous contraintes de mémorisation : une optimisation efficace des ressources lors de la synthèse d'architecture Gwenole Corre , Nathalie Julien , Eric Senn , Eric Martin 2003, pp.147-152 Conference papers hal-00008498v1
	Contraintes mémoire et solution architecturale pour applications TDSI Gwenole Corre , Nathalie Julien , Eric Senn , Eric Martin 2003, pp.150-154 Conference papers hal-00008496v1
	Conception faible consommation Nathalie Julien Ecole thématique Architecture des systèmes matériels enfouis et méthodes de conception associées, ARCHI'03, 2003, Roscoff, France Conference papers hal-00106230v1
	Optimisation de la consommation des unités de mémorisation lors de la synthèse d'architecture Gwenole Corre , Nathalie Julien , Eric Senn , Eric Martin 2002, pp.169-172 Conference papers hal-00008500v1
	Power Consumption Estimation of a C-algorithm: A New Perspective for Software Design Nathalie Julien , Eric Senn , Johann Laurent , Eric Martin 2002, pp 67-72 Conference papers hal-00077561v1
	Power Estimation of a C algorithm on a VLIW Processor Nathalie Julien , Eric Senn , Johann Laurent , Eric Martin 2002, pp 100 Conference papers hal-00077336v1
	Power Estimation of a C algorithm based on the Functional- Level Power Analysis of a Digital Signal Processor Nathalie Julien , Johann Laurent , Eric Senn , Eric Martin 2002, pp 354-360 Conference papers hal-00077553v1
	Intégration de la synthèse mémoire dans l'outil de synthèse d'architecture GAUT Low Power Gwenolé Corre , Nathalie Julien , Eric Senn , Eric Martin JFAAA'02 (Journées Francophone Adéquation Algorithme Architecture), 2002, monastir, Tunisie Conference papers hal-00077402v1
	Estimation de la consommation d'un algorithme C par analyse fonctionnelle Johann Laurent , Nathalie Julien , Eric Senn , Eric Martin 2002, pp 165-168 Conference papers hal-00077559v1
	Power Consumption Estimation of a C Program for Data-Intensive Applications Eric Senn , Nathalie Julien , Johann Laurent , Eric Martin 2002, pp 332-342 Conference papers hal-00077332v1
	Estimation de la consommation d'un algorithme C intégrant l'architecture cible : une aide efficace pour la conception système Johann Laurent , Nathalie Julien , Eric Senn , Eric Martin 2002, pp 100 Conference papers hal-00077890v1
	High-Level Energy Estimation for DSP Systems Johann Laurent , Eric Senn , Nathalie Julien , Eric Martin 2001, pp 3.1.1-3.1.10 Conference papers hal-00077563v1
	High Level Power Estimation based on a functional analysis for Embedded DSP Software Johann Laurent , Nathalie Julien , Eric Senn , Eric Martin 2001, pp 168-172 Conference papers hal-00077564v1
	High Level Power Analysis for Embedded DSP Software Johann Laurent , Nathalie Julien , Eric Martin 2000, pp 100 Conference papers hal-00077588v1
	High Level Power Estimation for DSP Johann Laurent , Nathalie Julien , Eric Martin 2000, pp 112-117 Conference papers hal-00077587v1
	Area/Time/Power space exploration in module selection for DSP high level synthesis Stéphane Gaillard , Jean-Philippe Diguet , Nathalie Julien , Eric Martin Patmos'97, Sep 1997, Belgium Conference papers hal-00104770v1

	Le jumeau numérique Nathalie Julien , Eric Martin Dunod. Dunod, 2020, 978-2-10-080028-5 Books hal-02886100v1
	L'usine du futur - Stratégies et déploiement. Industrie 4.0, de l'IoT aux jumeaux numériques Eric Martin , Nathalie Julien 2018 Books hal-02457869v1

	Spatial Switching Johann Laurent , Antoine Courtay , Olivier Sentieys , Nathalie Julien France, N° de brevet: 0851672. 2008, pp.19 Patents hal-00267251v1

	Il faut repenser le rapport au travail Nathalie Julien , Eric Martin 2018 Other publications hal-02512129v1
	On-chip interconnects energy consumption: High-level estimation and architectural optimizations Antoine Courtay , Olivier Sentieys , Johann Laurent , Nathalie Julien 2009 Other publications hal-00417253v1
	Interconnect Explorer: a High-Level Estimation Tool for On-Chip Interconnects Antoine Courtay , Olivier Sentieys , Johann Laurent , Nathalie Julien 2008 Other publications hal-00294146v1

Nathalie Julien

Publications

Industrie et pandémie, quelles mutations ?

L'usine du futur sera humaine ou ne sera pas...

Le robot doit désormais prendre en compte son environnement

Énergie et puissance dans les systèmes embarqués

Estimation et optimisation de la consommation des mémoires

High-Level Interconnect Delay and Power Estimation

Méthodes et outils d'estimation de la consommation de code embarqué sur processeur

Power Consumption and Performance's Library on DSPs: Case Study MPEG2

An FPGA power aware design flow

SoftExplorer: Estimating and Optimizing the Power and Energy Consumption of a C Program for DSP Applications

Panorama des outils d'analyse et d'optimisation de la consommation dans les SOC

Functional Level Power Analysis of Complex Processor

Power Consumption Modeling and Characterization of the TI C6201

Low Power Synthesis Methodology with Data Format Optimization applied on a DWT

"Power Consumption Modeling of the TI C6201 and Characterization of its Architectural Complexity", IEEE Micro, Special Issue on Power- and Complexity-Aware Design,

High Level Power Analysis for Embedded DSP Software

Modeling of Smart Batteries for the Realization of a Digital Twin Prototype

Aide à la conception de l’architecture d’un jumeau numérique par la modélisation des données

Modular and Distributed Architecture using an Embedded Digital Twin for Assistive Technologies Adaptation

Modélisation comportementale d'un data center pour le développement d'un jumeau numérique

Long Short Term Memory-based anomaly detection applied to an industrial dosing pump

Typology as a Deployment Tool for Digital Twins: Application to Maintenance in Industry

Using Cognitive Work Analysis to deploy collaborative digital twins : application to predictive maintenance

A Usage-driven Approach to Characterize and Implement Industrial Digital Twins

How to Characterize a Digital Twin: A Usage-Driven Classification

Une approche générique du jumeau numérique pilotée par les usages

Cobots, robots fixes, robots mobiles, comment les intégrer ?

L'humain dans l'usine du futur

L'usine du futur, un défi pour tous

Cluster-Head Selection Algorithm to Enhance Energy-Efficiency and Reliability of Wireless Sensor Networks

On-line self-diagnosis based on power measurement for a wireless sensor node

Increasing the autonomy of Wireless Sensor Node by effective use of both DPM and DVFS methods

The detection and localization of hard-failure for Wireless Sensor Node based on online power management

Conception sous Contraintes de Sûreté de Fonctionnement et de Consommation d'énergie de Réseau de Capteurs Sans Fil

Design under Constraints of Availability and Energy for Sensor Node in Wireless Sensor Network

Virtual SoPC Rad-Hardening for Satellite Applications

Building and Using System, Algorithmic, and Architectural Power and Energy Models in the FPGA Design-Flow

Interconnect Explorer: A High-level Power Estimation Tool for On-Chip Interconnects

Using Integer Linear Programming in Test-Bench Generation for Evaluating Communication Processors

Using integer linear programming in test-bench generation for evaluating communication processors

New Directions in Interconnect Performance Optimization

Modélisation, Estimation et Optimisation de la consommation des interconnexions dans les SOC

Novel Cross-Transition Elimination Technique Improving Delay and Power Consumption for On-Chip Buses

Modélisation et estimation de la consommation des interconnexions dans les SOC

Performance estimation of communication processors using design of experiments

High-Level Power Estimation and Exploration of FPGA

A High Level SoC Power Estimation Based on IP Modeling

Building and Using System, Algorithmic, and Architectural Power and Energy Models in the FPGA Design-Flow

Interconnexions et consommation: où en sommes nous?

A FPGA Power Aware Design Flow

Méthodologie de Modélisation de la Consommation des Applications sur FPGA

Une méthode d'optimisation mémoire à haut niveau par gestion logicielle de cache (scratchpad)"

Estimation de la consommation logicielle dans un système embarqué : Etude de cas

Réduction de l'influence du placement mémoire par la synthèse de haut niveau

Méthodologie de Modélisation de la Consommation d'Applications à Haut-Niveau pour la Conception Système.

Méthodologie de Modélisation Multi-Niveau de la consommation des Applications sur FPGA.

Méthodologie de modélisation de la consommation sur FPGA : Application au VirtexE 400

Etude de la consommation de plates-formes multiprocesseurs

Méthodologie de Modélisation à Haut-niveau de la Consommation des Applications du T.D.S.I sur FPGA

A High Level Power modeling IP Methodology for SoC Design Based on FPGA Approach

Power/Energy Estimation in SoCs by Multi-Level Parametric Modeling

High Level Ageing Vectors Management for Data Intensive Applications

A Complete Methodology for Memory Optimization in DSP Applications

A Memory Aware behavioral Synthesis Tool for Real-Time VLSI Circuits

Memory aware HLS and the implementation of ageing vectors

Algorithmic level power and energy optimization for DSP applications: SoftExplorer

Power Consumption Characterization and Modeling of Embedded Memories in Xilinx Virtex 400E FPGA

Memory Accesses management during High Level Synthesis

SoftExplorer: estimation, characterization and optimization of the power and energy consumption at the algorithmic level

Functional Level Power Analysis: An Efficient Approach for Modeling the Power Consumption of Complex Processors

"High Level Ageing Vectors Management for Data Intensive Applications",

SoftExplorer: estimation of the power and energy consumption for DSP applications

A Memory Aware High Level Synthesis Tool

approche logicielle de la consommation dans les systèmes embarqués

A Memory Aware High Level Synthesis Tool

Memory Aware High-Level Synthesis for Embedded Systems

Ordonnancement sous contraintes de mémorisation : une optimisation efficace des ressources lors de la synthèse d'architecture

Contraintes mémoire et solution architecturale pour applications TDSI