Patrick Girard

457

Documents

Researcher identifiers

patrick-girard-lirmm
0000-0003-0722-8772

Presentation

Publications

	Non-Volatile Latch Designs with Node-Upset Tolerance and Recovery using Magnetic Tunnel Junctions and CMOS Aibin Yan , Litao Wang , Jie Cui , Zhengfeng Huang , Tianming Ni IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2024, 32 (1), pp.116-127. ⟨10.1109/TVLSI.2023.3323562⟩ Journal articles lirmm-04239391v1
	Two Double-Node-Upset-Hardened Flip-Flop Designs for High-Performance Applications Aibin Yan , Aoran Cao , Zhengfeng Huang , Jie Cui , Tianming Ni IEEE Transactions on Emerging Topics in Computing, 2023, 11 (4), pp.1070-1081. ⟨10.1109/TETC.2023.3317070⟩ Journal articles lirmm-04239309v1
	Analysis of resistive defects on a foundry 8T SRAM-based IMC architecture Lila Ammoura , Marie-Lise Flottes , Patrick Girard , Jean-Philippe Noël , Arnaud Virazel Microelectronics Reliability, 2023, 147, pp.115029. ⟨10.1016/j.microrel.2023.115029⟩ Journal articles hal-04129470v1
	A Highly Robust and Low-Power Flip-Flop Cell With Complete Double-Node-Upset Tolerance for Aerospace Applications Aibin Yan , Yuting He , Xiaoxiao Niu , Jie Cui , Tianming Ni IEEE Design & Test, 2023, 40 (4), pp.34-41. ⟨10.1109/MDAT.2023.3267747⟩ Journal articles lirmm-04236363v1
	Designs of Two Quadruple-Node-Upset Self-Recoverable Latches for Highly Robust Computing in Harsh Radiation Environments Aibin Yan , Zhixing Li , Jie Cui , Zhengfeng Huang , Tianming Ni IEEE Transactions on Aerospace and Electronic Systems, 2023, 59 (3), pp.2885-2897. ⟨10.1109/TAES.2022.3219372⟩ Journal articles lirmm-04236216v1
	Designs of BCD Adder Based on Excess-3 Code in Quantum-Dot Cellular Automata Aibin Yan , Runqi Liu , Jie Cui , Tianming Ni , Patrick Girard IEEE Transactions on Circuits and Systems II: Express Briefs, 2023, 70 (6), pp.2256-2260. ⟨10.1109/TCSII.2023.3237695⟩ Journal articles lirmm-04236366v1
	Designs of Array Multipliers with an Optimized Delay in Quantum-Dot Cellular Automata Aibin Yan , Xuehua Li , Runqi Liu , Zhengfeng Huang , Patrick Girard Electronics, 2023, 12 (14), pp.3189. ⟨10.3390/electronics12143189⟩ Journal articles lirmm-04239247v1
	LDAVPM: A Latch Design and Algorithm-based Verification Protected against Multiple-Node-Upsets in Harsh Radiation Environments Aibin Yan , Zhixing Li , Jie Cui , Zhengfeng Huang , Tianming Ni IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2023, 42 (6), pp.2069-2073. ⟨10.1109/TCAD.2022.3213212⟩ Journal articles lirmm-03770056v1
	Two sextuple cross-coupled SRAM cells with double-node-upset protection and cost optimization for aerospace applications Aibin Yan , Jing Xiang , Yang Chang , Zhengfeng Huang , Jie Cui Microelectronics Journal, 2023, 139, pp.105908. ⟨10.1016/j.mejo.2023.105908⟩ Journal articles lirmm-04239447v1
	All-Spin PUF: An Area Efficient and reliable PUF Design with Signature Improvement for Spin-Transfer Torque Magnetic Cell-Based All-Spin Circuits Kangwei Xu , Dongrong Zhang , Qiang Ren , Yuanqing Cheng , Patrick Girard ACM Journal on Emerging Technologies in Computing Systems, 2022, 18 (4), pp.1-20/71. ⟨10.1145/3517811⟩ Journal articles lirmm-03768916v1
	Novel Quadruple-Node-Upset-Tolerant Latch Designs with Optimized Overhead for Reliable Computing in Harsh Radiation Environments Aibin Yan , Zhelong Xu , Xiangfeng Feng , Jie Cui , Zhili Chen IEEE Transactions on Emerging Topics in Computing, 2022, 10 (1), pp.404-413. ⟨10.1109/TETC.2020.3025584⟩ Journal articles lirmm-03031709v1
	Designs of Level-Sensitive T Flip-Flops and Polar Encoders Based on Two XOR/XNOR Gates Aibin Yan , Runqi Liu , Zhengfeng Huang , Patrick Girard , Xiaoqing Wen Electronics, 2022, 11 (10), pp.1658. ⟨10.3390/electronics11101658⟩ Journal articles lirmm-03769025v1
	Quadruple and Sextuple Cross-Coupled SRAM Cell Designs With Optimized Overhead for Reliable Applications Aibin Yan , Jing Xiang , Aoran Cao , Zhihui He , Jie Cui IEEE Transactions on Device and Materials Reliability, 2022, 22 (2), pp.282-295. ⟨10.1109/TDMR.2022.3175324⟩ Journal articles lirmm-03769794v1
	A comprehensive framework for cell-aware diagnosis of customer returns Pierre D’hondt , Safa Mhamdi , Patrick Girard , Arnaud Virazel , Aymen Ladhar Microelectronics Reliability, 2022, 135, pp.114595. ⟨10.1016/j.microrel.2022.114595⟩ Journal articles lirmm-03768999v1
	A ReRAM-Based Non-Volatile and Radiation-Hardened Latch Design Aibin Yan , Shaojie Wei , Yu Chen , Zhengzheng Fan , Zhengfeng Huang Micromachines, 2022, 13 (11), pp.1802. ⟨10.3390/mi13111802⟩ Journal articles lirmm-04236275v1
	Cost-Effective and Highly Reliable Circuit Components Design for Safety-Critical Applications Aibin Yan , Zhengzheng Fan , Liang Ding , Jie Cui , Zhengfeng Huang IEEE Transactions on Aerospace and Electronic Systems, 2022, 58 (1), pp.517-529. ⟨10.1109/TAES.2021.3103586⟩ Journal articles lirmm-03380293v1
	Design of Radiation Hardened Latch and Flip-Flop with Cost-Effectiveness for Low-Orbit Aerospace Applications Aibin Yan , Aoran Cao , Zhelong Xu , Jie Cui , Tianming Ni Journal of Electronic Testing: : Theory and Applications, 2021, 37, pp.489-502. ⟨10.1007/s10836-021-05962-0⟩ Journal articles lirmm-03377194v1
	Error-Tolerant Reconfigurable VDD 10T SRAM Architecture for IoT Applications Neha Gupta , Ambika Prasad Shah , Sajid Khan , Santosh Kumar Vishvakarma , Michael Waltl Electronics, 2021, 10 (14), pp.1718. ⟨10.3390/electronics10141718⟩ Journal articles lirmm-03376967v1
	Dual-modular-redundancy and dual-level error-interception based triple-node-upset tolerant latch designs for safety-critical applications Aibin Yan , Zhihui He , Jun Zhou , Jie Cui , Tianming Ni Microelectronics Journal, 2021, 111, pp.#105034. ⟨10.1016/j.mejo.2021.105034⟩ Journal articles lirmm-03380265v1
	Improving TID Radiation Robustness of a CMOS OxRAM-Based Neuron Circuit by Using Enclosed Layout Transistors Pablo Ilha Vaz , Patrick Girard , Arnaud Virazel , Hassen Aziza IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2021, 29 (6), pp.1122-1131. ⟨10.1109/TVLSI.2021.3067446⟩ Journal articles lirmm-03376937v1
	Multi-Level Control of Resistive RAM (RRAM) Using a Write Termination to Achieve 4 Bits/Cell in High Resistance State Hassen Aziza , Said Hamdioui , Moritz Fieback , Mottaqiallah Taouil , Mathieu Moreau Electronics, 2021, 10 (18), pp.#2222. ⟨10.3390/electronics10182222⟩ Journal articles lirmm-03377249v1
	DOVA PRO: A Dynamic Overwriting Voltage Adjustment Technique for STT-MRAM L1 Cache Considering Dielectric Breakdown Effect Kangwei Xu , Dongrong Zhang , Patrick Girard , Qiang Ren , Yuanqing Cheng IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2021, 29 (7), pp.1325-1334. ⟨10.1109/TVLSI.2021.3073415⟩ Journal articles lirmm-03376949v1
	Density Enhancement of RRAMs using a RESET Write Termination for MLC Operation Hassen Aziza , Said Hamdioui , Moritz Fieback , Mottaqiallah Taouil , Mathieu Moreau Microelectronics Reliability, 2021, 126, pp.1877-1880. ⟨10.23919/DATE51398.2021.9473967⟩ Journal articles hal-03504284v1
	A Survey of Test and Reliability Solutions for Magnetic Random Access Memories Patrick Girard , Yuanqing Cheng , Arnaud Virazel , Weisheng Zhao , Rajendra Bishnoi Proceedings of the IEEE, 2021, 109 (2), pp.149-169. ⟨10.1109/JPROC.2020.3029600⟩ Journal articles lirmm-03031646v1
	Design of Double-Upset Recoverable and Transient-Pulse Filterable Latches for Low Power and Low-Orbit Aerospace Applications Aibin Yan , Yan Chen , Zhelong Xu , Zhili Chen , Jie Cui IEEE Transactions on Aerospace and Electronic Systems, 2020, 56 (5), pp.3931-3940. ⟨10.1109/TAES.2020.2982341⟩ Journal articles lirmm-03031912v1
	Quadruple Cross-Coupled Dual-Interlocked-Storage-Cells based Multiple-Node-Upset-Tolerant Latch Designs Aibin Yan , Yafei Ling , Jie Cui , Zhili Chen , Zhengfeng Huang IEEE Transactions on Circuits and Systems Part 1 Fundamental Theory and Applications, 2020, 67 (3), pp.879-890. ⟨10.1109/TCSI.2019.2959007⟩ Journal articles lirmm-02399091v1
	Cell-Aware Defect Diagnosis of Customer Returns Based on Supervised Learning Safa Mhamdi , Patrick Girard , Arnaud Virazel , Alberto Bosio , Eric Faehn IEEE Transactions on Device and Materials Reliability, 2020, 20 (2), pp.329-340. ⟨10.1109/TDMR.2020.2992482⟩ Journal articles lirmm-03031823v1
	Information Assurance through Redundant Design: A Novel TNU Error Resilient Latch for Harsh Radiation Environment Aibin Yan , Yuanjie Hu , Jie Cui , Zhili Chen , Zhengfeng Huang IEEE Transactions on Computers, 2020, 69 (6), pp.789-799. ⟨10.1109/TC.2020.2966200⟩ Journal articles lirmm-02395602v1
	A Novel Low-Cost TMR-Without-Voter Based HIS-Insensitive and MNU-Tolerant Latch Design for Space Applications Aibin Yan , Kang Yang , Jie Cui , Patrick Girard , Xiaoqing Wen IEEE Transactions on Aerospace and Electronic Systems, 2020, 56 (4), pp.2666-2676. ⟨10.1109/TAES.2019.2951186⟩ Journal articles lirmm-02395572v1
	A Survey of Testing Techniques for Approximate Integrated Circuits Marcello Traiola , Arnaud Virazel , Patrick Girard , Mario Barbareschi , Alberto Bosio Proceedings of the IEEE, 2020, 108 (12), pp.2178-2194. ⟨10.1109/JPROC.2020.2999613⟩ Journal articles lirmm-02395609v1
	Novel Speed-and-Power-Optimized SRAM Cell Designs With Enhanced Self-Recoverability From Single- and Double-Node Upsets Aibin Yan , Yang Cheng , Yuanjie Hu , Jun Zhou , Tianming Ni IEEE Transactions on Circuits and Systems I: Regular Papers, 2020, 67 (12), pp.4684-4695. ⟨10.1109/TCSI.2020.3018328⟩ Journal articles lirmm-03031784v1
	On Using Approximate Computing to Build an Error Detection Scheme for Arithmetic Circuits Bastien Deveautour , Arnaud Virazel , Patrick Girard , Valentin Gherman Journal of Electronic Testing: : Theory and Applications, 2020, 36, pp.33-46. ⟨10.1007/s10836-020-05858-5⟩ Journal articles lirmm-02395626v1
	Novel Quadruple Cross-Coupled Memory Cell Designs Protected against Single Event Upsets and Double-Node Upsets Aibin Yan , Yuanjie Hu , Jun Zhou , Jie Cui , Zhengfeng Huang IEEE Access, 2019, 7, pp.176188-176196. ⟨10.1109/ACCESS.2019.2958109⟩ Journal articles lirmm-02395589v1
	A Test Pattern Generation Technique for Approximate Circuits Based on an ILP-Formulated Pattern Selection Procedure Marcello Traiola , Arnaud Virazel , Patrick Girard , Mario Barbareschi , Alberto Bosio IEEE Transactions on Nanotechnology, 2019, 18, pp.849-857. ⟨10.1109/TNANO.2019.2923040⟩ Journal articles lirmm-02395306v1
	Scan-Chain Intra-Cell Aware Testing Aymen Touati , Alberto Bosio , Patrick Girard , Arnaud Virazel , Matteo Sonza Reorda IEEE Transactions on Emerging Topics in Computing, 2018, 6 (2), pp.278-287. ⟨10.1109/TETC.2016.2624311⟩ Journal articles lirmm-01430859v1
	Microprocessor Testing: Functional Meets Structural Test Aymen Touati , Alberto Bosio , Patrick Girard , Arnaud Virazel , Paolo Bernardi Journal of Circuits, Systems, and Computers, 2017, 26 (08), ⟨10.1142/S0218126617400072⟩ Journal articles lirmm-01718578v1
	HPET: An Efficient Hybrid Power Estimation Technique to Improve High-Level Power Characterization Arnaud Virazel , Alejandro Nocua , Alberto Bosio , Patrick Girard , Cyril Chevalier Journal of Circuits, Systems, and Computers, 2017, 26 (8), pp.#1740004. ⟨10.1142/S0218126617400047⟩ Journal articles lirmm-01718575v1
	A Cross-Level Power Estimation Technique to Improve IP Power Models Quality Alejandro Nocua , Arnaud Virazel , Alberto Bosio , Patrick Girard , Cyril Chevalier Journal of Low Power Electronics, 2017, 13 (1), pp.10-28. ⟨10.1166/jolpe.2017.1472⟩ Journal articles lirmm-01433322v1
	A Low-Cost Reliability vs. Cost Trade-Off Methodology to Selectively Harden Logic Circuits Arnaud Virazel , Imran Wali , Bastien Deveautour , Alberto Bosio , Patrick Girard Journal of Electronic Testing: : Theory and Applications, 2017, 33 (1), pp.25-36. ⟨10.1007/s10836-017-5640-6⟩ Journal articles lirmm-01718568v1
	An Effective Power-Aware At-Speed Test Methodology for IP Qualification and Characterization Kapil Juneja , Darayus Adil Patel , Rajesh Kumar Immadi , Balwant Singh , Sylvie Naudet Journal of Electronic Testing: : Theory and Applications, 2016, 32 (6), pp.721-733. ⟨10.1007/s10836-016-5621-1⟩ Journal articles lirmm-01446887v1
	A Hybrid Fault-Tolerant Architecture for Highly Reliable Processing Cores Imran Wali , Arnaud Virazel , Alberto Bosio , Patrick Girard , Serge Pravossoudovitch Journal of Electronic Testing: : Theory and Applications, 2016, 32 (2), pp.147-161. ⟨10.1007/s10836-016-5578-0⟩ Journal articles lirmm-01354746v1
	Design for Test and Diagnosis of Power Switches Miroslav Valka , Alberto Bosio , Luigi Dilillo , Patrick Girard , Arnaud Virazel Journal of Circuits, Systems, and Computers, 2016, 25 (3), pp.1640013. ⟨10.1142/S0218126616400132⟩ Journal articles lirmm-01272986v1
	A Complete Resistive-Open Defect Analysis for Thermally Assisted Switching MRAMs João Azevedo , Arnaud Virazel , Alberto Bosio , Luigi Dilillo , Patrick Girard IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2014, 22 (11), pp.2326-2335. ⟨10.1109/TVLSI.2013.2294080⟩ Journal articles lirmm-01248578v1
	Multiple Cell Upset Classification in Commercial SRAMs Georgios Tsiligiannis , Luigi Dilillo , Alberto Bosio , Patrick Girard , Serge Pravossoudovitch IEEE Transactions on Nuclear Science, 2014, 61 (4), pp.1747-1754. ⟨10.1109/TNS.2014.2313742⟩ Journal articles lirmm-01234446v1
	Evaluating a Radiation Monitor for Mixed-Field Environments based on SRAM Technology Georgios Tsiligiannis , Luigi Dilillo , Alberto Bosio , Patrick Girard , Serge Pravossoudovitch Journal of Instrumentation, 2014, 9 (5), pp.#C05052. ⟨10.1088/1748-0221/9/05/C05052⟩ Journal articles lirmm-01234448v1
	An SRAM Based Monitor for Mixed-Field Radiation Environments Georgios Tsiligiannis , Luigi Dilillo , Alberto Bosio , Patrick Girard , Serge Pravossoudovitch IEEE Transactions on Nuclear Science, 2014, 61 (4), pp.1663-1670. ⟨10.1109/TNS.2014.2299733⟩ Journal articles lirmm-01234441v1
	On the Test and Mitigation of Malfunctions in Low-Power SRAMs Leonardo B. Zordan , Alberto Bosio , Luigi Dilillo , Patrick Girard , Arnaud Virazel Journal of Electronic Testing: : Theory and Applications, 2014, 30 (5), pp.611-627. ⟨10.1007/s10836-014-5479-z⟩ Journal articles lirmm-01238443v1
	Intra-Cell Defects Diagnosis Zhenzhou Sun , Alberto Bosio , Luigi Dilillo , Patrick Girard , Serge Pravossoudovitch Journal of Electronic Testing: : Theory and Applications, 2014, 30 (5), pp.541-555. ⟨10.1007/s10836-014-5481-5⟩ Journal articles lirmm-01272964v1
	Globally Constrained Locally Optimized 3-D Power Delivery Networks Aida Todri-Sanial , Sandip Kundu , Patrick Girard , Alberto Bosio , Luigi Dilillo IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2014, 22 (10), pp.2131-2144. ⟨10.1109/TVLSI.2013.2283800⟩ Journal articles lirmm-01255754v1
	90 nm SRAM Static and Dynamic Mode Real-Time Testing at Concordia Station in Antarctica Georgios Tsiligiannis , Luigi Dilillo , Alberto Bosio , Patrick Girard , Serge Pravossoudovitch IEEE Transactions on Nuclear Science, 2014, 61 (6), pp.3389-3394. ⟨10.1109/TNS.2014.2363120⟩ Journal articles hal-04056468v1
	Dynamic Compact Model of Self-Referenced Magnetic Tunnel Junction João Azevedo , Arnaud Virazel , Alberto Bosio , Luigi Dilillo , Patrick Girard IEEE Transactions on Electron Devices, 2014, 61 (11), pp.3877-3882. ⟨10.1109/TED.2014.2355418⟩ Journal articles lirmm-01272978v1
	Dynamic Test Methods for COTS SRAMs Georgios Tsiligiannis , Luigi Dilillo , Viyas Gupta , Alberto Bosio , Patrick Girard IEEE Transactions on Nuclear Science, 2014, 61 (6), pp.3095-3102. ⟨10.1109/TNS.2014.2363123⟩ Journal articles lirmm-01234463v1
	A New Hybrid Fault-Tolerant Architecture for Digital CMOS Circuits and Systems Ahn Duc Tran , Alberto Bosio , Luigi Dilillo , Patrick Girard , Arnaud Virazel Journal of Electronic Testing: : Theory and Applications, 2014, 30 (4), pp.401-413. ⟨10.1007/s10836-014-5459-3⟩ Journal articles lirmm-01272958v1
	Uncorrelated Power Supply Noise and Ground Bounce Consideration for Test Pattern Generation Aida Todri-Sanial , Alberto Bosio , Luigi Dilillo , Patrick Girard , Arnaud Virazel IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2013, 21 (5), pp.958-970. ⟨10.1109/TVLSI.2012.2197427⟩ Journal articles lirmm-00806774v1
	Testing a Commercial MRAM under Neutron and Alpha Radiation in Dynamic Mode Georgios Tsiligiannis , Luigi Dilillo , Alberto Bosio , Patrick Girard , Aida Todri-Sanial IEEE Transactions on Nuclear Science, 2013, 60 (4), pp.2617-2622. ⟨10.1109/TNS.2013.2239311⟩ Journal articles lirmm-00805005v1
	Fast Power Evaluation for Effective Generation of Test Programs Maximizing Peak Power Consumption Paolo Bernardi , Mauricio de Carvalho , Ernesto Sanchez , Matteo Sonza Reorda , Alberto Bosio Journal of Low Power Electronics, 2013, 9 (2), pp.253-263. ⟨10.1166/jolpe.2013.1259⟩ Journal articles lirmm-00934937v1
	A Study of Tapered 3-D TSVs for Power and Thermal Integrity Aida Todri-Sanial , Sandip Kundu , Patrick Girard , Alberto Bosio , Luigi Dilillo IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2013, 21 (2), pp.306-319. ⟨10.1109/TVLSI.2012.2187081⟩ Journal articles lirmm-00806776v1
	A Layout-Aware Pattern Grading Procedure for Critical Paths Considering Power Supply Noise and Crosstalk Patrick Girard , Mohammad Tehranipoor , Junxia Ma Journal of Electronic Testing: : Theory and Applications, 2012, 28 (2), pp.201-214. ⟨10.1007/s10836-011-5268-x⟩ Journal articles lirmm-00816589v1
	Layout-Aware Pattern Evaluation and Analysis for Power-Safe Application of TDF Patterns Patrick Girard , Mohammad Tehranipoor , Hassan Salmani , Wei Zhao , Xiaoqing Wen Journal of Low Power Electronics, 2012, 8 (2), pp.248-258. ⟨10.1166/jolpe.2012.1188⟩ Journal articles lirmm-00816606v1
	Neutron-Induced Multiple Bit Upsets on Two Commercial SRAMs Under Dynamic-Stress Paolo Rech , Jean-Marc J.-M. Galliere , Patrick Girard , Alessio Griffoni , Jérôme Boch IEEE Transactions on Nuclear Science, 2012, 59 (4), pp.893-899. ⟨10.1109/TNS.2012.2187218⟩ Journal articles lirmm-00805031v1
	Analysis and Fault Modeling of Actual Resistive Defects in ATMELtm eFlash Memories Pierre-Didier Mauroux , Arnaud Virazel , Alberto Bosio , Luigi Dilillo , Patrick Girard Journal of Electronic Testing: : Theory and Applications, 2012, 28 (2), pp.215-228. ⟨10.1007/s10836-012-5277-4⟩ Journal articles lirmm-00806773v1
	Impact of Resistive-Bridging Defects in SRAM at Different Technology Nodes Renan Alves Fonseca , Luigi Dilillo , Alberto Bosio , Patrick Girard , Serge Pravossoudovitch Journal of Electronic Testing: : Theory and Applications, 2012, 28 (3), pp.317-329. ⟨10.1007/s10836-012-5291-6⟩ Journal articles lirmm-00805017v1
	Impact of Resistive-Open Defects on SRAM Error Rate Induced by Alpha Particles and Neutrons Paolo Rech , Jean-Marc J.-M. Galliere , Patrick Girard , Frédéric Wrobel , Frédéric Saigné IEEE Transactions on Nuclear Science, 2011, 58 (3), pp.855-861. ⟨10.1109/TNS.2011.2123114⟩ Journal articles lirmm-00805046v1
	SoC Yield Improvement - Using TMR Architectures for Manufacturing Defect Tolerance in Logic Cores Julien Vial , Arnaud Virazel , Alberto Bosio , Luigi Dilillo , Patrick Girard International Journal On Advances in Systems and Measurements, 2010, 3 (1/2), pp.1-10 Journal articles lirmm-00553567v1
	High Launch Switching Activity Reduction in At-Speed Scan Testing using CTX: A Clock-Gating-Based Test Relaxation and X-Filling Scheme Kohli Miyase , Hideo Furukawa , Patrick Girard , Xiaoqing Wen , Yuta Yamato IEICE Transactions on Information and Systems, 2010, E93-D (1), pp.2-9. ⟨10.1587/transinf.E93.D.2⟩ Journal articles lirmm-00406963v1
	A Comprehensive Analysis of Transition Fault Coverage and Test Power Dissipation for LOS and LOC Schemes Fangmei Wu , Luigi Dilillo , Alberto Bosio , Patrick Girard , Serge Pravossoudovitch Journal of Low Power Electronics, 2010, 6 (2), pp.359-374. ⟨10.1166/jolpe.2010.1086⟩ Journal articles lirmm-00553548v1
	A Comprehensive Framework for Logic Diagnosis of Arbitrary Defects Alberto Bosio , Patrick Girard , Serge Pravossoudovitch , Arnaud Virazel IEEE Transactions on Computers, 2010, 59 (3), pp.289-300. ⟨10.1109/TC.2009.177⟩ Journal articles lirmm-00553545v1
	Is TMR Suitable for Yield Improvement ? Julien Vial , Arnaud Virazel , Alberto Bosio , Patrick Girard , Christian Landrault IET Computers & Digital Techniques, 2009, 3 (6), pp.581-592. ⟨10.1049/iet-cdt.2008.0127⟩ Journal articles lirmm-00406961v1
	A SPICE-Like 2T-FLOTOX Core-Cell Model for Defect Injection and Faulty Behavior Prediction in eFlash Olivier Ginez , Jean-Michel Daga , Patrick Girard , Christian Landrault , Serge Pravossoudovitch Journal of Electronic Testing: : Theory and Applications, 2009, N/A, pp.127-144. ⟨10.1007/s10836-008-5096-9⟩ Journal articles lirmm-00371370v1
	Analysis of Resistive-Open Defects in SRAM Sense Amplifiers Alexandre Ney , Patrick Girard , Serge Pravossoudovitch , Arnaud Virazel , Magali Bastian Hage-Hassan IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2009, 17 (10), pp.1556-1559. ⟨10.1109/TVLSI.2008.2005194⟩ Journal articles lirmm-00371367v1
	New March Elements for Address Decoder Open and Resistive Open Fault Detection in SRAM Memories Luigi Dilillo , Patrick Girard , Serge Pravossoudovitch , Arnaud Virazel , Simone Borri Journal of Integrated Circuits and Systems, 2008, 3 (1), pp.7-12. ⟨10.29292/jics.v3i1.276⟩ Journal articles lirmm-00341793v1
	A Selective Scan Slice Encoding Technique for Test Data Volume and Test Power Reduction Nabil Badereddine , Zhanglei Wang , Patrick Girard , Krishnendu Chakrabarty , Arnaud Virazel Journal of Electronic Testing: : Theory and Applications, 2008, 24 (4), pp.353-364. ⟨10.1007/s10836-007-5053-z⟩ Journal articles lirmm-00331296v1
	Analysis and Test of Resistive-Open Defects in SRAM Pre-Charge Circuits Luigi Dilillo , Patrick Girard , Serge Pravossoudovitch , Arnaud Virazel ,

Patrick Girard

Presentation

Publications

Non-Volatile Latch Designs with Node-Upset Tolerance and Recovery using Magnetic Tunnel Junctions and CMOS

Two Double-Node-Upset-Hardened Flip-Flop Designs for High-Performance Applications

Analysis of resistive defects on a foundry 8T SRAM-based IMC architecture

A Highly Robust and Low-Power Flip-Flop Cell With Complete Double-Node-Upset Tolerance for Aerospace Applications

Designs of Two Quadruple-Node-Upset Self-Recoverable Latches for Highly Robust Computing in Harsh Radiation Environments

Designs of BCD Adder Based on Excess-3 Code in Quantum-Dot Cellular Automata

Designs of Array Multipliers with an Optimized Delay in Quantum-Dot Cellular Automata

LDAVPM: A Latch Design and Algorithm-based Verification Protected against Multiple-Node-Upsets in Harsh Radiation Environments

Two sextuple cross-coupled SRAM cells with double-node-upset protection and cost optimization for aerospace applications

All-Spin PUF: An Area Efficient and reliable PUF Design with Signature Improvement for Spin-Transfer Torque Magnetic Cell-Based All-Spin Circuits

Novel Quadruple-Node-Upset-Tolerant Latch Designs with Optimized Overhead for Reliable Computing in Harsh Radiation Environments

Designs of Level-Sensitive T Flip-Flops and Polar Encoders Based on Two XOR/XNOR Gates

Quadruple and Sextuple Cross-Coupled SRAM Cell Designs With Optimized Overhead for Reliable Applications

A comprehensive framework for cell-aware diagnosis of customer returns

A ReRAM-Based Non-Volatile and Radiation-Hardened Latch Design

Cost-Effective and Highly Reliable Circuit Components Design for Safety-Critical Applications

Design of Radiation Hardened Latch and Flip-Flop with Cost-Effectiveness for Low-Orbit Aerospace Applications

Error-Tolerant Reconfigurable VDD 10T SRAM Architecture for IoT Applications

Dual-modular-redundancy and dual-level error-interception based triple-node-upset tolerant latch designs for safety-critical applications

Improving TID Radiation Robustness of a CMOS OxRAM-Based Neuron Circuit by Using Enclosed Layout Transistors

Multi-Level Control of Resistive RAM (RRAM) Using a Write Termination to Achieve 4 Bits/Cell in High Resistance State

DOVA PRO: A Dynamic Overwriting Voltage Adjustment Technique for STT-MRAM L1 Cache Considering Dielectric Breakdown Effect

Density Enhancement of RRAMs using a RESET Write Termination for MLC Operation

A Survey of Test and Reliability Solutions for Magnetic Random Access Memories

Design of Double-Upset Recoverable and Transient-Pulse Filterable Latches for Low Power and Low-Orbit Aerospace Applications

Quadruple Cross-Coupled Dual-Interlocked-Storage-Cells based Multiple-Node-Upset-Tolerant Latch Designs

Cell-Aware Defect Diagnosis of Customer Returns Based on Supervised Learning

Information Assurance through Redundant Design: A Novel TNU Error Resilient Latch for Harsh Radiation Environment

A Novel Low-Cost TMR-Without-Voter Based HIS-Insensitive and MNU-Tolerant Latch Design for Space Applications

A Survey of Testing Techniques for Approximate Integrated Circuits

Novel Speed-and-Power-Optimized SRAM Cell Designs With Enhanced Self-Recoverability From Single- and Double-Node Upsets

On Using Approximate Computing to Build an Error Detection Scheme for Arithmetic Circuits

Novel Quadruple Cross-Coupled Memory Cell Designs Protected against Single Event Upsets and Double-Node Upsets

A Test Pattern Generation Technique for Approximate Circuits Based on an ILP-Formulated Pattern Selection Procedure

Scan-Chain Intra-Cell Aware Testing

Microprocessor Testing: Functional Meets Structural Test

HPET: An Efficient Hybrid Power Estimation Technique to Improve High-Level Power Characterization

A Cross-Level Power Estimation Technique to Improve IP Power Models Quality

A Low-Cost Reliability vs. Cost Trade-Off Methodology to Selectively Harden Logic Circuits

An Effective Power-Aware At-Speed Test Methodology for IP Qualification and Characterization

A Hybrid Fault-Tolerant Architecture for Highly Reliable Processing Cores

Design for Test and Diagnosis of Power Switches

A Complete Resistive-Open Defect Analysis for Thermally Assisted Switching MRAMs

Multiple Cell Upset Classification in Commercial SRAMs

Evaluating a Radiation Monitor for Mixed-Field Environments based on SRAM Technology

An SRAM Based Monitor for Mixed-Field Radiation Environments

On the Test and Mitigation of Malfunctions in Low-Power SRAMs

Intra-Cell Defects Diagnosis

Globally Constrained Locally Optimized 3-D Power Delivery Networks

90 nm SRAM Static and Dynamic Mode Real-Time Testing at Concordia Station in Antarctica

Dynamic Compact Model of Self-Referenced Magnetic Tunnel Junction

Dynamic Test Methods for COTS SRAMs

A New Hybrid Fault-Tolerant Architecture for Digital CMOS Circuits and Systems

Uncorrelated Power Supply Noise and Ground Bounce Consideration for Test Pattern Generation

Testing a Commercial MRAM under Neutron and Alpha Radiation in Dynamic Mode

Fast Power Evaluation for Effective Generation of Test Programs Maximizing Peak Power Consumption

A Study of Tapered 3-D TSVs for Power and Thermal Integrity

A Layout-Aware Pattern Grading Procedure for Critical Paths Considering Power Supply Noise and Crosstalk

Layout-Aware Pattern Evaluation and Analysis for Power-Safe Application of TDF Patterns

Neutron-Induced Multiple Bit Upsets on Two Commercial SRAMs Under Dynamic-Stress

Analysis and Fault Modeling of Actual Resistive Defects in ATMELtm eFlash Memories

Impact of Resistive-Bridging Defects in SRAM at Different Technology Nodes

Impact of Resistive-Open Defects on SRAM Error Rate Induced by Alpha Particles and Neutrons

SoC Yield Improvement - Using TMR Architectures for Manufacturing Defect Tolerance in Logic Cores

High Launch Switching Activity Reduction in At-Speed Scan Testing using CTX: A Clock-Gating-Based Test Relaxation and X-Filling Scheme

A Comprehensive Analysis of Transition Fault Coverage and Test Power Dissipation for LOS and LOC Schemes

A Comprehensive Framework for Logic Diagnosis of Arbitrary Defects

Is TMR Suitable for Yield Improvement ?

A SPICE-Like 2T-FLOTOX Core-Cell Model for Defect Injection and Faulty Behavior Prediction in eFlash

Analysis of Resistive-Open Defects in SRAM Sense Amplifiers

New March Elements for Address Decoder Open and Resistive Open Fault Detection in SRAM Memories

A Selective Scan Slice Encoding Technique for Test Data Volume and Test Power Reduction

Analysis and Test of Resistive-Open Defects in SRAM Pre-Charge Circuits