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Patrick Girard

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Cost-Effective and Highly Reliable Circuit Components Design for Safety-Critical Applications

Aibin Yan , Zhengzheng Fan , Liang Ding , Jie Cui , Zhengfeng Huang et al.
IEEE Transactions on Aerospace and Electronic Systems, 2022, 58 (1), pp.517-529. ⟨10.1109/TAES.2021.3103586⟩
Journal articles lirmm-03380293v1
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A comprehensive framework for cell-aware diagnosis of customer returns

Pierre D’hondt , Safa Mhamdi , Patrick Girard , Arnaud Virazel , Aymen Ladhar et al.
Microelectronics Reliability, 2022, 135, pp.114595. ⟨10.1016/j.microrel.2022.114595⟩
Journal articles lirmm-03768999v1
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Quadruple and Sextuple Cross-Coupled SRAM Cell Designs With Optimized Overhead for Reliable Applications

Aibin Yan , Jing Xiang , Aoran Cao , Zhihui He , Jie Cui et al.
IEEE Transactions on Device and Materials Reliability, 2022, 22 (2), pp.282-295. ⟨10.1109/TDMR.2022.3175324⟩
Journal articles lirmm-03769794v1
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Designs of Level-Sensitive T Flip-Flops and Polar Encoders Based on Two XOR/XNOR Gates

Aibin Yan , Runqi Liu , Zhengfeng Huang , Patrick Girard , Xiaoqing Wen et al.
Electronics, 2022, 11 (10), pp.1658. ⟨10.3390/electronics11101658⟩
Journal articles lirmm-03769025v1
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All-Spin PUF: An Area Efficient and reliable PUF Design with Signature Improvement for Spin-Transfer Torque Magnetic Cell-Based All-Spin Circuits

Kangwei Xu , Dongrong Zhang , Qiang Ren , Yuanqing Cheng , Patrick Girard et al.
ACM Journal on Emerging Technologies in Computing Systems, 2022, 18 (4), pp.1-20/71. ⟨10.1145/3517811⟩
Journal articles lirmm-03768916v1
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LDAVPM: A Latch Design and Algorithm-based Verification Protected against Multiple-Node-Upsets in Harsh Radiation Environments

Aibin Yan , Zhixing Li , Jie Cui , Zhengfeng Huang , Tianming Ni et al.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, In press, In press. ⟨10.1109/TCAD.2022.3213212⟩
Journal articles lirmm-03770056v1
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Improving TID Radiation Robustness of a CMOS OxRAM-Based Neuron Circuit by Using Enclosed Layout Transistors

Pablo Ilha Vaz , Patrick Girard , Arnaud Virazel , Hassen Aziza
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2021, 29 (6), pp.1122-1131. ⟨10.1109/TVLSI.2021.3067446⟩
Journal articles lirmm-03376937v1
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Dual-modular-redundancy and dual-level error-interception based triple-node-upset tolerant latch designs for safety-critical applications

Aibin Yan , Zhihui He , Jun Zhou , Jie Cui , Tianming Ni et al.
Microelectronics Journal, 2021, 111, pp.#105034. ⟨10.1016/j.mejo.2021.105034⟩
Journal articles lirmm-03380265v1
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Density Enhancement of RRAMs using a RESET Write Termination for MLC Operation

Hassen Aziza , Said Hamdioui , Moritz Fieback , Mottaqiallah Taouil , Mathieu Moreau et al.
Microelectronics Reliability, 2021, 126, pp.1877-1880. ⟨10.23919/DATE51398.2021.9473967⟩
Journal articles hal-03504284v1
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DOVA PRO: A Dynamic Overwriting Voltage Adjustment Technique for STT-MRAM L1 Cache Considering Dielectric Breakdown Effect

Kangwei Xu , Dongrong Zhang , Patrick Girard , Qiang Ren , Yuanqing Cheng et al.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2021, 29 (7), pp.1325-1334. ⟨10.1109/TVLSI.2021.3073415⟩
Journal articles lirmm-03376949v1
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Multi-Level Control of Resistive RAM (RRAM) Using a Write Termination to Achieve 4 Bits/Cell in High Resistance State

Hassen Aziza , Said Hamdioui , Moritz Fieback , Mottaqiallah Taouil , Mathieu Moreau et al.
Electronics, 2021, 10 (18), pp.#2222. ⟨10.3390/electronics10182222⟩
Journal articles lirmm-03377249v1
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Design of Radiation Hardened Latch and Flip-Flop with Cost-Effectiveness for Low-Orbit Aerospace Applications

Aibin Yan , Aoran Cao , Zhelong Xu , Jie Cui , Tianming Ni et al.
Journal of Electronic Testing: : Theory and Applications, 2021, 37, pp.489-502. ⟨10.1007/s10836-021-05962-0⟩
Journal articles lirmm-03377194v1
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Error-Tolerant Reconfigurable VDD 10T SRAM Architecture for IoT Applications

Neha Gupta , Ambika Prasad Shah , Sajid Khan , Santosh Kumar Vishvakarma , Michael Waltl et al.
Electronics, 2021, 10 (14), pp.1718. ⟨10.3390/electronics10141718⟩
Journal articles lirmm-03376967v1
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A Survey of Test and Reliability Solutions for Magnetic Random Access Memories

Patrick Girard , Yuanqing Cheng , Arnaud Virazel , Weisheng Zhao , Rajendra Bishnoi et al.
Proceedings of the IEEE, 2021, 109 (2), pp.149-169. ⟨10.1109/JPROC.2020.3029600⟩
Journal articles lirmm-03031646v1
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Novel Speed-and-Power-Optimized SRAM Cell Designs With Enhanced Self-Recoverability From Single- and Double-Node Upsets

Aibin Yan , Yang Cheng , Yuanjie Hu , Jun Zhou , Tianming Ni et al.
IEEE Transactions on Circuits and Systems I: Regular Papers, 2020, 67 (12), pp.4684-4695. ⟨10.1109/TCSI.2020.3018328⟩
Journal articles lirmm-03031784v1
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Design of Double-Upset Recoverable and Transient-Pulse Filterable Latches for Low Power and Low-Orbit Aerospace Applications

Aibin Yan , Yan Chen , Zhelong Xu , Zhili Chen , Jie Cui et al.
IEEE Transactions on Aerospace and Electronic Systems, 2020, 56 (5), pp.3931-3940. ⟨10.1109/TAES.2020.2982341⟩
Journal articles lirmm-03031912v1
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A Survey of Testing Techniques for Approximate Integrated Circuits

Marcello Traiola , Arnaud Virazel , Patrick Girard , Mario Barbareschi , Alberto Bosio et al.
Proceedings of the IEEE, 2020, 108 (12), pp.2178 - 2194. ⟨10.1109/JPROC.2020.2999613⟩
Journal articles lirmm-02395609v1
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A Novel Low-Cost TMR-Without-Voter Based HIS-Insensitive and MNU-Tolerant Latch Design for Space Applications

Aibin Yan , Kang Yang , Jie Cui , Patrick Girard , Xiaoqing Wen et al.
IEEE Transactions on Aerospace and Electronic Systems, 2020, 56 (4), pp.2666-2676. ⟨10.1109/TAES.2019.2951186⟩
Journal articles lirmm-02395572v1
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Cell-Aware Defect Diagnosis of Customer Returns Based on Supervised Learning

Safa Mhamdi , Patrick Girard , Arnaud Virazel , Alberto Bosio , Eric Faehn et al.
IEEE Transactions on Device and Materials Reliability, 2020, 20 (2), pp.329-340. ⟨10.1109/TDMR.2020.2992482⟩
Journal articles lirmm-03031823v1

Information Assurance through Redundant Design: A Novel TNU Error Resilient Latch for Harsh Radiation Environment

Aibin Yan , Yuanjie Hu , Jie Cui , Zhili Chen , Zhengfeng Huang et al.
IEEE Transactions on Computers, 2020, 69 (6), pp.789-799. ⟨10.1109/TC.2020.2966200⟩
Journal articles lirmm-02395602v1
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Novel Quadruple-Node-Upset-Tolerant Latch Designs with Optimized Overhead for Reliable Computing in Harsh Radiation Environments

Aibin Yan , Zhelong Xu , Xiangfeng Feng , Jie Cui , Zhili Chen et al.
IEEE Transactions on Emerging Topics in Computing, inPress, ⟨10.1109/TETC.2020.3025584⟩
Journal articles lirmm-03031709v1

Quadruple Cross-Coupled Dual-Interlocked-Storage-Cells based Multiple-Node-Upset-Tolerant Latch Designs

Aibin Yan , Yafei Ling , Jie Cui , Zhili Chen , Zhengfeng Huang et al.
IEEE Transactions on Circuits and Systems Part 1 Fundamental Theory and Applications, 2020, 67 (3), pp.879-890. ⟨10.1109/TCSI.2019.2959007⟩
Journal articles lirmm-02399091v1

On Using Approximate Computing to Build an Error Detection Scheme for Arithmetic Circuits

Bastien Deveautour , Arnaud Virazel , Patrick Girard , Valentin Gherman
Journal of Electronic Testing: : Theory and Applications, 2020, 36, pp.33-46. ⟨10.1007/s10836-020-05858-5⟩
Journal articles lirmm-02395626v1
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Novel Quadruple Cross-Coupled Memory Cell Designs Protected against Single Event Upsets and Double-Node Upsets

Aibin Yan , Yuanjie Hu , Jun Zhou , Jie Cui , Zhengfeng Huang et al.
IEEE Access, 2019, 7, pp.176188-176196. ⟨10.1109/ACCESS.2019.2958109⟩
Journal articles lirmm-02395589v1

A Test Pattern Generation Technique for Approximate Circuits Based on an ILP-Formulated Pattern Selection Procedure

Marcello Traiola , Arnaud Virazel , Patrick Girard , Mario Barbareschi , Alberto Bosio et al.
IEEE Transactions on Nanotechnology, 2019, 18, pp.849-857. ⟨10.1109/TNANO.2019.2923040⟩
Journal articles lirmm-02395306v1

Scan-Chain Intra-Cell Aware Testing

Aymen Touati , Alberto Bosio , Patrick Girard , Arnaud Virazel , Matteo Sonza Reorda et al.
IEEE Transactions on Emerging Topics in Computing, 2018, 6 (2), pp.278-287. ⟨10.1109/TETC.2016.2624311⟩
Journal articles lirmm-01430859v1

A Cross-Level Power Estimation Technique to Improve IP Power Models Quality

Alejandro Nocua , Arnaud Virazel , Alberto Bosio , Patrick Girard , Cyril Chevalier et al.
Journal of Low Power Electronics, 2017, 13 (1), pp.10-28. ⟨10.1166/jolpe.2017.1472⟩
Journal articles lirmm-01433322v1

A Low-Cost Reliability vs. Cost Trade-Off Methodology to Selectively Harden Logic Circuits

Arnaud Virazel , Imran Wali , Bastien Deveautour , Alberto Bosio , Patrick Girard et al.
Journal of Electronic Testing: : Theory and Applications, 2017, 33 (1), pp.25-36. ⟨10.1007/s10836-017-5640-6⟩
Journal articles lirmm-01718568v1

HPET: An Efficient Hybrid Power Estimation Technique to Improve High-Level Power Characterization

Arnaud Virazel , Alejandro Nocua , Alberto Bosio , Patrick Girard , Cyril Chevalier et al.
Journal of Circuits, Systems, and Computers, 2017, 26 (8), pp.#1740004. ⟨10.1142/S0218126617400047⟩
Journal articles lirmm-01718575v1

Microprocessor Testing: Functional Meets Structural Test

Aymen Touati , Alberto Bosio , Patrick Girard , Arnaud Virazel , Paolo Bernardi et al.
Journal of Circuits, Systems, and Computers, 2017, 26 (08), ⟨10.1142/S0218126617400072⟩
Journal articles lirmm-01718578v1

A Hybrid Fault-Tolerant Architecture for Highly Reliable Processing Cores

Imran Wali , Arnaud Virazel , Alberto Bosio , Patrick Girard , Serge Pravossoudovitch et al.
Journal of Electronic Testing: : Theory and Applications, 2016, 32 (2), pp.147-161. ⟨10.1007/s10836-016-5578-0⟩
Journal articles lirmm-01354746v1

An Effective Power-Aware At-Speed Test Methodology for IP Qualification and Characterization

Kapil Juneja , Darayus Adil Patel , Rajesh Kumar Immadi , Balwant Singh , Sylvie Naudet et al.
Journal of Electronic Testing: : Theory and Applications, 2016, 32 (6), pp.721-733. ⟨10.1007/s10836-016-5621-1⟩
Journal articles lirmm-01446887v1

Design for Test and Diagnosis of Power Switches

Miroslav Valka , Alberto Bosio , Luigi Dilillo , Patrick Girard , Arnaud Virazel et al.
Journal of Circuits, Systems, and Computers, 2016, 25 (3), pp.1640013. ⟨10.1142/S0218126616400132⟩
Journal articles lirmm-01272986v1

Multiple Cell Upset Classification in Commercial SRAMs

Georgios Tsiligiannis , Luigi Dilillo , Alberto Bosio , Patrick Girard , Serge Pravossoudovitch et al.
IEEE Transactions on Nuclear Science, 2014, 61 (4), pp.1747-1754. ⟨10.1109/TNS.2014.2313742⟩
Journal articles lirmm-01234446v1
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Evaluating a Radiation Monitor for Mixed-Field Environments based on SRAM Technology

Georgios Tsiligiannis , Luigi Dilillo , Alberto Bosio , Patrick Girard , Serge Pravossoudovitch et al.
Journal of Instrumentation, 2014, 9 (5), pp.#C05052. ⟨10.1088/1748-0221/9/05/C05052⟩
Journal articles lirmm-01234448v1
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Use of CCD to Detect Terrestrial Cosmic Rays at Ground Level: Altitude vs. Underground Experiments, Modeling and Numerical Monte Carlo Simulation

Georgios Tsiligiannis , Luigi Dilillo , Alberto Bosio , Patrick Girard , Serge Pravossoudovitch et al.
IEEE Transactions on Nuclear Science, 2014, 61 (6), pp.3380-3388. ⟨10.1109/TNS.2014.2365038⟩
Journal articles lirmm-01234455v1

An SRAM Based Monitor for Mixed-Field Radiation Environments

Georgios Tsiligiannis , Luigi Dilillo , Alberto Bosio , Patrick Girard , Serge Pravossoudovitch et al.
IEEE Transactions on Nuclear Science, 2014, 61 (4), pp.1663-1670. ⟨10.1109/TNS.2014.2299733⟩
Journal articles lirmm-01234441v1

Dynamic Compact Model of Self-Referenced Magnetic Tunnel Junction

João Azevedo , Arnaud Virazel , Alberto Bosio , Luigi Dilillo , Patrick Girard et al.
IEEE Transactions on Electron Devices, 2014, 61 (11), pp.3877-3882. ⟨10.1109/TED.2014.2355418⟩
Journal articles lirmm-01272978v1
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Globally Constrained Locally Optimized 3-D Power Delivery Networks

Aida Todri-Sanial , Sandip Kundu , Patrick Girard , Alberto Bosio , Luigi Dilillo et al.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2014, 22 (10), pp.2131-2144. ⟨10.1109/TVLSI.2013.2283800⟩
Journal articles lirmm-01255754v1

On the Test and Mitigation of Malfunctions in Low-Power SRAMs

Leonardo B. Zordan , Alberto Bosio , Luigi Dilillo , Patrick Girard , Arnaud Virazel et al.
Journal of Electronic Testing: : Theory and Applications, 2014, 30 (5), pp.611-627. ⟨10.1007/s10836-014-5479-z⟩
Journal articles lirmm-01238443v1
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Intra-Cell Defects Diagnosis

Zhenzhou Sun , Alberto Bosio , Luigi Dilillo , Patrick Girard , Serge Pravossoudovitch et al.
Journal of Electronic Testing: : Theory and Applications, 2014, 30 (5), pp.541-555. ⟨10.1007/s10836-014-5481-5⟩
Journal articles lirmm-01272964v1

A Complete Resistive-Open Defect Analysis for Thermally Assisted Switching MRAMs

João Azevedo , Arnaud Virazel , Alberto Bosio , Luigi Dilillo , Patrick Girard et al.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2014, 22 (11), pp.2326-2335. ⟨10.1109/TVLSI.2013.2294080⟩
Journal articles lirmm-01248578v1

A New Hybrid Fault-Tolerant Architecture for Digital CMOS Circuits and Systems

Ahn Duc Tran , Alberto Bosio , Luigi Dilillo , Patrick Girard , Arnaud Virazel et al.
Journal of Electronic Testing: : Theory and Applications, 2014, 30 (4), pp.401-413. ⟨10.1007/s10836-014-5459-3⟩
Journal articles lirmm-01272958v1

Dynamic Test Methods for COTS SRAMs

Georgios Tsiligiannis , Luigi Dilillo , Viyas Gupta , Alberto Bosio , Patrick Girard et al.
IEEE Transactions on Nuclear Science, 2014, 61 (6), pp.3095-3102. ⟨10.1109/TNS.2014.2363123⟩
Journal articles lirmm-01234463v1

Testing a Commercial MRAM under Neutron and Alpha Radiation in Dynamic Mode

Georgios Tsiligiannis , Luigi Dilillo , Alberto Bosio , Patrick Girard , Aida Todri-Sanial et al.
IEEE Transactions on Nuclear Science, 2013, 60 (4), pp.2617-2622. ⟨10.1109/TNS.2013.2239311⟩
Journal articles lirmm-00805005v1

Fast Power Evaluation for Effective Generation of Test Programs Maximizing Peak Power Consumption

Paolo Bernardi , Mauricio de Carvalho , Ernesto Sanchez , Matteo Sonza Reorda , Alberto Bosio et al.
Journal of Low Power Electronics, 2013, 9 (2), pp.253-263. ⟨10.1166/jolpe.2013.1259⟩
Journal articles lirmm-00934937v1
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A Study of Tapered 3-D TSVs for Power and Thermal Integrity

Aida Todri-Sanial , Sandip Kundu , Patrick Girard , Alberto Bosio , Luigi Dilillo et al.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2013, 21 (2), pp.306-319. ⟨10.1109/TVLSI.2012.2187081⟩
Journal articles lirmm-00806776v1
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Uncorrelated Power Supply Noise and Ground Bounce Consideration for Test Pattern Generation

Aida Todri-Sanial , Alberto Bosio , Luigi Dilillo , Patrick Girard , Arnaud Virazel et al.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2013, 21 (5), pp.958-970. ⟨10.1109/TVLSI.2012.2197427⟩
Journal articles lirmm-00806774v1

A Layout-Aware Pattern Grading Procedure for Critical Paths Considering Power Supply Noise and Crosstalk

Patrick Girard , Mohammad Tehranipoor , Junxia Ma
Journal of Electronic Testing: : Theory and Applications, 2012, 28 (2), pp.201-214. ⟨10.1007/s10836-011-5268-x⟩
Journal articles lirmm-00816589v1

Layout-Aware Pattern Evaluation and Analysis for Power-Safe Application of TDF Patterns

Patrick Girard , Mohammad Tehranipoor , Hassan Salmani , Wei Zhao , Xiaoqing Wen et al.
Journal of Low Power Electronics, 2012, 8 (2), pp.248-258. ⟨10.1166/jolpe.2012.1188⟩
Journal articles lirmm-00816606v1

Analysis and Fault Modeling of Actual Resistive Defects in ATMELtm eFlash Memories

Pierre-Didier Mauroux , Arnaud Virazel , Alberto Bosio , Luigi Dilillo , Patrick Girard et al.
Journal of Electronic Testing: : Theory and Applications, 2012, 28 (2), pp.215-228. ⟨10.1007/s10836-012-5277-4⟩
Journal articles lirmm-00806773v1

Neutron-Induced Multiple Bit Upsets on Two Commercial SRAMs Under Dynamic-Stress

Paolo Rech , Jean-Marc J.-M. Galliere , Patrick Girard , Alessio Griffoni , Jérôme Boch et al.
IEEE Transactions on Nuclear Science, 2012, 59 (4), pp.893-899. ⟨10.1109/TNS.2012.2187218⟩
Journal articles lirmm-00805031v1

Impact of Resistive-Bridging Defects in SRAM at Different Technology Nodes

Renan Alves Fonseca , Luigi Dilillo , Alberto Bosio , Patrick Girard , Serge Pravossoudovitch et al.
Journal of Electronic Testing: : Theory and Applications, 2012, 28 (3), pp.317-329. ⟨10.1007/s10836-012-5291-6⟩
Journal articles lirmm-00805017v1

Impact of Resistive-Open Defects on SRAM Error Rate Induced by Alpha Particles and Neutrons

Paolo Rech , Jean-Marc J.-M. Galliere , Patrick Girard , Frédéric Wrobel , Frédéric Saigné et al.
IEEE Transactions on Nuclear Science, 2011, 58 (3), pp.855-861. ⟨10.1109/TNS.2011.2123114⟩
Journal articles lirmm-00805046v1

A Comprehensive Framework for Logic Diagnosis of Arbitrary Defects

Alberto Bosio , Patrick Girard , Serge Pravossoudovitch , Arnaud Virazel
IEEE Transactions on Computers, 2010, 59 (3), pp.289-300. ⟨10.1109/TC.2009.177⟩
Journal articles lirmm-00553545v1

A Comprehensive Analysis of Transition Fault Coverage and Test Power Dissipation for LOS and LOC Schemes

Fangmei Wu , Luigi Dilillo , Alberto Bosio , Patrick Girard , Serge Pravossoudovitch et al.
Journal of Low Power Electronics, 2010, 6 (2), pp.359-374. ⟨10.1166/jolpe.2010.1086⟩
Journal articles lirmm-00553548v1
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High Launch Switching Activity Reduction in At-Speed Scan Testing using CTX: A Clock-Gating-Based Test Relaxation and X-Filling Scheme

Kohli Miyase , Hideo Furukawa , Patrick Girard , Xiaoqing Wen , Yuta Yamato et al.
IEICE Transactions on Information and Systems, 2010, E93-D (1), pp.2-9. ⟨10.1587/transinf.E93.D.2⟩
Journal articles lirmm-00406963v1

SoC Yield Improvement - Using TMR Architectures for Manufacturing Defect Tolerance in Logic Cores

Julien Vial , Arnaud Virazel , Alberto Bosio , Luigi Dilillo , Patrick Girard et al.
International Journal On Advances in Systems and Measurements, 2010, 3 (1/2), pp.1-10
Journal articles lirmm-00553567v1

Analysis of Resistive-Open Defects in SRAM Sense Amplifiers

Alexandre Ney , Patrick Girard , Serge Pravossoudovitch , Arnaud Virazel , Magali Bastian Hage-Hassan et al.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2009, 17 (10), pp.1556-1559. ⟨10.1109/TVLSI.2008.2005194⟩
Journal articles lirmm-00371367v1

A SPICE-Like 2T-FLOTOX Core-Cell Model for Defect Injection and Faulty Behavior Prediction in eFlash

Olivier Ginez , Jean-Michel Daga , Patrick Girard , Christian Landrault , Serge Pravossoudovitch et al.
Journal of Electronic Testing: : Theory and Applications, 2009, N/A, pp.127-144. ⟨10.1007/s10836-008-5096-9⟩
Journal articles lirmm-00371370v1

Is TMR Suitable for Yield Improvement ?

Julien Vial , Arnaud Virazel , Alberto Bosio , Patrick Girard , Christian Landrault et al.
IET Computers & Digital Techniques, 2009, 3 (6), pp.581-592. ⟨10.1049/iet-cdt.2008.0127⟩
Journal articles lirmm-00406961v1

New March Elements for Address Decoder Open and Resistive Open Fault Detection in SRAM Memories

Luigi Dilillo , Patrick Girard , Serge Pravossoudovitch , Arnaud Virazel , Simone Borri et al.
Journal of Integrated Circuits and Systems, 2008, 3 (1), pp.7-12. ⟨10.29292/jics.v3i1.276⟩
Journal articles lirmm-00341793v1

A Selective Scan Slice Encoding Technique for Test Data Volume and Test Power Reduction

Nabil Badereddine , Zhanglei Wang , Patrick Girard , Krishnendu Chakrabarty , Arnaud Virazel et al.
Journal of Electronic Testing: : Theory and Applications, 2008, 24 (4), pp.353-364. ⟨10.1007/s10836-007-5053-z⟩
Journal articles lirmm-00331296v1
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Analysis and Test of Resistive-Open Defects in SRAM Pre-Charge Circuits

Luigi Dilillo , Patrick Girard , Serge Pravossoudovitch , Arnaud Virazel , Magali Bastian Hage-Hassan et al.
Journal of Electronic Testing: : Theory and Applications, 2007, 23 (3), pp.435-444. ⟨10.1007/s10836-007-5003-9⟩
Journal articles lirmm-00194254v1

A Gated Clock Scheme for Low Power Testing of Logic Cores

Christian Landrault , Yannick Bonhomme , Arnaud Virazel , Patrick Girard , Loïs Guiller et al.
Journal of Electronic Testing: : Theory and Applications, 2006, 22 (1), pp.89-99. ⟨10.1007/s10836-006-6259-1⟩
Journal articles lirmm-00134766v1

ADOFs and Resistive-ADOFs in SRAM Address Decoders: Test Conditions and March Solutions

Patrick Girard , Luigi Dilillo , Serge Pravossoudovitch , Arnaud Virazel , Magali Bastian Hage-Hassan et al.
Journal of Electronic Testing: : Theory and Applications, 2006, 22 (3), pp.287-296. ⟨10.1007/s10836-006-7761-1⟩
Journal articles lirmm-00134769v1

An Efficient BIST Architecture for Delay Faults in the Logic Cells of Symmetrical SRAM-Based FPGAs

Patrick Girard , Serge Pravossoudovitch , Olivier Héron , Michel Renovell
Journal of Electronic Testing: : Theory and Applications, 2006, 22 (2), pp.161-172. ⟨10.1007/s10836-005-4631-1⟩
Journal articles lirmm-00135456v1

Reducing Power Dissipation in SRAM During Test

Luigi Dilillo , Paul Rosinger , Bashir Al-Hashimi , Patrick Girard
Journal of Low Power Electronics, 2006, 2 (2), pp.271-280. ⟨10.1166/jolpe.2006.062⟩
Journal articles lirmm-00137590v1
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Analysis of Dynamic Faults in Embedded-SRAMs: Implications for Memory Test

Simone Borri , Magali Bastian Hage-Hassan , Luigi Dilillo , Patrick Girard , Serge Pravossoudovitch et al.
Journal of Electronic Testing: : Theory and Applications, 2005, 21 (2), pp.169-179. ⟨10.1007/s10836-005-6146-1⟩
Journal articles lirmm-00105313v1
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Efficient March Test Procedure for Dynamic Read Destructive Fault Detection in SRAM Memories

Luigi Dilillo , Patrick Girard , Serge Pravossoudovitch , Arnaud Virazel , Simone Borri et al.
Journal of Electronic Testing: : Theory and Applications, 2005, 21 (5), pp.551-561. ⟨10.1007/s10836-005-1169-1⟩
Journal articles lirmm-00105314v1

Low Power Scan Chain Design: A Solution for an Efficient Tradeoff Between Test Power and Scan Routing

Patrick Girard , Yannick Bonhomme
Journal of Low Power Electronics, 2005, 1 (1), pp.85-95. ⟨10.1166/jolpe.2005.004⟩
Journal articles lirmm-00105357v1

Delay Fault Testing of Look-Up Tables in SRAM-Based FPGAs

Patrick Girard , Olivier Héron , Serge Pravossoudovitch , Michel Renovell
Journal of Electronic Testing: : Theory and Applications, 2005, 21 (1), pp.43-55. ⟨10.1007/s10836-005-5286-7⟩
Journal articles lirmm-00105329v1

Power-Driven Routing-Constrained Scan Chain Design

Yannick Bonhomme , Patrick Girard , Loïs Guiller , Christian Landrault , Serge Pravossoudovitch et al.
Journal of Electronic Testing: : Theory and Applications, 2004, 20 (6), pp.647-660. ⟨10.1007/s10677-004-4252-2⟩
Journal articles lirmm-00108581v1

A Ring Architecture Strategy for BIST Test Pattern Generation

Christophe Fagot , Olivier Gascuel , Patrick Girard , Christian Landrault
Journal of Electronic Testing: : Theory and Applications, 2003, 19 (3), pp.223-231. ⟨10.1023/A:1023788727542⟩
Journal articles lirmm-02273114v1

Hardware Generation of Random Single Input Change Test Sequence

René M. G. David , Patrick Girard , Christian Landrault , Serge Pravossoudovitch , Arnaud Virazel et al.
Journal of Electronic Testing: : Theory and Applications, 2002, 18 (2), pp.145-157. ⟨10.1023/A:1014941525735⟩
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High Defect Coverage with Low Power Test Sequences in a BIST Environment

Patrick Girard , Christian Landrault , Serge Pravossoudovitch , Arnaud Virazel , Hans-Joachim Wunderlich et al.
IEEE Design & Test, 2002, 19 (5), pp.44-52. ⟨10.1109/MDT.2002.1033791⟩
Journal articles lirmm-00268585v1

Survey of Low-Power Testing of VLSI Circuits

Patrick Girard
IEEE Design & Test, 2002, 19 (3), pp.82-92. ⟨10.1109/MDT.2002.1003802⟩
Journal articles lirmm-00268584v1
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Delay Fault Testing: Choosing Between Random SIC and Random MIC Test Sequences

Arnaud Virazel , René M. G. David , Patrick Girard , Christian Landrault , Serge Pravossoudovitch et al.
Journal of Electronic Testing: : Theory and Applications, 2001, 17 (3/4), pp.233-241. ⟨10.1023/A:1012259227622⟩
Journal articles lirmm-00345796v1
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A New Scan-BIST Structures to Test delay Faults in Sequential Circuits

Patrick Girard , Christian Landrault , Véronique Moreda , Serge Pravossoudovitch , Arnaud Virazel et al.
Journal of Electronic Testing: : Theory and Applications, 1999, 14, pp.95-102. ⟨10.1023/A:1008305507376⟩
Journal articles lirmm-00345797v1

A Scan-BIST Structure to Test Delay Faults in Sequential Circuits

Patrick Girard , Christian Landrault , Véronique Moreda , Serge Pravossoudovitch , Arnaud Virazel et al.
Journal of Electronic Testing: : Theory and Applications, 1999, 14 (1/2), pp.95-102. ⟨10.1023/A:1008305507376⟩
Journal articles lirmm-00345794v1
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Two 0.8 V, Highly Reliable RHBD 10T and 12T SRAM Cells for Aerospace Applications

Aibin Yan , Zhihui He , Jing Xiang , Jie Cui , Yong Zhou et al.
GLVLSI 2022 - 32nd ACM Great Lakes Symposium on VLSI, Jun 2022, Irvine, CA, United States. pp.261-266, ⟨10.1145/3526241.3530312⟩
Conference papers lirmm-03770855v1
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A Radiation-Hardened Non-Volatile Magnetic Latch with High Reliability and Persistent Storage

Aibin Yan , Liang Ding , Zhen Zhou , Zhengfeng Huang , Jie Cui et al.
ATS 2022 - 31st IEEE Asian Test Symposium, Nov 2022, Taichung, Taiwan. ⟨10.1109/ATS56056.2022.00013⟩
Conference papers lirmm-03770951v1

Configuring a Universal BIST Solution for CMOS Image Sensors

Julia Lefèvre , Philippe Debaud , Patrick Girard , Arnaud Virazel
16e Colloque National du GDR SoC², Jun 2022, Strasbourg, France
Conference papers lirmm-03988569v1
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Effective techniques for automatically improving the transition delay fault coverage of Self-Test Libraries

Riccardo Cantoro , Francesco Garau , Patrick Girard , Nima Kolahimahmoudi , Sandro Sartoni et al.
ETS 2022 - 27th IEEE European Test Symposium, May 2022, Barcelona, Spain. pp.1-2, ⟨10.1109/ETS54262.2022.9810392⟩
Conference papers lirmm-03739788v1
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A Highly Reliable and Low Power RHBD Flip-Flop Cell for Aerospace Applications

Aibin Yan , Kuikui Qian , Jie Cui , Ningning Cui , Zhengfeng Huang et al.
VTS 2022 - IEEE 40th VLSI Test Symposium, Apr 2022, San Diego, CA, United States. pp.1-6, ⟨10.1109/VTS52500.2021.9794197⟩
Conference papers lirmm-03770473v1
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On Using Cell-Aware Models for Representing SRAM Architecture

Xhesila Xhafa , Aymen Ladhar , Eric Faehn , Lorena Anghel , Gregory Di Pendina et al.
16e Colloque National du GDR SoC², Jun 2022, Strasbourg, France
Conference papers lirmm-03987914v1
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Analysis of Read Port Short Defects in an 8T SRAM-based IMC Architecture

Lila Ammoura , Marie-Lise Flottes , Patrick Girard , Jean-Philippe Noel , Arnaud Virazel et al.
16e Colloque National du GDR SoC², Jun 2022, Strasbourg, France
Conference papers lirmm-03990078v1
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Cost-Optimized and Robust Latch Hardened against Quadruple Node Upsets for Nanoscale CMOS

Aibin Yan , Shukai Song , Jixiang Zhang , Jie Cui , Zhengfeng Huang et al.
ITC-Asia 2022 - IEEE International Test Conference in Asian, Aug 2022, Taipei, Taiwan. pp.73-78, ⟨10.1109/ITCAsia55616.2022.00023⟩
Conference papers lirmm-03770182v1
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SCLCRL: Shuttling C-elements based Low-Cost and Robust Latch Design Protected against Triple Node Upsets in Harsh Radiation Environments

Aibin Yan , Zhixing Li , Shiwei Huang , Zijie Zhai , Xiangyu Cheng et al.
DATE 2022 - 25th Design, Automation and Test in Europe Conference and Exhibition, Mar 2022, Virtual, France. pp.1257-1262, ⟨10.23919/DATE54114.2022.9774665⟩
Conference papers lirmm-03769070v1
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Sextuple Cross-Coupled-DICE Based Double-Node-Upset Recoverable and Low-Delay Flip-Flop for Aerospace Applications

Aibin Yan , Yu Chen , Shukai Song , Zijie Zhai , Jie Cui et al.
GLVLSI 2022 - 32nd ACM Great Lakes Symposium on VLSI, Jun 2022, Irvine, CA, United States. pp.333-338, ⟨10.1145/3526241.3530355⟩
Conference papers