Pierre Bomel
Publications
Publications
Bi-Objective Cost Function for Adaptive Routing in Network-on-ChipIEEE Transactions on Multi-Scale Computing Systems, 2018, 4 (2), pp.177-187. ⟨10.1109/TMSCS.2018.2810223⟩ |
|
Energy Savings in Networks-on-Chip with Smart Temporal ShieldingJournal of Low Power Electronics, 2017, Journal of Low Power Electronics, 13 (3), pp.441-455. ⟨10.1166/jolpe.2017.1500⟩ |
|
Bit-Accurate Energy Estimation for Networks-on-ChipJournal of Systems Architecture, 2017, ⟨10.1016/j.sysarc.2017.05.002⟩ |
|
|
|
Hardware Discrete Channel EmulatorHigh Performance Computing and Simulation (HPCS), 2010 International Conference on, 2010, pp.452-458. ⟨10.1109/HPCS.2010.5547099⟩ |
Ultra-Fast Downloading of Partial Bitstreams Through EthernetLecture Notes in Computer Science, 2009, vol. 5455., pp.72-83 |
|
|
|
A Networked, Lightweight and Partially Reconfigurable Platform4th International Workshop, ARC 2008, London, UK, LNCS 4943, 2008, LNCS 4943 (ISSN 0302-9743, ISBN-10 3-540-78609-0, ISBN-13 978-3-540-78609-2), pp.318-323 |
A Priori Implementation Effort Estimation for HW Design Based on Independent-Path AnalysisEURASIP Journal on Embedded Systems, 2008 |
|
Constrained algorithmic IP design for system-on-chipIntegration, the VLSI Journal, 2007, 40 (2), pp.XX-XX |
|
A Formal Method for Hardware IP Design and Integration under I/O and Timing ConstraintsACM Transactions on Embedded Computing Systems (TECS), 2006, vol 5, No. 1, pp.29-53. ⟨10.1145/1132357.1132359⟩ |
|
|
|
Software radio and dynamic reconfiguration on a DSP/FPGA platformFrequenz, 2004, 58, pp.152-159 |
|
|
Real time heading sensors fusion and fault detectionChesapeake Sailing Yacht Symposium, Mar 2022, Annapolis, United States |
Energy Aware Networks-on-Chip Cortex Inspired CommunicationPATMOS 2017, Sep 2017, Thessaloniki, Greece |
|
Un Web Service sur les problèmes de transport avec des distances réelles, pour propager les algorithmes de recherche opérationnelleROADEF: Recherche Opérationnelle et d'Aide à la Décision, Feb 2017, Metz, France |
|
Crosstalk-aware link power model for Networks-on-ChipDASIP, Oct 2016, Rennes, France. ⟨10.1109/DASIP.2016.7853807⟩ |
|
Heuristic based Routing Algorithm for Network on ChipIEEE 10th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSOC), Sep 2016, Lyon, France. pp.39-45, ⟨10.1109/MCSoC.2016.43⟩ |
|
|
|
Modèle de consommation d'énergie des liens sensible au crosstalk pour les réseaux sur pucesCOMPAS, Jul 2016, Lorient, France |
Virtual Devices for Hot-Pluggable Processors17th Euromicro Conference on Digital System Design (DSD), Aug 2014, Verona, Italy |
|
Parallel deadlock detection and recovery for networks-on-chip dedicated to diffused computationsProceedings of the Euromicro DSD/SEAA conference, Sep 2013, Santander, Spain. pp.29-36 |
|
Virtual UARTs for Reconfigurable Multi-processor ArchitecturesIEEE 27th International Symposium on Parallel and Distributed Processing, May 2013, United States. pp.Pages 252-259 |
|
Comparison entre une architecture matérielle dédiée et un GP-GPU pour l'optimisationROADEF, 14ème congrès de la Société Française de Recherche Opérationnelle et d'Aide à la Décision, Feb 2013, Troyes, France |
|
|
|
Functional Validation of AADL Models via Model Transformation to SystemC with ATL5th International Workshop on Model Based Architecting and Construction of Embedded Systems ACES 2012, Sep 2012, Innsbruck, Austria |
Functional Validation of AADL Models via Model Transformation to SystemC with ATLACM/IEEE 15th International Conference on Model Driven Engineering Languages & Systems, Sep 2012, Innsbruck, Austria |
|
Hardware Discrete Channel EmulatorWorkshop on Exploitation of Hardware Accelerators (WEHA 2010), Jun 2010, France. pp.1-6 |
|
Self-reconfigurable embedded systems: from modeling to implementationEngineering of Reconfigurable Systems and Algorithms, Jul 2010, Las Vegas, Nevada, United States |
|
Networked Self-Adaptive Systems: An Opportunity for Configuring in the LargeInt. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), Jul 2009, Las Vegas, USA, France |
|
A Method for A Priori Implementation Effort Estimation for Hardware DesignIntl. Consortium for Educational Development, 2008, Malaysia |
|
|
|
High-level synthesis under I/O Timing and Memory constraints2005, pp.680-683 |
DVB-DSNG Modem High Level Synthesis in an Optimized Latency Insensitive System Context2005, pp.424-433 |
|
|
|
Synthèse Comportementale Sous Contraintes de Communication et de Placement Mémoire pour les composants du TDSIGRETSI'05 (Colloque sur le Traitement du Signal et de l'Image), 2005, LOUVAIN LA NEUVE, Belgique. pp.779-782 |
|
|
A More Efficient and Flexible DSP Design Flow from MATLAB-SIMULINK2005, Vol. V p. 61-64 |
|
|
Synchronization Processor Synthesis for Latency Insensitive SystemsDATE'05, Mar 2005, Munich, Germany. pp.896-897 |
Synchronization Processor Synthesis for Latency Insensitive Systems2005, pp.896 |
|
|
|
C- BASED RAPID PROTOTYPING FOR DIGITAL SIGNAL PROCESSINGEUSIPCO, 2005, Turkey. pp.1-4 |
Architecture de wrapper de synchronisation pour environnement de type GALS/LISJournées francophones sur l'Adéquation Algorithme Architecture, Jan 2005, Dijon, France |
|
|
|
Software radio and dynamic reconfiguration on a DSP/FPGA platform3rd Karlsruhe Workshop on Software Radios, 2004, France. pp.XX |
|
|
High Level Synthesis Assisted Rapid Prototyping for Digital Signal ProcessingIEEE International Conference on Microelectronics, Dec 2004, Tunis, Tunisia. pp.000 |
|
|
Electronic System Level to Hw/Sw Design Flow2004, pp.1-6 |
|
|
Memory Accesses management during High Level SynthesisIEEE ACM CO-DESign symposium and International Symposium on System Synthesis, 2004, stockholm, Sweden. pp.42-47 |
|
|
Networks-on-Chip Cortex Inspired Communication To Reduce Energy ConsumptionDesign Automation Conference (DAC 2017), Jun 2017, Austin, TX, United States. , Design Automation Conference, DAC 2017 |
|
|
A bit-accurate power estimation simulator for NoCsDATE 2017 Design Automation and Test in Europe, Mar 2017, Lausanne, Switzerland. , Design Automation and Test in Europe |
|
|
Orcc's Compa-Backend demonstrationConference on Design and Architectures for Signal and Image Processing, Demo Night, Oct 2014, Madrid, Spain. 2014 |
End-to-End Bitstreams Repository Hierarchy for FPGA Partially Reconfigurable SystemsGuy Gogniat, Dragomir Milojevic, Adam Morawiec, Ahmet Erdogan. Algorithm-Architecture Matching for Signal and Image Processing, Springer, pp.171-194, 2011, Lecture Notes in Electrical Engineering |
|
∂ GAUT: A High-Level Synthesis Tool for DSP applicationsPhilippe Coussy & Adam Morawiec. High-Level Synthesis: From Algorithm to Digital Circuits, Springer, pp.147-170, 2008 |
|
GAUT: A High-Level Synthesis Tool for DSP ApplicationsHigh-Level Synthesis : From Algorithm to Digital Circuit, Springer, 2008 |
Procédé de reconfiguration d'un ensemble de composants d'un circuit électronique, système de reconfiguration et procédé de transmission de données correspondantsFrance, N° de brevet: FR 0850641. 2008 |
|
|
Une Plate-Forme Légère Reconfigurable Partiellement à Distance2008 |
|
|
Bitstreams Repository Hierarchy for FPGA Partially Reconfigurable Systems2008 |
|
|
Plate-forme de prototypage rapide fondée sur la synthèse de haut niveau pour applications de radiocommunications.Micro et nanotechnologies/Microélectronique. Université de Bretagne Sud, 2004. Français. ⟨NNT : ⟩ |