Pirouz Bazargan Sabet
Publications
Publications
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Smart security management in secure devicesJournal of Cryptographic Engineering, 2016, ⟨10.1007/s13389-016-0143-4⟩ |
Power grid redundant path contribution in system on chip (SoC) robustness against electromigrationMicroelectronics Reliability, 2014, 54 (9-10), pp.1702--1706. ⟨10.1016/j.microrel.2014.07.016⟩ |
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Power Noise Measurements of Cryptographic VLSI Circuits Regarding Side-Channel Information LeakageIEICE Transactions on Electronics, 2014, E97.C (4), pp. 272-279 |
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A Simplified Circuit to Model RC InterconnectWSEAS Transactions on circuits and systems, 2004, 3 (3), pp.431-436 |
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A Power-Efficient Attention-Infused CNN Hardware Accelerator for RF Spectrum MonitoringIEEE International Symposium on Circuits and Systems, May 2025, London, United Kingdom |
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SMART SECURITY MANAGEMENT IN SECURE DEVICESPROOFS: Security Proofs for Embedded Systems, Sep 2015, Saint-Malo, France |
Identifying Signal Correlations Using Discrete Event SimulationIEEE International New Circuits and Systems Conference, Jun 2013, Paris, France. pp.349-352, ⟨10.1109/NEWCAS.2013.6573646⟩ |
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Redundancy Method to assess Electromigration Lifetime in power grid designIEEE International Interconnect Technology Conference (IITC),, Jun 2013, Kyoto, Japan. pp.81-83, ⟨10.1109/IITC.2013.6615570⟩ |
On-Chip Power Noise Measurements of Cryptographic VLSI Circuits and Interpretation for Side-Channel AnalysisInternational Symposium on Electromagnetic Compatibility (EMC Europe), Sep 2013, Brugge, Belgium. pp.405-410 |
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Measurement of side-channel information from cryptographic devices on security evaluation platform: Demonstration of SPACES projectSICE Annual Conference, Aug 2012, Akita, Japan |
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Implementation of complex strategies of security in secure embedded systemsNTMS 2011 - 4th IFIP International Conference on New Technologies, Mobility and Security, Feb 2011, Paris, France. pp.1-5, ⟨10.1109/NTMS.2011.5721145⟩ |
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Management of the security in smart secure devicesSSI 2010 - Smart Systems Integration, Mar 2011, Dresden, Germany. pp.1-9 |
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Smart On SmartColloque « Systèmes embarqués, sécurité et sûreté de fonctionnement », Dec 2010, Toulouse, France |
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SOS An innovative secure system architectureCryptarchi, Jun 2010, Paris, France |
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A methodology for Analysis of Voltage Drop in VLSI Digital CircuitsInternational Conference on Modeling, Simulation and Control (ICMSC'2010), Nov 2010, Cairo, Egypt |
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Formal Verification of Timed VHDL ProgramsForum on Specification & Design Languages, FDL 2010, Sep 2010, Southampton, United Kingdom. pp.80-85, ⟨10.1049/ic.2010.0133⟩ |
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Strategy Of Security on Smart On SmartPACA Security Trends In embedded Security, Jun 2010, Gardanne, France |
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A Novel Method to Determine the RC Interconnect Circuit OutputsDCIS International Conference on Design of Circuits and Integrated Systems, Nov 2008, Grenoble, France |
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Modeling the Effects of Input Slew Rate and Temporal Proximity of Input Transitions in Event-Driven SimulationSSST IEEE Southeastern Symposium on System Theory, Mar 2006, Cookeville, Tenessess, United States. pp.185-189, ⟨10.1109/SSST.2006.1619069⟩ |
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Capturing RC-Interconnect Effect in Crosstalk AnalysisMIXDES 2005 - 12th International conference on Mixed Design of Integrated Circuits and Systems, Jun 2005, Krakow, Poland. pp.309-314 |
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Splitting of RC-Network for Accurate Model ReductionICM 2004 - 16th International Conference on Microelectronics, Dec 2004, Tunis, Tunisia. pp.734-737, ⟨10.1109/ICM.2004.1434771⟩ |
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Determining The Analytic Waveform of an RC-Circuit OutputMIXDES Mixed Design of Integrated Circuits and Systems, Jun 2004, Szczecin, Poland. pp.363-368 |
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Using Symbolic Simulation to Exhibit Worst Case Crosstalk4th IEEE Latin-American Test Workshop (LATW'03), Feb 2003, Natal, Brazil. pp.264-268 |
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An Event-Driven Approach to Crosstalk Noise Analysis36th Annual Simulation Symposium (ANSS'36), Mar 2003, Orlando, FL, United States. pp.319-326, ⟨10.1109/SIMSYM.2003.1192829⟩ |
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Conception d'un outil d'évaluation des bruits diaphoniques dans les circuits submicroniquesVèmes Journées Nationales du Réseau Doctoral de Micro-électronique (JNRDM'2002), Apr 2002, Grenoble, France |
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A MOS Transistor Model for Peak Voltage Calculation of Crosstalk Noise9th International Conference on Electronics, Circuits and Systems, Sep 2002, Dubrovnick, Croatia. pp.773-776, ⟨10.1109/ICECS.2002.1046284⟩ |
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Structuration des données dans les outils de vérification back-endTroisième colloque du GDR CAO de circuits et systèmes intégrés, 2002, Paris, France. pp.129-132 |
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Modèle du transistor MOS à canal court en vue de l'évaluation du bruit de diaphonie dans les circuits submicroniquesTroisième colloque du GDR CAO de circuits et systèmes intégrés, 2002, Paris, France. pp.125-128 |
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Modèle d'évaluation du bruit de diaphonie pour les technologies submicroniquesIVèmes Journées Nationales du Réseau Doctoral de Micro-électronique (JNRDM'2001), Apr 2001, Strasbourg, France. pp.188-189 |
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An Approach to Mapping the Timing Behavior of VLSI Circuits on Emulators12th IEEE International Workshop on Rapid System Prototyping, Jun 2001, Monterey, California, United States. pp.168-173, ⟨10.1109/IWRSP.2001.933856⟩ |
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Modeling Croostalk Noise for Deep Submicron Verification ToolsDesign Automation and Test in Europe Conference (DATE'2001), Mar 2001, Munich, Germany. pp.530-534, ⟨10.1109/DATE.2001.915074⟩ |
A Model for Crosstalk Evaluation in Deep Submicron ProcessesInternational Symposium on Quality Electronic Design (ISQED'2001), Mar 2001, San Jose, California, United States. pp.139-144, ⟨10.1109/ISQED.2001.915218⟩ |
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An Example of Practice Based Engineering Education : the Design of a Microprogrammed MIPS Processor with the Alliance CAD SystemComputer Aided Learning In Engineering (CALIE'2001), Nov 2001, Tunis, Tunisia. pp.47-50 |
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Timed simulation of VLSI circuits using a FPGA netApplied Informatics (IASTED AI 2000), May 2000, Innsbruck, Austria |
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Simulation logico temporelle de circuits VLSI à l'aide d'un réseau de FPGAColloque CAO de Circuits Intégrés et Systèmes GDR 732, May 1999, Aix-en-Provence, France |
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Interactive Learning of Processor Architecture5th International Conference on Computer Aided Engineering Education (CAEE'99), 1999, Sofia, Bulgaria. pp.123-129 |
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CRISE : Un Outil d'Evaluation des Risques dus à la Diaphonie dans les Circuits Intégrés fortement Sub-MicroniquesColloque CAO de Circuits Intégrés et Systèmes GDR 732, May 1999, Aix-en-Provence, France |
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Circuit Disassembly for Verification and functional Abstraction of CMOS CircuitsSophia Antipolis forum on MicroElectronics (SAME'98), Oct 1998, Sophia Antipolis, France. pp.60-63 |
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Efficient Partitioning Method for Distributed Logic Simulation of VLSI Circuits31st Annual Simulation Symposium, Apr 1998, Boston, MA, United States. pp.196-201, ⟨10.1109/SIMSYM.1998.668488⟩ |
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Using Node Replication to Improve Circuit's Partition in Distributed Logic Simulation12th European Simulation Multiconference, Jun 1998, Manchester, United Kingdom. pp.235-237 |
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YAGLE, a Second generation Functional Abstractor for CMOS VLSI Circuits10th International Conference on Microelectronics (ICM'98), Dec 1998, Monastir, Tunisia. pp.265-268, ⟨10.1109/ICM.1998.825615⟩ |
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Méthodes Probabilistes pour l'Evaluation de la Consommation des Circuits Intégrés VLSI1er Colloque CAO de Circuits Intégrés et Systèmes, Jan 1997, Grenoble, France. pp.116-119 |
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Méthodes Probabilistes et Problèmes de Corrélations pour l'Evaluation de la Consommation des Circuits VLSIJournées Faible Tension Faible Consommation, Nov 1997, Paris, France. pp.131-134 |
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Un Outil d'Evaluation de la Consommation Basée sur l'Extraction d'un Réseau de Portes Caractérisées1er Colloque CAO de Circuits Intégrés et Systèmes, Jan 1997, Grenoble, France. pp.128-131 |
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SWISSE: A Fast Switch-Level Timing Simulator with Slope Effects for Large Digital MOS Circuits4th IEEE International Conference on Electronics Circuits and Systems (ICECS'97), Dec 1997, Cairo, Egypt. pp.875-879 |
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Technique de Simulation Event-Driven en Vue d'une Simulation Mixte Efficace1er Colloque CAO de Circuits Intégrés et Systèmes, Jan 1997, Grenoble, France. pp.22-25 |