Roselyne Chotin
59
Documents
Publications
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Optimisation de contre-mesure à l'insertion de Hardware Trojan22ème Conférence ROADEF de la société Française de Recherche Opérationnelle et Aide à la Décision, Apr 2021, Mulhouse, France
Conference papers
cea-03463925v1
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FPGA Acceleration of the Horn and Schunck Hierarchical algorithmInternational Symposium on Circuits and Systems (ISCAS), May 2021, Daegu, South Korea. ⟨10.1109/ISCAS51556.2021.9401068⟩
Conference papers
hal-03330803v1
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Mathematical modelling of Logic Locking against the insertion of Hardware Trojan in an Intregated Circuit31 European conference on operational research, Jul 2021, Athènes, Greece
Conference papers
cea-03463941v1
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Toward an Implementation Modeling Methodology for Designing SCA resilient Cryptographic Circuits2021 16th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS), Jun 2021, Montpellier, France. pp.1-4, ⟨10.1109/DTIS53253.2021.9505109⟩
Conference papers
hal-03650043v1
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Virtual Prototyping of Open Source Heterogeneous Systems with an Open Source Framework Featuring SystemC MDVP Extensions2020 Forum for Specification and Design Languages (FDL), Sep 2020, Kiel, Germany. pp.1-8, ⟨10.1109/FDL50818.2020.9232947⟩
Conference papers
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Model-Based Virtual Prototyping of CPS: Application to Bio-Medical DevicesMODELSWARD 2020: Model-Driven Engineering and Software Development, Feb 2020, Valletta, Malta. pp.74-96, ⟨10.1007/978-3-030-67445-8_4⟩
Conference papers
hal-03161772v1
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High-level Partitioning and Design Space Exploration for Cyber Physical SystemsModelsward 2020 - 8th International Conference on Model-Driven Engineering and Software Development, Feb 2020, Valletta, Malta. pp.84-91, ⟨10.5220/0009171600840091⟩
Conference papers
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A HDL Generator for Flexible and Efficient Finite-Field Multipliers on FPGAsWAIFI 2020 - 8th International Workshop on Arithmetic of Finite Fields, Jul 2020, Rennes, France. pp.75-91, ⟨10.1007/978-3-030-68869-1_4⟩
Conference papers
hal-03650044v1
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MixLock: Securing Mixed-Signal Circuits via Logic LockingDesign, Automation and Test in Europe (DATE 2019), Mar 2019, Florence, Italy. pp.84-89
Conference papers
hal-02094516v1
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RISC-V design using Free Open Source Softwarethe RISC-V Week, Oct 2019, Paris, France
Conference papers
hal-02316711v1
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Using Timing-Driven Inter-FPGA Routing for Multi-FPGA Prototyping ExplorationEuromicro Conference on Digital System Design (DSD), Aug 2016, Limassol, Cyprus. pp.641-645, ⟨10.1109/DSD.2016.93⟩
Conference papers
hal-01406787v1
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Inter-FPGA Routing Environment for Performance Exploration of Multi-FPGA SystemsRapid System Prototyping (RSP), Oct 2016, Pittsburgh, United States. pp.1-6
Conference papers
hal-01406803v1
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AEGIS-Based Efficient Solution for Secure Reconfiguration of FPGAsCryptography and Security in Computing Systems, Jan 2016, Prague, Czech Republic. pp.37-40, ⟨10.1145/2858930.2858937⟩
Conference papers
hal-01259069v1
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Multiple FPGAs based prototyping and debugging with complete design flowIDT 2016 - 11th International Design & Test Symposium, Dec 2016, Hammamet, Tunisia. pp.171-176, ⟨10.1109/IDT.2016.7843035⟩
Conference papers
hal-01657908v1
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Impact of defect tolerance techniques on the criticality of a SRAM-based Mesh of Cluster FPGAReConFig 2014 - International Conference on ReConFigurable Computing and FPGAs, Dec 2014, Cancun, Mexico. pp.1-6, ⟨10.1109/ReConFig.2014.7032508⟩
Conference papers
hal-01162066v1
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A reference-based specification tool for creating reliable library development specifications12th International New Circuits and Systems Conference, NEWCAS 2014, Jun 2014, Trois-Rivieres, QC, Canada. pp.133-136, ⟨10.1109/NEWCAS.2014.6934001⟩
Conference papers
hal-01217236v1
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Improve defect tolerance in a cluster of a SRAM-based Mesh of Cluster FPGA using hardware redundancyFPL 2014 - 24th International Conference on Field Programmable Logic and Applications, Sep 2014, Munich, Germany. pp.1-4, ⟨10.1109/FPL.2014.6927389⟩
Conference papers
hal-01162011v1
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Impact of Cluster Size on Routability, Testability and Robustness of a Cluster in a Mesh FPGAIEEE Computer Society Annual Symposium on VLSI (ISVLSI'14), Jul 2014, Tampa, FL, United States. pp.553-558, ⟨10.1109/ISVLSI.2014.66⟩
Conference papers
hal-01400630v1
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FPGA-Based High Performance AES-GCM Using Efficient Karatsuba Ofman Algorithm10th International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications, ARC 2014, Apr 2014, Vilamoura, Portugal. pp.13-24, ⟨10.1007/978-3-319-05960-0_2⟩
Conference papers
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Lightweight and Compact Solutions for Secure Reconfiguration of FPGAsInternational Conference on Reconfigurable Computing and FPGAs, Dec 2013, Cancun, Mexico. pp.1-4, ⟨10.1109/ReConFig.2013.6732304⟩
Conference papers
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Efficient Multilevel Interconnect Topology for Cluster-based Mesh FPGA ArchitectureReConFig 2013 - International Conference on Reconfigurable Computing and FPGAs, Dec 2013, Cancun, Mexico. pp.1-6, ⟨10.1109/ReConFig.2013.6732282⟩
Conference papers
hal-00987368v2
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Efficient State-Dependent Power Model for Multi-bit Flip-Flop BanksIEEE International Midwest Symposium on Circuits and Systems, Aug 2013, Columbus, United States. pp.461-464, ⟨10.1109/MWSCAS.2013.6674685⟩
Conference papers
hal-00913885v1
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A formalism of the specifications for library developmentIEEE International System-on-Chip Conference, Sep 2013, Erlangen, Germany. pp.307-312, ⟨10.1109/SOCC.2013.6749706⟩
Conference papers
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Improved Method for Parallel AES-GCM Cores Using FPGAsReConFig 2013 - International Conference on Reconfigurable Computing and FPGAs, Dec 2013, Cancun, Mexico. pp.1-4, ⟨10.1109/ReConFig.2013.6732299⟩
Conference papers
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Protecting FPGA Bitstreams Using Authenticated Encryption11th IEEE International Conference of New Circuits and Systems (NEWCAS), Jun 2013, Paris, France. pp.1-4, ⟨10.1109/NEWCAS.2013.6573635⟩
Conference papers
hal-01017823v2
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Formalisme de la spécification de la plateforme de conception pour le développement de la bibliothèqueJournees Nationales du Reseau Doctoral de Micro-electronique, 2013, Grenoble, France. pp.1-4
Conference papers
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High Speed Authenticated Encryption for Slow Changing Key Applications Using Reconfigurable DevicesWireless Days (WD), 2013 IFIP, Nov 2013, Valencia, Spain. pp.1 - 6, ⟨10.1109/WD.2013.6686460⟩
Conference papers
hal-01017858v2
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A Defect-tolerant Cluster in a Mesh SRAM-based FPGAInternational Conference on Field-Programmable Technology (FPT), Dec 2013, Kyoto, Japan. pp.434-437, ⟨10.1109/FPT.2013.6718407⟩
Conference papers
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Générateur d'Architecture de FPGAColloque GDR SOC-SIP, Jun 2012, Paris, France. pp.1-3
Conference papers
hal-00987369v1
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Synthesis and Optimization of Quantum Boolean Circuit Using the Truth Table MethodInternational Workshop on Number Theory, Codes, Cryptography and Communication Systems (NTCCCS), Apr 2012, Oujda, Morocco. pp.192-197
Conference papers
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The Effect of S-box Design on Pipelined AES Using FPGAsColloque GDR SOC-SIP, Jun 2012, Paris, France. pp.1-4
Conference papers
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Efficient Parallel-Pipelined GHASH for Message AuthenticationInternational Conference on Reconfigurable Computing and FPGAs (ReConFig 2012), Dec 2012, Cancun, Mexico. pp.1 - 6, ⟨10.1109/ReConFig.2012.6416742⟩
Conference papers
hal-01017807v1
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Stratus: Free design of highly parametrized VLSI modules interoperable with commercial toolsISQED 2011 - 12th International Symposium on Quality Electronic Design, Mar 2011, Santa Clara, CA, United States. pp.502-507, ⟨10.1109/ISQED.2011.5770774⟩
Conference papers
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Quantum circuits design and simulationThe First International Conference on "Research to Applications & Markets" (RAM 2011), Jun 2011, Monastir, Tunisia. pp.115-115
Conference papers
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Design and FPGA Implementation of Modular Multiplication Methods Using Cellular AutomataDTIS IEEE International Conference on Design & Test of Integrated Systems in Nanoscale Technology, Mar 2010, Hammamet, Tunisia. pp.1-5, ⟨10.1109/DTIS.2010.5487586⟩
Conference papers
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Modélisation et simplification de circuits quantiquesMateriaux 2010, Nov 2010, Mahdia, Tunisia. pp.2-2
Conference papers
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Arithmetic Data path Optimization using Borrow-Save RepresentationISVLSI IEEE Computer Society Annual Symposium on Emerging VLSI, Apr 2008, Montpellier, France. pp.4-9, ⟨10.1109/ISVLSI.2008.29⟩
Conference papers
hal-01265632v1
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Automatic Allocation of Redundant Operators in Arithmetic Data path OptimizationDASIP IEEE International Conference on Design and Architectures for Signal and Image Processing, Nov 2008, Bruxelles, Belgium. pp.176-183
Conference papers
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Data Path Optimization using Redundant Arithmetic and Pattern MatchingWorkshop on Design and Architectures for Signal and Image Processing (DASIP'2007), Nov 2007, Grenoble, France. pp.281-288
Conference papers
hal-01265633v1
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Mapping an obstacles detection, stereo vision-based, software application on a multi-processor system-on-chipIV 2006 - IEEE Intelligent Vehicles Symposium, Jun 2006, Tokyo, Japan. pp.370-376, ⟨10.1109/IVS.2006.1689656⟩
Conference papers
hal-00103535v1
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Stratus : Un environnement de développement de circuitsJP CNFM Journées pédagogiques du CNFM, 2006, Saint-Malo, France. pp.57-61
Conference papers
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MP-SoC Architecture for an Obstacle Detection Application in Pre-Crash Situation2nd International Workshop on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC'06), Jul 2006, Montpellier, France. pp.24-30
Conference papers
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On the computation of the CESTAC functionReal Numbers and Computers 5 (RNC5), Sep 2003, Lyon, France. pp.247-260
Conference papers
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Hardware implementation of discrete stochastic arithmetic6th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS'03), 2003, Poznan, Poland. pp.57-64
Conference papers
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Hardware implementation of the CESTAC method10th GAMM - IMACS International Symposium on Scientific Computing Computer Arithmetic and Validated Numerics (SCAN'2002), Sep 2002, Paris, France. pp.162-162
Conference papers
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Une unité de calcul flottant utilisant l'arithmétique stochastiqueVèmes Journées Nationales du Réseau Doctoral de Micro-électronique (JNRDM'2002), 2002, Grenoble, France. pp.217-218
Conference papers
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Implantation matérielle d'une méthode de contrôle des erreurs d'arrondi de calculTroisième colloque du GDR CAO de circuits et systèmes intégrés, 2002, Paris, France. pp.63-66
Conference papers
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Hardware implementation of a method to control round-off errors6th WSEAS International Multiconference on Circuits Systems Communications and Computers (CSCC'2002), Jul 2002, Rethymnon, Greece. pp.157-162
Conference papers
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A Floating-Point Unit using stochastic arithmetic compliant with the IEEE-754 standard9th IEEE International Conference on Electronics Circuits and Systems (ICECS'2002), Sep 2002, Dubrovnik, Croatia. pp.603-606, ⟨10.1109/ICECS.2002.1046241⟩
Conference papers
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Use of Redundant Arithmetic on Architecture and Design of a High Performance DCT Macro-bloc Generator15th Design of Circuits and Integrated Systems Conference (DCIS), 2000, Montpellier, France. pp.428-433
Conference papers
hal-01265641v1
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Architectures matérielles pour l'arithmétique stochastique discrèteArithmétique des ordinateurs. Université Pierre et Marie Curie (Paris, France), 2003. Français. ⟨NNT : ⟩
Theses
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Towards high performance GHASH for pipelined AES-GCM using FPGAsACM/SIGDA International Symposium on Field-Programmable Gate Arrays, FPGA '14, Feb 2014, Monterey, CA, United States. ACM, pp.242-242, 2014, ⟨10.1145/2554688.2554709⟩
Conference poster
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