Thierry Grandpierre
Présentation
Thèmes de recherche Responsabilités Autres pages
Publications
Publications
Procédé de calcul d’un pire temps de transmission, programme d’ordinateur et système informatique associésFrance, N° de brevet: 2312310 (n°de dépôt). 2023 |
|
Dispositif médical en radiologie interventionnelle de guidage temps réel d'une aiguille médicale d'opération dans un volumeFrance, Patent n° : EP3682808A1. 2019, pp.15 |
|
Dispositif et procédé de projection d'images sur des écrans mobilesFrance, Patent n° : FR2991787A1. 2012, pp.18 |
Apprendre en s'amusant ! Quand l'expérience de visite muséale se vit au travers d'une application gamifiéeCongrès de l'Association Française du Marketing, Université de Lille, May 2025, Lille, France |
|
Multi-Criteria Optimization of Distributed Real-Time Network Topologies2024 IEEE 27th International Symposium on Real-Time Distributed Computing (ISORC), May 2024, Tunis, Tunisia. pp.1-11, ⟨10.1109/ISORC61049.2024.10551327⟩ |
|
|
|
A New Modelling Framework for Coarse-Grained Programmable ArchitecturesCompas 2020, Jun 2021, Lyon, France |
Modelling and Mapping Framework for Coarse-GrainedProgrammable Architectures14th Summer School on Modelling and Verification of Parallel Processes, Jun 2020, (on-line), France |
|
|
|
A Mapping Methodology for Coarse-Grained Pipelined Configurable Architectures14th Workshop on Models and Algorithms for Planning and Scheduling Problems (MAPSP 2019), Jun 2019, Renesse, Netherlands |
|
|
An hypervisor approach for mixed critical real-time UAV applications2019 IEEE International Conference on Pervasive Computing and Communications Workshops (PerCom Workshops), Mar 2019, Kyoto, France. pp.985-991, ⟨10.1109/PERCOMW.2019.8730705⟩ |
|
|
A New Mapping Methodology for Coarse-Grained Programmable Systolic Architectures22nd International Workshop on Software and Compilers for Embedded Systems (SCOPES 2019), May 2019, St Goar, Germany. ⟨10.1145/3323439.3323982⟩ |
|
|
A mapping tool for configurable pipeline co-processorsColloque National du GDR SoC-SiP, GDR-SOC-SIP, Jun 2018, Paris, France |
|
|
Real-time H264/AVC high definition video encoder on a multicore DSP TMS320C66782015 International Conference on Computer Vision and Image Analysis Applications (ICCVIA), Jan 2015, Sousse, Tunisia. ⟨10.1109/ICCVIA.2015.7351893⟩ |
Automatic Hardware/Software interface generation for SynDEx-mixteATSIP 2014, Mar 2014, Sousse, Tunisia. pp.512-516, ⟨10.1109/ATSIP.2014.6834668⟩ |
|
|
|
GOP level parallelism implementation for real-time H264/AVC video encoder on multicore DSP TMS320C64722014 6th European Embedded Design in Education and Research Conference (EDERC), Sep 2014, Milano, France. ⟨10.1109/EDERC.2014.6924378⟩ |
|
|
GOP level parallelism implementation for real-time H264/AVC video encoder on multicore DSP TMS320C6472EDERC 2014, IEEE, EURASIP, Nov 2014, Milan, Italy. pp.152-156, ⟨10.1109/EDERC.2014.6924378⟩ |
|
|
Optimisations structurelles et matérielles de l'encodeur vidéo H264/AVC sur un seul coeur d'un DSP multicoeurs TMS320C6472GRETSI 2013 (Symposium on Signal and Image Processing), 2013, BREST, France |
|
|
Optimisations structurelles et matérielles de l'encodeur vidéo H264/AVC sur un seul coeur d'un DSP multicoeurs TMS320C6472gretsi, Sep 2013, Brest, France |
Latency and power optimization in AAA methodology for integrated circuitsICECS 2010, IEEE, Dec 2010, Athens, Greece. pp.639-642, ⟨10.1109/ICECS.2010.5724593⟩ |
|
Parallel Algorithm for Concurrent Computation of Connected Component TreeAdvanced Concepts for Intelligent Vision Systems (ACIVS'08), Oct 2008, France. pp.230-241 |
|
AAA and SynDEx-Ic: A Methodology and a Software Framework for the Implementation of Real-Time Applications onto Reconfigurable CircuitsInternational Embedded Systems Symposium, 2007, France. 10pp |
|
A rapid prototyping methodology to implement and optimizing image processing algorithms for FPGAsIS&T / SPIE, Symposium on Electronic Imaging Science and Technologies, Real-Time Imaging IX Conference, 2006, San Jose, USA, France. 10pp |
|
|
|
From Algorithm and Architecture Specifications to Automatic Generation of Distributed Real-Time Executives: a Seamless Flow of Graphs Transformations2003 1st IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE 2003), Jun 2003, Mont Saint Michel, France. ⟨10.1109/MEMCOD.2003.1210097⟩ |
A joystick driving algorithm with a collision stop feature on an electric vehicle (Cycab)IEEE Intelligent Vehicle Symposium 2002, Jun 2002, Versailles, France. pp.501-506, ⟨10.1109/IVS.2002.1188000⟩ |
|
From Algorithm Graph Specification to Automatic Synthesis of FPGA Circuit: A Seamless Flow of Graphs TransformationsField Programmable Logic and Application, 13th International Conference, Sep 2003, Lisbon, Portugal. pp.934-943, ⟨10.1007/978-3-540-45234-8_90⟩ |
|
PROMPT : A mapping environment for telecom applications on System on a ChipInternational conference on Compilers, architecture, and synthesis for embedded systems, Nov 2000, San Jose, United States. pp.41-47, ⟨10.1145/354880.354887⟩ |
|
|
|
Optimized Rapid Prototyping for Real-Time Embedded Heterogeneous Multiprocessorsthe seventh international workshop, 1999, Rome, France. ⟨10.1145/301177.301489⟩ |
Implementing Real-Time Algorithms by using the AAA Prototyping Methodology?. Embedded System Design, Techniques and Trends, 231, Springer, pp.27-36, 2007, IFIP |
|
|
Modèle d'exécutif distribué temps réel pour SynDEx[Rapport de recherche] RR-3476, INRIA. 1998 |
|
|
Adéquation Algorithme Architecture : Modélisations, Implémentations, Optimisations pour Applications Temps Réel EmbarquéesEmbedded Systems. Université Paris Est, 2024 |