Valentin Egloff
Maitre de conférences, Grenoble-INP UGA, ESISAR, LCIS
78%
Libre accès
9
Documents
Affiliation actuelle
- Laboratoire de Conception et d'Intégration des Systèmes (LCIS)
Identifiants chercheurs
Domaines de recherche
Architectures Matérielles [cs.AR]
Systèmes embarqués
Technologies Émergeantes [cs.ET]
Micro et nanotechnologies/Microélectronique
Cryptographie et sécurité [cs.CR]
Publications
Publications
Towards a truly integrated vector processing unit for memory-bound applications based on a cost-competitive computational SRAM design solutionACM Journal on Emerging Technologies in Computing Systems, 2022, 18 (2), pp.1-26. ⟨10.1145/3485823⟩
Article dans une revue
cea-04129882
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Inferred Fault Models for RISC-V and Arm: A Comparative Study37th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, Oct 2024, Oxfordshire, United Kingdom
Communication dans un congrès
hal-04726690
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Modeling Clock Glitch Fault Injection Effects on a RISC-V Microcontroller2024 IEEE 30th International Symposium on On-Line Testing and Robust System Design (IOLTS), Jul 2024, Rennes, France. ⟨10.1109/IOLTS60994.2024.10616064⟩
Communication dans un congrès
hal-04634303
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Invited Paper: An Automated Design Methodology for Computational SRAM Dedicated to Highly Data-Centric ApplicationsICCAD '22: IEEE/ACM International Conference on Computer-Aided Design, Nov 2022, San Diego California, France. pp.1-7, ⟨10.1145/3557988.3569715⟩
Communication dans un congrès
hal-04445922
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Storage class memory with computing row buffer: A design space exploration2021 Design, Automation & Test in Europe Conference & Exhibition (DATE), Feb 2021, grenoble, France. pp.1-6, ⟨10.23919/DATE51398.2021.9473992⟩
Communication dans un congrès
cea-03605068
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Computational SRAM Design Automation using Pushed-Rule Bitcells for Energy-Efficient Vector Processing2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), Mar 2020, Grenoble, France. pp.1187-1192, ⟨10.23919/DATE48585.2020.9116506⟩
Communication dans un congrès
cea-02889406
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Reconfigurable tiles of computing-in-memory SRAM architecture for scalable vectorizationISLPED 2020: ACM/IEEE International Symposium on Low Power Electronics and Design, Aug 2020, Boston, MA, United States. pp.121-126, ⟨10.1145/3370748.3406550⟩
Communication dans un congrès
cea-02963719
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Caractérisation métrologique d'un système de mesure de la photosynthese pour organes massifs2014, 45 p
Autre publication scientifique
hal-01192490
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Exploration and conception of computing architectures of type computing in-memory based on emerging non volatile memoriesMicro and nanotechnologies/Microelectronics. Aix-Marseille Université, 2022. English. ⟨NNT : 2022AIXM0446⟩
Thèse
tel-04055973
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